GPIO Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.420s	99.036us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	78.391us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.520s	53.717us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.460s	229.388us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	22.950us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.720s	43.426us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.480s	1.312ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	19.670us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.820s	76.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.720s	43.426us	20	20	100.00
		gpio_csr_aliasing	0.880s	19.670us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	63.913us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	145.153us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.060s	52.281us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.550s	377.117us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.710s	503.043us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.590s	355.726us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.050s	3.359ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.640s	2.175ms	50	50	100.00
V2	full_random	gpio_full_random	1.240s	133.978us	50	50	100.00
V2	stress_all	gpio_stress_all	3.746m	63.238ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	20.290us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	24.932us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.360s	499.221us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.360s	499.221us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.720s	43.426us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	154.082us	20	20	100.00
		gpio_csr_aliasing	0.880s	19.670us	5	5	100.00
		gpio_csr_hw_reset	0.660s	22.950us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.720s	43.426us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	154.082us	20	20	100.00
		gpio_csr_aliasing	0.880s	19.670us	5	5	100.00
		gpio_csr_hw_reset	0.660s	22.950us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.490s	386.568us	20	20	100.00
		gpio_sec_cm	0.980s	98.800us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.490s	386.568us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.673m	440.246ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			945	970	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:774) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 25 failures:
  • Test gpio_stress_all_with_rand_reset has 25 failures.

    • 8.gpio_stress_all_with_rand_reset.15674853324268676033411479687598313967497397020044237234513704710641493607221
      Line 5303, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 83199102037 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 83199102037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.gpio_stress_all_with_rand_reset.34148671341837580944822910985790888783357681823050470029995855985096085200269
      Line 2286, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/9.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45042241382 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 45042241382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

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