GPIO Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.390s	376.254us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.500s	1.359ms	50	50	100.00
		gpio_smoke_en_cdc_prim	1.500s	198.868us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	104.146us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	86.930us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.700s	45.554us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.510s	1.042ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	17.675us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.500s	34.627us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.700s	45.554us	20	20	100.00
		gpio_csr_aliasing	0.860s	17.675us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.300s	37.093us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.360s	78.361us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	57.561us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	179.112us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.450s	262.425us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.870s	190.141us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.040s	1.646ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.420s	978.213us	50	50	100.00
V2	full_random	gpio_full_random	1.130s	1.905ms	50	50	100.00
V2	stress_all	gpio_stress_all	3.855m	94.807ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	12.516us	50	50	100.00
V2	intr_test	gpio_intr_test	0.730s	16.291us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.770s	486.489us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.770s	486.489us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.700s	45.554us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	66.758us	20	20	100.00
		gpio_csr_aliasing	0.860s	17.675us	5	5	100.00
		gpio_csr_hw_reset	0.660s	86.930us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.700s	45.554us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	66.758us	20	20	100.00
		gpio_csr_aliasing	0.860s	17.675us	5	5	100.00
		gpio_csr_hw_reset	0.660s	86.930us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	589.812us	20	20	100.00
		gpio_sec_cm	1.120s	402.177us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	589.812us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.691m	216.513ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 1.gpio_stress_all_with_rand_reset.34194056504109542521155245435520126618079885635781048697176699565828643334824
      Line 402, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 643259225 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 643259225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.gpio_stress_all_with_rand_reset.89383294233815440465554631877958696502539375794609024386580637358775940696805
      Line 8253, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39731431096 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 39731431096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

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