GPIO Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.580s	345.114us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.580s	330.183us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	84.816us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.470s	420.684us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	56.851us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	17.223us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.280s	508.140us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	41.388us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.720s	88.651us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	17.223us	20	20	100.00
		gpio_csr_aliasing	0.920s	41.388us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	direct_and_masked_out	gpio_random_dout_din	1.480s	270.281us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.460s	803.643us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	159.742us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.510s	51.638us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.690s	128.211us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.050s	94.570us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.660s	6.338ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.850s	1.901ms	50	50	100.00
V2	full_random	gpio_full_random	1.110s	93.496us	50	50	100.00
V2	stress_all	gpio_stress_all	4.165m	33.539ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	12.345us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	70.584us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.300s	609.961us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.300s	609.961us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	17.223us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	171.015us	20	20	100.00
		gpio_csr_aliasing	0.920s	41.388us	5	5	100.00
		gpio_csr_hw_reset	0.660s	56.851us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	17.223us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	171.015us	20	20	100.00
		gpio_csr_aliasing	0.920s	41.388us	5	5	100.00
		gpio_csr_hw_reset	0.660s	56.851us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.670s	355.448us	20	20	100.00
		gpio_sec_cm	0.980s	306.035us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.670s	355.448us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.169m	377.576ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			937	970	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test gpio_stress_all_with_rand_reset has 31 failures.
  - 1.gpio_stress_all_with_rand_reset.15367374253804489279618550477514152909003593271305625459775316934394386722946
    Line 489, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1041172302 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1041172302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.41082981181517326051879827609859143644762756997468461839029668023931735667812
    Line 2389, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7840503482 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7840503482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test gpio_csr_mem_rw_with_rand_reset has 1 failures.

1.gpio_csr_mem_rw_with_rand_reset.65312847793298417166588395145361538592328641038501297718235434243422572249793
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_mem_rw_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077126337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4077126337
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Apr  2 12:26 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (cip_base_vseq.sv:753) [gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test gpio_stress_all_with_rand_reset has 1 failures.
  - 29.gpio_stress_all_with_rand_reset.48442086837877330945835891923268599755325655298384566596017093582135003784263
    Line 20493, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/29.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 233807879039 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 233807879039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```