GPIO Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.470s	134.751us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.580s	356.820us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.800s	145.317us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	58.301us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	78.507us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.710s	22.046us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.320s	3.702ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	116.469us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.780s	41.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.710s	22.046us	20	20	100.00
		gpio_csr_aliasing	0.880s	116.469us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	275.562us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.510s	287.038us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	69.959us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.560s	540.157us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.680s	131.792us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.750s	352.081us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.700s	3.205ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.570s	124.904us	50	50	100.00
V2	full_random	gpio_full_random	1.200s	196.802us	50	50	100.00
V2	stress_all	gpio_stress_all	3.620m	32.205ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	30.766us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	14.419us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.730s	326.825us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.730s	326.825us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.710s	22.046us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	35.305us	20	20	100.00
		gpio_csr_aliasing	0.880s	116.469us	5	5	100.00
		gpio_csr_hw_reset	0.660s	78.507us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.710s	22.046us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	35.305us	20	20	100.00
		gpio_csr_aliasing	0.880s	116.469us	5	5	100.00
		gpio_csr_hw_reset	0.660s	78.507us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.590s	121.489us	20	20	100.00
		gpio_sec_cm	0.940s	418.267us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.590s	121.489us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.160m	450.572ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test gpio_stress_all_with_rand_reset has 27 failures.

    • 0.gpio_stress_all_with_rand_reset.14174233727462892326226839421017063620000065408511125032706540858916631314216
      Line 5327, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 474441453524 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 474441453524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.39489598317554755513632054081446258425939052990149843052750159180356736623528
      Line 4326, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75904652676 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 75904652676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

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