GPIO Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.550s	96.719us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.450s	155.248us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.610s	104.395us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.440s	88.531us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	73.853us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	16.567us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.480s	810.489us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	32.316us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.980s	76.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	16.567us	20	20	100.00
		gpio_csr_aliasing	0.880s	32.316us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	328.401us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.310s	148.336us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.030s	52.770us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.580s	383.755us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.670s	168.696us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.840s	611.174us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.730s	2.269ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.050s	366.545us	50	50	100.00
V2	full_random	gpio_full_random	1.300s	178.671us	50	50	100.00
V2	stress_all	gpio_stress_all	3.463m	39.697ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	14.834us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	12.669us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.120s	754.030us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.120s	754.030us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	16.567us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	35.762us	20	20	100.00
		gpio_csr_aliasing	0.880s	32.316us	5	5	100.00
		gpio_csr_hw_reset	0.650s	73.853us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	16.567us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	35.762us	20	20	100.00
		gpio_csr_aliasing	0.880s	32.316us	5	5	100.00
		gpio_csr_hw_reset	0.650s	73.853us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.940s	1.006ms	20	20	100.00
		gpio_sec_cm	0.990s	1.018ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.940s	1.006ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.679m	523.174ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 0.gpio_stress_all_with_rand_reset.41402050027362632998598790830353276491825541213517997454383930732117863095097
      Line 2631, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8869498263 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8869498263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.102483287881448724269184261630186962861032921677375433632989849372886597663155
      Line 10081, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77134377572 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 77134377572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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