GPIO Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.590s	172.928us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.580s	84.421us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	195.007us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.630s	89.667us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	22.415us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	15.091us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.310s	1.336ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	64.131us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.680s	137.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	15.091us	20	20	100.00
		gpio_csr_aliasing	0.860s	64.131us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.610s	60.750us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.490s	149.495us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.040s	250.515us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.510s	210.126us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.890s	467.650us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.020s	92.720us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.980s	2.009ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.250s	930.220us	50	50	100.00
V2	full_random	gpio_full_random	1.220s	158.099us	50	50	100.00
V2	stress_all	gpio_stress_all	3.779m	16.382ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	15.248us	50	50	100.00
V2	intr_test	gpio_intr_test	0.710s	14.785us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.480s	167.443us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.480s	167.443us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	15.091us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	34.799us	20	20	100.00
		gpio_csr_aliasing	0.860s	64.131us	5	5	100.00
		gpio_csr_hw_reset	0.660s	22.415us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	15.091us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	34.799us	20	20	100.00
		gpio_csr_aliasing	0.860s	64.131us	5	5	100.00
		gpio_csr_hw_reset	0.660s	22.415us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	215.527us	20	20	100.00
		gpio_sec_cm	0.960s	591.966us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	215.527us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	35.073m	107.047ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test gpio_stress_all_with_rand_reset has 31 failures.

    • 0.gpio_stress_all_with_rand_reset.12693936781755858240544634897536129224222503368999271912333143761987154868138
      Line 5228, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25441786017 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25441786017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.66103217195215413845651566655937243546605731479986300352003990293466245114065
      Line 10011, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 116700436607 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 116700436607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

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