GPIO Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.460s	110.085us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	53.194us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.500s	83.370us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.700s	110.394us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	13.220us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.710s	22.472us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.240s	1.012ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	42.252us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.800s	37.846us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.710s	22.472us	20	20	100.00
		gpio_csr_aliasing	0.860s	42.252us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.330s	64.270us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.340s	111.866us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.920s	162.612us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.500s	52.684us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.710s	227.614us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.630s	86.351us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.880s	4.998ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.330s	1.105ms	50	50	100.00
V2	full_random	gpio_full_random	1.240s	87.883us	50	50	100.00
V2	stress_all	gpio_stress_all	3.587m	348.210ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	33.628us	50	50	100.00
V2	intr_test	gpio_intr_test	0.730s	13.568us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.500s	164.368us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.500s	164.368us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.710s	22.472us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	36.062us	20	20	100.00
		gpio_csr_aliasing	0.860s	42.252us	5	5	100.00
		gpio_csr_hw_reset	0.650s	13.220us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.710s	22.472us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	36.062us	20	20	100.00
		gpio_csr_aliasing	0.860s	42.252us	5	5	100.00
		gpio_csr_hw_reset	0.650s	13.220us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.840s	542.237us	20	20	100.00
		gpio_sec_cm	0.920s	423.930us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.840s	542.237us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.452m	257.277ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test gpio_stress_all_with_rand_reset has 32 failures.
  - 0.gpio_stress_all_with_rand_reset.11949517496960223805166031556128495286990163481568004189109847294934675901663
    Line 873, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1601720362 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1601720362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.45387596313865914735469936816948113128394603928645005122131004215435762975473
    Line 2016, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7472571088 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7472571088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.

GPIO Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1c75f24e99`