GPIO Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.400s	366.043us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	399.882us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.590s	55.715us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.430s	337.537us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	30.566us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	42.799us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.900s	303.822us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	72.469us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.550s	155.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	42.799us	20	20	100.00
		gpio_csr_aliasing	0.880s	72.469us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.320s	37.299us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	36.954us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	210.500us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	164.903us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.630s	148.010us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.540s	97.726us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.710s	516.742us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.210s	367.257us	50	50	100.00
V2	full_random	gpio_full_random	1.110s	103.628us	50	50	100.00
V2	stress_all	gpio_stress_all	3.659m	47.835ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.610s	15.478us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	99.861us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.450s	564.903us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.450s	564.903us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	42.799us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	215.504us	20	20	100.00
		gpio_csr_aliasing	0.880s	72.469us	5	5	100.00
		gpio_csr_hw_reset	0.700s	30.566us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	42.799us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	215.504us	20	20	100.00
		gpio_csr_aliasing	0.880s	72.469us	5	5	100.00
		gpio_csr_hw_reset	0.700s	30.566us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	378.076us	20	20	100.00
		gpio_sec_cm	0.970s	388.676us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	378.076us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.478m	613.145ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test gpio_stress_all_with_rand_reset has 32 failures.
  - 0.gpio_stress_all_with_rand_reset.33552462929089159788956932904223967344514865535308700921075541306618956861720
    Line 379, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 394878071 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 394878071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.65258082980471394785353304677102160581900482951753022837157118836492498566100
    Line 397, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 383757517 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 383757517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.

GPIO Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d3942ca074`