GPIO Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.460s 157.469us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.560s 179.722us 50 50 100.00
gpio_smoke_en_cdc_prim 1.490s 335.833us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.650s 51.883us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.640s 39.010us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 32.516us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.410s 1.547ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.850s 34.889us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.380s 28.186us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 32.516us 20 20 100.00
gpio_csr_aliasing 0.850s 34.889us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.450s 33.064us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.300s 48.966us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.960s 382.479us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.490s 394.490us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.930s 125.580us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.760s 336.203us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 29.430s 5.854ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 7.010s 1.086ms 50 50 100.00
V2 full_random gpio_full_random 1.120s 319.456us 50 50 100.00
V2 stress_all gpio_stress_all 3.771m 17.108ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 16.078us 50 50 100.00
V2 intr_test gpio_intr_test 0.690s 10.995us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.980s 292.454us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.980s 292.454us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 32.516us 20 20 100.00
gpio_same_csr_outstanding 0.960s 314.926us 20 20 100.00
gpio_csr_aliasing 0.850s 34.889us 5 5 100.00
gpio_csr_hw_reset 0.640s 39.010us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 32.516us 20 20 100.00
gpio_same_csr_outstanding 0.960s 314.926us 20 20 100.00
gpio_csr_aliasing 0.850s 34.889us 5 5 100.00
gpio_csr_hw_reset 0.640s 39.010us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.470s 280.637us 20 20 100.00
gpio_sec_cm 0.970s 192.101us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.470s 280.637us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 41.565m 476.086ms 22 50 44.00
V3 TOTAL 22 50 44.00
TOTAL 942 970 97.11

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results