GPIO Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	105.638us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.570s	392.672us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.600s	331.298us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.580s	320.354us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	21.660us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	26.017us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.320s	253.614us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.800s	29.710us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.860s	448.286us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	26.017us	20	20	100.00
		gpio_csr_aliasing	0.800s	29.710us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	61.001us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.360s	144.175us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	204.044us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.450s	141.047us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.470s	251.577us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.770s	152.835us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.210s	1.605ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.670s	577.365us	50	50	100.00
V2	full_random	gpio_full_random	1.110s	245.348us	50	50	100.00
V2	stress_all	gpio_stress_all	4.102m	45.906ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	91.891us	50	50	100.00
V2	intr_test	gpio_intr_test	0.700s	16.257us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.070s	59.496us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.070s	59.496us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	26.017us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	65.985us	20	20	100.00
		gpio_csr_aliasing	0.800s	29.710us	5	5	100.00
		gpio_csr_hw_reset	0.660s	21.660us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	26.017us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	65.985us	20	20	100.00
		gpio_csr_aliasing	0.800s	29.710us	5	5	100.00
		gpio_csr_hw_reset	0.660s	21.660us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	384.716us	20	20	100.00
		gpio_sec_cm	1.060s	342.465us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	384.716us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.189m	100.190ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			947	970	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test gpio_stress_all_with_rand_reset has 23 failures.

    • 0.gpio_stress_all_with_rand_reset.115032599510357008688080049459089577346667631209589179865389277825747637580923
      Line 1792, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23869308684 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23869308684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.39673146286926892214613056555285843609034520472459293763106761566180982284147
      Line 15130, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 471770985291 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 471770985291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

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