GPIO Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.610s	100.720us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.610s	58.721us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.610s	86.121us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.640s	81.878us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	21.390us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	14.577us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.570s	395.198us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	31.347us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.640s	70.707us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	14.577us	20	20	100.00
		gpio_csr_aliasing	0.860s	31.347us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.440s	52.667us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	82.546us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	69.800us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	441.789us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.160s	553.870us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.860s	90.196us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.460s	1.019ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.560s	482.261us	50	50	100.00
V2	full_random	gpio_full_random	1.130s	1.612ms	50	50	100.00
V2	stress_all	gpio_stress_all	4.058m	81.422ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	14.750us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	48.422us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.470s	1.344ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.470s	1.344ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	14.577us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	67.909us	20	20	100.00
		gpio_csr_aliasing	0.860s	31.347us	5	5	100.00
		gpio_csr_hw_reset	0.690s	21.390us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	14.577us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	67.909us	20	20	100.00
		gpio_csr_aliasing	0.860s	31.347us	5	5	100.00
		gpio_csr_hw_reset	0.690s	21.390us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	944.532us	20	20	100.00
		gpio_sec_cm	0.880s	228.595us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	944.532us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.290m	101.969ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			944	970	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test gpio_stress_all_with_rand_reset has 26 failures.
  - 0.gpio_stress_all_with_rand_reset.44974145827556258957118827830140288510802375706025573943339505647259007693753
    Line 963, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3390431301 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3390431301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.67132167959648480706281743875168446163224082373769801042762882053085480501960
    Line 1702, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11916222897 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11916222897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.

GPIO Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`