GPIO Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.470s	190.859us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	106.404us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.750s	1.292ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.700s	50.804us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	85.221us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	19.406us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.420s	257.401us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.790s	273.276us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.270s	30.253us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	19.406us	20	20	100.00
		gpio_csr_aliasing	0.790s	273.276us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	35.865us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	880.914us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	52.491us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.520s	476.227us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.590s	113.961us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.100s	97.073us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.070s	483.294us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.560s	803.356us	50	50	100.00
V2	full_random	gpio_full_random	1.180s	1.745ms	50	50	100.00
V2	stress_all	gpio_stress_all	3.818m	20.318ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	23.651us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	31.392us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.040s	177.557us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.040s	177.557us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	19.406us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	244.179us	20	20	100.00
		gpio_csr_aliasing	0.790s	273.276us	5	5	100.00
		gpio_csr_hw_reset	0.680s	85.221us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	19.406us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	244.179us	20	20	100.00
		gpio_csr_aliasing	0.790s	273.276us	5	5	100.00
		gpio_csr_hw_reset	0.680s	85.221us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	115.773us	20	20	100.00
		gpio_sec_cm	0.960s	479.431us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	115.773us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.386m	438.465ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 1.gpio_stress_all_with_rand_reset.97963091938253124165981805418268447792781716617295235395670772361066800341707
      Line 834, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4267325661 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4267325661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.42963915690887946234387259341252243631526382210234022014439584094311400736421
      Line 575, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1118316025 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1118316025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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