GPIO Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.450s	80.984us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	103.659us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.530s	348.869us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.450s	198.768us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.640s	11.916us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	44.173us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.280s	1.119ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	39.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.300s	109.894us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	44.173us	20	20	100.00
		gpio_csr_aliasing	0.880s	39.123us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	74.821us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	59.967us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.940s	184.889us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.420s	110.380us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.370s	255.041us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.660s	735.668us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.750s	1.049ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.540s	3.387ms	50	50	100.00
V2	full_random	gpio_full_random	1.100s	399.346us	50	50	100.00
V2	stress_all	gpio_stress_all	3.629m	32.681ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	19.987us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	24.585us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.600s	106.167us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.600s	106.167us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	44.173us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	117.387us	20	20	100.00
		gpio_csr_aliasing	0.880s	39.123us	5	5	100.00
		gpio_csr_hw_reset	0.640s	11.916us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	44.173us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	117.387us	20	20	100.00
		gpio_csr_aliasing	0.880s	39.123us	5	5	100.00
		gpio_csr_hw_reset	0.640s	11.916us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	279.128us	20	20	100.00
		gpio_sec_cm	1.090s	742.788us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	279.128us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	39.991m	469.546ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test gpio_stress_all_with_rand_reset has 29 failures.
  - 0.gpio_stress_all_with_rand_reset.97163754522317939127632151993275821092559689033683239763281211104540437270927
    Line 4222, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 228079610035 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 228079610035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.100705769956646062069843234916833749305550582088004894410219807555630271432997
    Line 4828, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 152346797272 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 152346797272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

GPIO Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`