GPIO Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.470s	240.799us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.560s	197.745us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.590s	103.566us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.590s	103.846us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	18.494us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	43.786us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.880s	325.389us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.830s	36.691us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.760s	103.066us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	43.786us	20	20	100.00
		gpio_csr_aliasing	0.830s	36.691us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.460s	303.897us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	225.357us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	48.082us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.600s	425.416us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.580s	121.665us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.890s	1.762ms	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.890s	2.859ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.420s	2.484ms	50	50	100.00
V2	full_random	gpio_full_random	1.150s	91.403us	50	50	100.00
V2	stress_all	gpio_stress_all	3.515m	11.846ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	25.377us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	125.672us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.340s	197.406us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.340s	197.406us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	43.786us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	84.524us	20	20	100.00
		gpio_csr_aliasing	0.830s	36.691us	5	5	100.00
		gpio_csr_hw_reset	0.690s	18.494us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	43.786us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	84.524us	20	20	100.00
		gpio_csr_aliasing	0.830s	36.691us	5	5	100.00
		gpio_csr_hw_reset	0.690s	18.494us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	131.177us	20	20	100.00
		gpio_sec_cm	0.960s	94.099us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	131.177us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.764m	1.445s	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			947	970	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test gpio_stress_all_with_rand_reset has 23 failures.
  - 2.gpio_stress_all_with_rand_reset.52217135556563212958556020143533378728297101837688282916229621986822833533927
    Line 11296, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137277810086 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137277810086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.78996027616088242912739146322737638203824839134141275974393851009820157365946
    Line 5455, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79270622522 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 79270622522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

GPIO Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9ae10fb42`