GPIO Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.710s	430.219us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.440s	247.275us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	106.038us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.450s	63.331us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.630s	13.526us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	58.829us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.290s	1.549ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	233.065us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.630s	34.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	58.829us	20	20	100.00
		gpio_csr_aliasing	0.870s	233.065us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.280s	109.345us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.260s	214.114us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	51.249us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.430s	210.781us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.330s	589.804us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.580s	91.779us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.100s	3.698ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.840s	1.533ms	50	50	100.00
V2	full_random	gpio_full_random	1.010s	88.374us	50	50	100.00
V2	stress_all	gpio_stress_all	3.688m	16.594ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	35.394us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	77.473us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.350s	208.289us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.350s	208.289us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	58.829us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	34.569us	20	20	100.00
		gpio_csr_aliasing	0.870s	233.065us	5	5	100.00
		gpio_csr_hw_reset	0.630s	13.526us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	58.829us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	34.569us	20	20	100.00
		gpio_csr_aliasing	0.870s	233.065us	5	5	100.00
		gpio_csr_hw_reset	0.630s	13.526us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	633.041us	20	20	100.00
		gpio_sec_cm	0.990s	627.733us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	633.041us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	39.149m	492.772ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test gpio_stress_all_with_rand_reset has 27 failures.

    • 0.gpio_stress_all_with_rand_reset.30314918559290726588495664610176484130345163555943467212495635538512707792396
      Line 6673, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63282493216 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 63282493216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.9694807692871841654415169973203540120166162418264491070335170990317440057450
      Line 3824, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 74171387194 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 74171387194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

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