GPIO Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.450s	443.655us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.440s	135.860us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.580s	315.240us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.580s	207.273us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	17.001us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	46.547us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.210s	875.441us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	91.588us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.540s	33.104us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	46.547us	20	20	100.00
		gpio_csr_aliasing	0.890s	91.588us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	116.191us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.360s	318.095us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	92.020us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	762.102us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.750s	472.280us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.810s	278.284us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.950s	3.673ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.050s	2.637ms	50	50	100.00
V2	full_random	gpio_full_random	1.100s	234.961us	50	50	100.00
V2	stress_all	gpio_stress_all	3.784m	8.059ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	24.751us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	11.637us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.930s	2.265ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.930s	2.265ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	46.547us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	27.031us	20	20	100.00
		gpio_csr_aliasing	0.890s	91.588us	5	5	100.00
		gpio_csr_hw_reset	0.720s	17.001us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	46.547us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	27.031us	20	20	100.00
		gpio_csr_aliasing	0.890s	91.588us	5	5	100.00
		gpio_csr_hw_reset	0.720s	17.001us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.530s	224.981us	20	20	100.00
		gpio_sec_cm	1.050s	117.304us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.530s	224.981us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	50.270m	511.944ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test gpio_stress_all_with_rand_reset has 27 failures.
  - 1.gpio_stress_all_with_rand_reset.105339742615184444306088143672375117909523585685662825530948613331102500603668
    Line 8024, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209339515876 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 209339515876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.112100622778682968668520097695346169486222004768535118436958467001268503133408
    Line 1363, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12716096234 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12716096234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

GPIO Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c42c47ec2d`