HMAC Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.520s	342.668us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.750s	36.754us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	152.087us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.940s	652.583us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.520s	601.606us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.713m	7.901ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	152.087us	20	20	100.00
		hmac_csr_aliasing	2.520s	601.606us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.709m	7.601ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.026m	8.084ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	7.995m	44.871ms	48	50	96.00
		hmac_test_hmac_vectors	1.200s	299.938us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.128m	6.107ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.584m	3.556ms	50	50	100.00
V2	error	hmac_error	3.444m	62.972ms	48	50	96.00
V2	wipe_secret	hmac_wipe_secret	1.566m	8.221ms	50	50	100.00
V2	stress_all	hmac_stress_all	36.023m	209.192ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	24.851us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	12.229us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.590s	68.435us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.590s	68.435us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.750s	36.754us	5	5	100.00
		hmac_csr_rw	0.760s	152.087us	20	20	100.00
		hmac_csr_aliasing	2.520s	601.606us	5	5	100.00
		hmac_same_csr_outstanding	1.360s	156.142us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.750s	36.754us	5	5	100.00
		hmac_csr_rw	0.760s	152.087us	20	20	100.00
		hmac_csr_aliasing	2.520s	601.606us	5	5	100.00
		hmac_same_csr_outstanding	1.360s	156.142us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	1.480s	1.664ms	5	5	100.00
		hmac_tl_intg_err	2.880s	620.673us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.880s	620.673us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.520s	342.668us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.405h	2.174s	190	200	95.00
V3		TOTAL			190	200	95.00
		TOTAL			906	920	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.60	99.54	98.58	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 7 failures:

Test hmac_stress_all_with_rand_reset has 7 failures.

0.hmac_stress_all_with_rand_reset.4141587189
Line 921, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47148748466 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 47148748466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

57.hmac_stress_all_with_rand_reset.1744088989
Line 392, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/57.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42001655878 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42001655878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test hmac_error has 2 failures.

0.hmac_error.1755557721
Line 249, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.hmac_error.2967833540
Line 253, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/23.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test hmac_test_sha_vectors has 2 failures.

17.hmac_test_sha_vectors.1321104792
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.hmac_test_sha_vectors.50036488
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 26.hmac_stress_all_with_rand_reset.174469667
    Line 1282, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100237476111 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 100237476111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 44.hmac_stress_all_with_rand_reset.2962888053
    Line 466, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181206326369 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 181206326369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 129.hmac_stress_all_with_rand_reset.1353457547
    Line 219, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/129.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   2454879 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @   2454879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```