HMAC Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.680s	441.391us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.690s	18.315us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.800s	21.731us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.370s	1.002ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.550s	1.066ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.527m	86.295ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.800s	21.731us	20	20	100.00
		hmac_csr_aliasing	2.550s	1.066ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.859m	36.111ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	52.990s	13.454ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.375m	151.725ms	47	50	94.00
		hmac_test_hmac_vectors	1.240s	228.202us	50	50	100.00
V2	burst_wr	hmac_burst_wr	58.930s	5.180ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.294m	33.641ms	50	50	100.00
V2	error	hmac_error	3.877m	34.229ms	49	50	98.00
V2	wipe_secret	hmac_wipe_secret	1.420m	11.187ms	50	50	100.00
V2	stress_all	hmac_stress_all	37.556m	193.694ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	41.709us	50	50	100.00
V2	intr_test	hmac_intr_test	0.620s	17.340us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.940s	222.840us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.940s	222.840us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.690s	18.315us	5	5	100.00
		hmac_csr_rw	0.800s	21.731us	20	20	100.00
		hmac_csr_aliasing	2.550s	1.066ms	5	5	100.00
		hmac_same_csr_outstanding	1.380s	85.018us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.690s	18.315us	5	5	100.00
		hmac_csr_rw	0.800s	21.731us	20	20	100.00
		hmac_csr_aliasing	2.550s	1.066ms	5	5	100.00
		hmac_same_csr_outstanding	1.380s	85.018us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	0.960s	101.431us	5	5	100.00
		hmac_tl_intg_err	3.080s	2.921ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.080s	2.921ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.680s	441.391us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.555h	253.507ms	193	200	96.50
V3		TOTAL			193	200	96.50
		TOTAL			909	920	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.53	98.58	100.00	100.00	99.76	99.49	100.00

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:
- Test hmac_stress_all_with_rand_reset has 5 failures.
  - 16.hmac_stress_all_with_rand_reset.80609317104955404293527058183555851207167010233709899573859267020295122376147
    Line 766, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 155595487255 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 155595487255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 102.hmac_stress_all_with_rand_reset.87707167829522668653644504237395381592642405811154367318002355492483109575689
    Line 1217, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/102.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74951149236 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 74951149236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test hmac_error has 1 failures.
  - 5.hmac_error.16273943273866219255490458914107598730395175207143009641561156457804635426966
    Line 293, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha_vectors has 3 failures.
  - 21.hmac_test_sha_vectors.16556029771273172873897413065814057171902242675921457037918650990445249608776
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.hmac_test_sha_vectors.57540377722187657712162694708055483688357451066179538455222863913281473864965
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/40.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 20.hmac_stress_all_with_rand_reset.44853521882588640023516574071948794625784256527177346595704239252450473568590
    Line 261, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 982676314 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 982676314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 181.hmac_stress_all_with_rand_reset.104578921503936928308082237117839882808838800355939666977440014635784476931348
    Line 751, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/181.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 142538466670 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 142538466670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `748235cbb6`