HMAC Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.550s	1.066ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.770s	49.649us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.750s	101.936us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.050s	810.546us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.550s	656.183us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	2.850s	52.512us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.750s	101.936us	20	20	100.00
		hmac_csr_aliasing	2.550s	656.183us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.008m	39.049ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.124m	1.688ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.431m	180.676ms	48	50	96.00
		hmac_test_hmac_vectors	1.300s	271.825us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.236m	8.545ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.493m	6.049ms	50	50	100.00
V2	error	hmac_error	3.109m	16.458ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.384m	14.356ms	50	50	100.00
V2	stress_all	hmac_stress_all	48.435m	172.812ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.680s	12.106us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	29.993us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.560s	196.651us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.560s	196.651us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.770s	49.649us	5	5	100.00
		hmac_csr_rw	0.750s	101.936us	20	20	100.00
		hmac_csr_aliasing	2.550s	656.183us	5	5	100.00
		hmac_same_csr_outstanding	1.510s	461.806us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.770s	49.649us	5	5	100.00
		hmac_csr_rw	0.750s	101.936us	20	20	100.00
		hmac_csr_aliasing	2.550s	656.183us	5	5	100.00
		hmac_same_csr_outstanding	1.510s	461.806us	20	20	100.00
V2		TOTAL			588	590	99.66
V2S	tl_intg_err	hmac_sec_cm	1.020s	366.259us	5	5	100.00
		hmac_tl_intg_err	2.570s	169.218us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.570s	169.218us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.550s	1.066ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.620h	144.463ms	12	200	6.00
V3		TOTAL			12	200	6.00
		TOTAL			730	920	79.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.63	98.23	96.36	100.00	87.50	95.49	99.49	99.31

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 178 failures:
- Test hmac_stress_all_with_rand_reset has 178 failures.
  - 1.hmac_stress_all_with_rand_reset.59135834299913102057588234827347158370258782018997204984127194107067022041568
    Line 300, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5541849299 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5541849299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.hmac_stress_all_with_rand_reset.33499421960363912393219611935359387537767532143357473885285759073869614935211
    Line 304, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14191422153 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14191422153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 176 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 10 failures:
- Test hmac_stress_all_with_rand_reset has 10 failures.
  - 47.hmac_stress_all_with_rand_reset.29223773005841747610607999683449285483354585238849921042172364484384337057875
    Line 381, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24763258459 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 24763258459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.hmac_stress_all_with_rand_reset.33057187373208984582154182503293986758172047018025814962472593846640967221471
    Line 885, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/54.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32960317533 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 32960317533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test hmac_test_sha_vectors has 2 failures.
  - 27.hmac_test_sha_vectors.99512809050125691527224834698425652065139174626825029113019020978484324105877
    Line 427, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.hmac_test_sha_vectors.102395243683755206237873351978347888848063413025192099830519543286427437487370
    Line 345, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c30684b3ca`