HMAC Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.640s	2.139ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.750s	421.534us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.820s	80.176us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.830s	380.793us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.530s	302.918us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.766m	233.021ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.820s	80.176us	20	20	100.00
		hmac_csr_aliasing	2.530s	302.918us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.845m	14.407ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.060m	3.707ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.193m	97.213ms	46	50	92.00
		hmac_test_hmac_vectors	1.320s	132.696us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.543m	3.754ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.502m	12.013ms	50	50	100.00
V2	error	hmac_error	2.985m	41.669ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.732m	32.541ms	50	50	100.00
V2	stress_all	hmac_stress_all	31.196m	74.735ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	26.447us	50	50	100.00
V2	intr_test	hmac_intr_test	0.710s	13.574us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.860s	731.963us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.860s	731.963us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.750s	421.534us	5	5	100.00
		hmac_csr_rw	0.820s	80.176us	20	20	100.00
		hmac_csr_aliasing	2.530s	302.918us	5	5	100.00
		hmac_same_csr_outstanding	1.510s	270.826us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.750s	421.534us	5	5	100.00
		hmac_csr_rw	0.820s	80.176us	20	20	100.00
		hmac_csr_aliasing	2.530s	302.918us	5	5	100.00
		hmac_same_csr_outstanding	1.510s	270.826us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	0.930s	104.705us	5	5	100.00
		hmac_tl_intg_err	2.550s	167.551us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.550s	167.551us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.640s	2.139ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.331h	668.279ms	9	200	4.50
V3		TOTAL			9	200	4.50
		TOTAL			725	920	78.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	98.36	96.53	100.00	87.50	95.83	99.49	99.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 180 failures:
- Test hmac_stress_all_with_rand_reset has 180 failures.
  - 0.hmac_stress_all_with_rand_reset.88617060176065340735828212894641325757222803581936607349753981212287406971439
    Line 633, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4669551185 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4669551185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.59997923135677641707127410286975225978152430882913526996280872598242227506892
    Line 367, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48855525868 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48855525868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 178 more failures.
UVM_ERROR (cip_base_vseq.sv:719) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 11 failures:
- Test hmac_stress_all_with_rand_reset has 11 failures.
  - 12.hmac_stress_all_with_rand_reset.71889176173852572422656690809699882314926713148451665426852557482671357361452
    Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  53858804 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  53858804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.hmac_stress_all_with_rand_reset.79212336672794641482755964790239990015881796505569938632737898168634343063235
    Line 254, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1236499475 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1236499475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test hmac_test_sha_vectors has 4 failures.
  - 6.hmac_test_sha_vectors.78290990028865872368120526469599630702818530826364838502644492807750468009559
    Line 335, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.hmac_test_sha_vectors.16669614025670061974637851200744003423035873143853318747827095779211544808419
    Line 381, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

HMAC Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e0c4026501`