HMAC Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.570s	411.784us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.690s	35.801us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.770s	22.985us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.090s	975.408us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.660s	512.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	22.384m	605.748ms	14	20	70.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.770s	22.985us	20	20	100.00
		hmac_csr_aliasing	2.660s	512.571us	5	5	100.00
V1		TOTAL			99	105	94.29
V2	long_msg	hmac_long_msg	1.803m	2.020ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.075m	1.804ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.468m	132.919ms	47	50	94.00
		hmac_test_hmac_vectors	1.240s	258.640us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.241m	17.655ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.543m	40.849ms	50	50	100.00
V2	error	hmac_error	3.806m	14.701ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.417m	2.411ms	50	50	100.00
V2	stress_all	hmac_stress_all	34.864m	158.234ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	12.666us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	12.079us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.780s	401.300us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.780s	401.300us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.690s	35.801us	5	5	100.00
		hmac_csr_rw	0.770s	22.985us	20	20	100.00
		hmac_csr_aliasing	2.660s	512.571us	5	5	100.00
		hmac_same_csr_outstanding	1.550s	92.499us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.690s	35.801us	5	5	100.00
		hmac_csr_rw	0.770s	22.985us	20	20	100.00
		hmac_csr_aliasing	2.660s	512.571us	5	5	100.00
		hmac_same_csr_outstanding	1.550s	92.499us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	0.950s	339.704us	5	5	100.00
		hmac_tl_intg_err	2.460s	342.792us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.460s	342.792us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.570s	411.784us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.171h	370.441ms	9	200	4.50
V3		TOTAL			9	200	4.50
		TOTAL			720	920	78.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.38	99.55	98.55	100.00	100.00	98.47	99.49	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [hmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.

has 178 failures:

Test hmac_stress_all_with_rand_reset has 172 failures.

0.hmac_stress_all_with_rand_reset.94135814763865594946903702050883160905559413872738922638139991254622491872293
Line 591, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12282956270 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 12282956270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.hmac_stress_all_with_rand_reset.107745339899167453418107996409350430979073507267402672826264436165251866398586
Line 504, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15488539842 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 15488539842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 170 more failures.

Test hmac_csr_mem_rw_with_rand_reset has 6 failures.

7.hmac_csr_mem_rw_with_rand_reset.50304294965848149452843084716252906150603798055796574659133273634964186155089
Line 250, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 242241628 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 242241628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.hmac_csr_mem_rw_with_rand_reset.77466181505539702253005779214844280585732671820178855551249286925734776639296
Line 256, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 360709623 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 360709623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:714) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 19 failures:
- Test hmac_stress_all_with_rand_reset has 19 failures.
  - 7.hmac_stress_all_with_rand_reset.50196906807902771004049428392339211569558312888788379176778852141671439264211
    Line 364, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3722813402 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3722813402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.hmac_stress_all_with_rand_reset.39889735223690107819154821795479058722654890775871850213169727775563976299093
    Line 250, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  76926827 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  76926827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test hmac_test_sha_vectors has 3 failures.
  - 27.hmac_test_sha_vectors.63911239390700562885880055334632885480017853646837099043750370181711440579018
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.hmac_test_sha_vectors.69075559314459132667738048737421776024323098854317919875533505839418932516658
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.