HMAC Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.620s	382.027us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.970s	93.767us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.790s	15.405us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.060s	2.486ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.560s	561.584us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	19.779m	537.819ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.790s	15.405us	20	20	100.00
		hmac_csr_aliasing	2.560s	561.584us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.956m	108.786ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.006m	1.743ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.319m	123.862ms	47	50	94.00
		hmac_test_hmac_vectors	1.290s	31.355us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.243m	6.562ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.844m	3.225ms	50	50	100.00
V2	error	hmac_error	3.459m	25.195ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.492m	4.436ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.984m	757.578ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	53.536us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	14.669us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.510s	727.706us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.510s	727.706us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.970s	93.767us	5	5	100.00
		hmac_csr_rw	0.790s	15.405us	20	20	100.00
		hmac_csr_aliasing	2.560s	561.584us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	71.332us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.970s	93.767us	5	5	100.00
		hmac_csr_rw	0.790s	15.405us	20	20	100.00
		hmac_csr_aliasing	2.560s	561.584us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	71.332us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	0.950s	451.296us	5	5	100.00
		hmac_tl_intg_err	2.610s	412.134us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.610s	412.134us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.620s	382.027us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.075h	373.764ms	17	200	8.50
V3		TOTAL			17	200	8.50
		TOTAL			734	920	79.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	98.36	96.63	100.00	90.62	95.83	99.49	99.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 170 failures:
- Test hmac_stress_all_with_rand_reset has 170 failures.
  - 0.hmac_stress_all_with_rand_reset.51959379689861102122312137119632222339580044577578714005074896320238747170343
    Line 316, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6726996694 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6726996694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.17932696004602452421766308511615637021381517934515052040715110325629702799591
    Line 262, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2236590226 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2236590226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 168 more failures.
UVM_ERROR (cip_base_vseq.sv:719) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 13 failures:
- Test hmac_stress_all_with_rand_reset has 13 failures.
  - 47.hmac_stress_all_with_rand_reset.34045833362681659041354174643383606723501897606961955564131924868763659181057
    Line 524, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15937755120 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15937755120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.hmac_stress_all_with_rand_reset.115534443328578180213336495874510414946239542691360143682956631417690838652624
    Line 858, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/51.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17705258197 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17705258197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test hmac_test_sha_vectors has 3 failures.
  - 15.hmac_test_sha_vectors.79375430674520076225239899836392548542900316127305816019848129168172890817346
    Line 414, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.hmac_test_sha_vectors.104969298804529727643961587689967428227270966117319324866457027714960404123180
    Line 405, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

HMAC Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `32ed2c4230`