HMAC Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.660s	1.306ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	19.482us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.780s	101.789us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	6.840s	2.494ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.510s	136.870us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	8.566m	109.559ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.780s	101.789us	20	20	100.00
		hmac_csr_aliasing	2.510s	136.870us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.461m	11.737ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.008m	10.228ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.718m	44.364ms	47	50	94.00
		hmac_test_hmac_vectors	1.330s	71.077us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.193m	1.475ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.959m	3.466ms	50	50	100.00
V2	error	hmac_error	3.284m	78.473ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.354m	25.990ms	50	50	100.00
V2	stress_all	hmac_stress_all	33.879m	117.105ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	80.247us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	24.373us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.720s	209.352us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.720s	209.352us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	19.482us	5	5	100.00
		hmac_csr_rw	0.780s	101.789us	20	20	100.00
		hmac_csr_aliasing	2.510s	136.870us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	271.109us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	19.482us	5	5	100.00
		hmac_csr_rw	0.780s	101.789us	20	20	100.00
		hmac_csr_aliasing	2.510s	136.870us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	271.109us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	0.990s	342.692us	5	5	100.00
		hmac_tl_intg_err	2.580s	624.522us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.580s	624.522us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.660s	1.306ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	57.630m	146.589ms	11	200	5.50
V3		TOTAL			11	200	5.50
		TOTAL			728	920	79.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.80	99.55	98.65	100.00	96.30	98.47	99.49	99.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 176 failures:
- Test hmac_stress_all_with_rand_reset has 176 failures.
  - 0.hmac_stress_all_with_rand_reset.32570867405369072673956758491464862726591730134139430049639653701031302624874
    Line 1091, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 93516296711 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 93516296711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.47677873600053369151151667172016519740279336556086770390565043697197686619188
    Line 434, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5420176164 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 5420176164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 174 more failures.
UVM_ERROR (cip_base_vseq.sv:719) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 13 failures:
- Test hmac_stress_all_with_rand_reset has 13 failures.
  - 3.hmac_stress_all_with_rand_reset.60907974070008395305349897528088899902131221957038861329981709354961081343721
    Line 639, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13191434475 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13191434475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.hmac_stress_all_with_rand_reset.17084020172183855152437207781375629995197055725770326227126892920645988060620
    Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  54484028 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  54484028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test hmac_test_sha_vectors has 3 failures.
  - 6.hmac_test_sha_vectors.30611024260378451956751155225385010157635914208760663322943342710325353329339
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.hmac_test_sha_vectors.24809289510759040751994231888145472482565405791295340619211403738915701334102
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

HMAC Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `49a27e136c`