HMAC Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.060s	623.800us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.030s	85.858us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.960s	120.279us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.930s	481.557us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.900s	618.266us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.371m	66.448ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.960s	120.279us	20	20	100.00
		hmac_csr_aliasing	7.900s	618.266us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.031m	8.768ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.152m	1.828ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.626m	137.205ms	50	50	100.00
		hmac_test_hmac_vectors	1.390s	1.068ms	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.225m	3.062ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.883m	2.865ms	50	50	100.00
V2	error	hmac_error	4.592m	82.964ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.377m	5.558ms	50	50	100.00
V2	stress_all	hmac_stress_all	51.190m	170.133ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.610s	43.890us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	40.510us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.120s	188.833us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.120s	188.833us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.030s	85.858us	5	5	100.00
		hmac_csr_rw	0.960s	120.279us	20	20	100.00
		hmac_csr_aliasing	7.900s	618.266us	5	5	100.00
		hmac_same_csr_outstanding	2.260s	533.746us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.030s	85.858us	5	5	100.00
		hmac_csr_rw	0.960s	120.279us	20	20	100.00
		hmac_csr_aliasing	7.900s	618.266us	5	5	100.00
		hmac_same_csr_outstanding	2.260s	533.746us	20	20	100.00
V2		TOTAL			589	590	99.83
V2S	tl_intg_err	hmac_sec_cm	1.000s	167.661us	5	5	100.00
		hmac_tl_intg_err	4.570s	1.673ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.570s	1.673ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.060s	623.800us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.301h	393.613ms	17	200	8.50
V3		TOTAL			17	200	8.50
		TOTAL			736	920	80.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.39	92.80	85.92	100.00	76.32	88.15	99.49	69.08

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 181 failures:
- Test hmac_stress_all_with_rand_reset has 181 failures.
  - 0.hmac_stress_all_with_rand_reset.91434780597455002285190876108196765549199436623953076923426835906087264566032
    Line 25190, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56264374885 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56264374885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.11895190410252117208427081499925606198428620867696419618959516812671441965809
    Line 85791, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 214452614576 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 214452614576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 179 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 45.hmac_stress_all_with_rand_reset.74354488252463404703592918691083734459939952426028366501096171537120290176755
    Line 108300, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10842932590 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 10842932590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.hmac_stress_all_with_rand_reset.12537364957616499942399497543241909687981012514940034466332602884167787807778
    Line 13743, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/94.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8601591727 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8601591727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:289) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all has 1 failures.
  - 34.hmac_stress_all.54890490360863255010469001552389107399193342809474798426169402311880350865200
    Line 101102, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 61165266167 ps: (hmac_scoreboard.sv:289) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1271635200 [0x4bcb9d00])
  UVM_INFO @ 61165266167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `36c168c253`