Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.42	95.81	80.59	100.00	40.00	90.11	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	84.91	95.81	83.54	100.00	40.00	90.11	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.91	95.81	83.54	100.00	40.00	90.11	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.44	95.76	94.06	100.00	73.68	91.67	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	94.00	95.33	92.05		100.00	88.61
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	88.21	97.82	92.96		72.00	90.05
u_reg	98.22	94.80	97.60	100.00		98.72	100.00
u_tlul_adapter	88.86	94.06	88.52			80.25	92.59

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		191	183	95.81
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	148	15	9	60.00
ALWAYS	189	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
ALWAYS	201	7	7	100.00
ALWAYS	215	3	3	100.00
ALWAYS	225	0	0
ALWAYS	225	21	21	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
ALWAYS	274	4	4	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	289	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	295	6	6	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
ALWAYS	336	6	6	100.00
ALWAYS	346	4	4	100.00
ALWAYS	381	6	6	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
ALWAYS	450	5	5	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	583	1	1	100.00
ALWAYS	588	3	3	100.00
ALWAYS	596	3	3	100.00
ALWAYS	601	10	8	80.00
CONT_ASSIGN	618	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
ALWAYS	779	6	6	100.00
CONT_ASSIGN	795	1	1	100.00
ALWAYS	800	7	7	100.00
CONT_ASSIGN	841	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
ALWAYS	847	3	3	100.00
CONT_ASSIGN	853	1	1	100.00
ALWAYS	875	6	6	100.00
ALWAYS	882	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
135	1	1
136	1	1
148	1	1
149	1	1
151	1	1
153	1	1
155	1	1
156	1	1
158	0	1
			MISSING_ELSE
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	0	1
173	0	1
			==> MISSING_ELSE
178	0	1
179	0	1
180	0	1
			==> MISSING_ELSE
189	1	1
190	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
203	1	1
204	1	1
206	1	1
207	1	1
208	1	1
			MISSING_ELSE
			MISSING_ELSE
215	2	2
216	1	1
225	1	1
227	1	1
229	1	1
230	1	1
			MISSING_ELSE
233	1	1
235	1	1
236	1	1
238	1	1
240	1	1
241	1	1
243	1	1
245	1	1
246	1	1
248	1	1
249	1	1
251	1	1
252	1	1
254	1	1
255	1	1
257	1	1
258	1	1
			MISSING_ELSE
265	1	1
269	1	1
270	1	1
272	1	1
274	1	1
275	1	1
276	1	1
277	1	1
286	1	1
289	2	2
290	1	1
293	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
308	1	1
309	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
318	1	1
319	1	1
320	1	1
321	1	1
324	1	1
325	1	1
330	1	1
331	1	1
332	1	1
333	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
346	1	1
347	1	1
374	1	1
375	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE
430	1	1
437	1	1
445	1	1
447	1	1
450	1	1
451	1	1
452	1	1
454	1	1
455	1	1
491	1	1
494	1	1
500	1	1
505	1	1
506	1	1
508	1	1
509	1	1
510	1	1
514	1	1
515	1	1
516	1	1
518	1	1
519	1	1
521	1	1
522	1	1
			==> MISSING_ELSE
525	1	1
583	1	1
588	1	1
589	1	1
590	1	1
596	2	2
597	1	1
601	1	1
602	1	1
603	1	1
604	0	1
			MISSING_ELSE
606	1	1
607	0	1
			MISSING_ELSE
			MISSING_ELSE
611	1	1
612	1	1
613	1	1
614	1	1
			MISSING_ELSE
618	1	1
619	1	1
626	1	1
627	1	1
735	1	1
764	1	1
765	1	1
766	1	1
771	1	1
776	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
795	1	1
800	1	1
801	1	1
803	1	1
807	1	1
811	1	1
815	1	1
819	1	1
841	1	1
845	1	1
847	1	1
848	1	1
850	1	1
853	1	1
875	2	2
876	2	2
877	2	2
			MISSING_ELSE
882	2	2
883	2	2
884	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	170	137	80.59
Logical	170	137	80.59
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       245
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       245
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       245
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       246
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       246
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       252
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       258
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       286
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       318
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       319
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       320
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       321
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       330
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Covered	T18,T19,T11
1	1	0	1	Covered	T18,T11,T20
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       331
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       332
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       333
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       340
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       374
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       430
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       437
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       437
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       437
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       437
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T3,T4
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T3,T4

 LINE       445
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T22
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       447
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T7,T21,T22
1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       494
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T7,T22,T23
1	1	1	Covered	T1,T3,T4

 LINE       510
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       510
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       516
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       519
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       519
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       519
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       535
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       583
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       613
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Unreachable	T7,T22,T23
1	1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       735
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T3,T4
1	1	Covered	T24,T25,T26

 LINE       764
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T18,T19,T11

 LINE       764
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       765
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T18,T11,T20

 LINE       765
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       766
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       771
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Covered	T3,T27,T14
0	1	0	Covered	T3,T4,T7
1	0	0	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       771
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T7,T28,T21
1	1	1	Covered	T3,T27,T14

 LINE       771
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       771
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       776
 EXPRESSION (reg_hash_start & invalid_config)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       795
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       795
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T3,T4,T5
0	0	0	1	0	Covered	T3,T4,T5
0	0	1	0	0	Covered	T18,T11,T20
0	1	0	0	0	Covered	T6,T9,T29
1	0	0	0	0	Covered	T18,T19,T11

 LINE       841
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T4
1	1	1	0	Covered	T5,T6,T7
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T29,T32	Yes	T3,T29,T32	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T10,T13,T11	Yes	T10,T13,T11	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T24,T25	Yes	T2,T24,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T24,T25	Yes	T2,T24,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T21,T33,T34	Yes	T21,T33,T34	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	165	Covered	T1,T2,T3
DoneAwaitHashComplete	173	Not Covered
DoneAwaitHashDone	155	Covered	T1,T3,T4
DoneAwaitMessageComplete	158	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	155	Covered	T1,T3,T4
DoneAwaitCmd->DoneAwaitMessageComplete	158	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	180	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	165	Covered	T1,T3,T4
DoneAwaitMessageComplete->DoneAwaitHashComplete	173	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		91	82	90.11
TERNARY	286	2	2	100.00
TERNARY	437	4	4	100.00
TERNARY	447	2	2	100.00
TERNARY	510	2	2	100.00
CASE	151	10	4	40.00
IF	189	2	2	100.00
IF	202	3	3	100.00
IF	215	2	2	100.00
IF	227	2	2	100.00
IF	235	5	5	100.00
CASE	274	4	4	100.00
IF	289	2	2	100.00
CASE	295	6	6	100.00
IF	336	4	4	100.00
IF	346	3	3	100.00
IF	381	4	4	100.00
IF	450	2	2	100.00
IF	514	4	3	75.00
IF	596	2	2	100.00
IF	602	5	3	60.00
IF	611	3	3	100.00
IF	780	2	2	100.00
CASE	801	6	6	100.00
IF	847	2	2	100.00
IF	875	4	4	100.00
IF	882	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	286	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	(fifo_full) ? 
-2-:	437	(fifo_empty_negedge) ? 
-3-:	437	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T21,T22

	LineNo.	Expression
-1-:	510	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	case (done_state_q)
-2-:	153	if (sha_hash_process)
-3-:	156	if (reg_hash_stop)
-4-:	163	if (reg_hash_done)
-5-:	170	if ((sha_message_length[8:0] == '0))
-6-:	178	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T3,T4
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T3,T4
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T3,T4
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if (wipe_secret)
-2-:	204	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	215	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((digest_size_started_q == SHA2_256))
-2-:	236	if ((i < 8))
-3-:	245	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))
-4-:	246	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T3,T4
1	0	-	-	Covered	T1,T3,T4
0	-	1	1	Covered	T3,T4,T5
0	-	1	0	Covered	T3,T4,T5
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T3,T4,T5
SHA2_512	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	295	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T3,T4,T5
Key_256	Covered	T1,T3,T4
Key_384	Covered	T3,T4,T5
Key_512	Covered	T3,T4,T5
Key_1024	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if ((!rst_ni))
-2-:	338	if (hash_start_or_continue)
-3-:	340	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	374	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	381	if ((!rst_ni))
-2-:	383	if (hash_start_or_continue)
-3-:	385	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if (hmac_fifo_wsel)
-2-:	516	if ((digest_size == SHA2_256))
-3-:	519	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T5
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	596	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if ((!cfg_block))
-2-:	603	if (reg2hw.msg_length_lower.qe)
-3-:	606	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	611	if (hash_start)
-2-:	613	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	780	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	801	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T18,T19,T11
update_seckey_inprocess	Covered	T6,T9,T29
hash_start_active	Covered	T18,T11,T20
msg_push_not_allowed	Covered	T3,T4,T5
invalid_config_atstart	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	847	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	875	if ((!rst_ni))
-2-:	876	if (hash_process)
-3-:	877	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	882	if ((!rst_ni))
-2-:	883	if (hash_start_or_continue)
-3-:	884	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	200993271	200948636	0	0
FpvSecCmRegWeOnehotCheck_A	200993271	120	0	0
IntrFifoEmptyOKnown	200993271	200948636	0	0
IntrHmacDoneOKnown	200993271	200948636	0	0
TlOAReadyKnown	200993271	200948636	0	0
TlODValidKnown	200993271	200948636	0	0
ValidHashProcessAssert	200993271	16492	0	0
ValidHmacEnConditionAssert	200993271	7230	0	0
ValidWriteAssert	200993271	10812454	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	200993271	10812454	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	120	0	0
T2	8058	30	0	0
T3	337146	0	0	0
T4	174183	0	0	0
T5	21781	0	0	0
T6	723395	0	0	0
T7	110952	0	0	0
T8	148534	0	0	0
T9	308067	0	0	0
T27	52084	0	0	0
T29	272793	0	0	0
T30	0	20	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	0	30	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	16492	0	0
T1	5057	4	0	0
T2	8058	0	0	0
T3	337146	18	0	0
T4	174183	13	0	0
T5	21781	13	0	0
T6	723395	194	0	0
T7	110952	24	0	0
T8	148534	5	0	0
T9	308067	194	0	0
T14	0	22	0	0
T27	52084	0	0	0
T29	0	194	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	7230	0	0
T1	5057	1	0	0
T2	8058	0	0	0
T3	337146	1	0	0
T4	174183	1	0	0
T5	21781	4	0	0
T6	723395	0	0	0
T7	110952	22	0	0
T8	148534	1	0	0
T9	308067	0	0	0
T14	0	27	0	0
T27	52084	3	0	0
T32	0	4	0	0
T41	0	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		191	183	95.81
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	148	15	9	60.00
ALWAYS	189	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
ALWAYS	201	7	7	100.00
ALWAYS	215	3	3	100.00
ALWAYS	225	0	0
ALWAYS	225	21	21	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
ALWAYS	274	4	4	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	289	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	295	6	6	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
ALWAYS	336	6	6	100.00
ALWAYS	346	4	4	100.00
ALWAYS	381	6	6	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
ALWAYS	450	5	5	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	583	1	1	100.00
ALWAYS	588	3	3	100.00
ALWAYS	596	3	3	100.00
ALWAYS	601	10	8	80.00
CONT_ASSIGN	618	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
ALWAYS	779	6	6	100.00
CONT_ASSIGN	795	1	1	100.00
ALWAYS	800	7	7	100.00
CONT_ASSIGN	841	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
ALWAYS	847	3	3	100.00
CONT_ASSIGN	853	1	1	100.00
ALWAYS	875	6	6	100.00
ALWAYS	882	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
135	1	1
136	1	1
148	1	1
149	1	1
151	1	1
153	1	1
155	1	1
156	1	1
158	0	1
			MISSING_ELSE
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	0	1
173	0	1
			==> MISSING_ELSE
178	0	1
179	0	1
180	0	1
			==> MISSING_ELSE
189	1	1
190	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
203	1	1
204	1	1
206	1	1
207	1	1
208	1	1
			MISSING_ELSE
			MISSING_ELSE
215	2	2
216	1	1
225	1	1
227	1	1
229	1	1
230	1	1
			MISSING_ELSE
233	1	1
235	1	1
236	1	1
238	1	1
240	1	1
241	1	1
243	1	1
245	1	1
246	1	1
248	1	1
249	1	1
251	1	1
252	1	1
254	1	1
255	1	1
257	1	1
258	1	1
			MISSING_ELSE
265	1	1
269	1	1
270	1	1
272	1	1
274	1	1
275	1	1
276	1	1
277	1	1
286	1	1
289	2	2
290	1	1
293	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
308	1	1
309	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
318	1	1
319	1	1
320	1	1
321	1	1
324	1	1
325	1	1
330	1	1
331	1	1
332	1	1
333	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
346	1	1
347	1	1
374	1	1
375	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE
430	1	1
437	1	1
445	1	1
447	1	1
450	1	1
451	1	1
452	1	1
454	1	1
455	1	1
491	1	1
494	1	1
500	1	1
505	1	1
506	1	1
508	1	1
509	1	1
510	1	1
514	1	1
515	1	1
516	1	1
518	1	1
519	1	1
521	1	1
522	1	1
			==> MISSING_ELSE
525	1	1
583	1	1
588	1	1
589	1	1
590	1	1
596	2	2
597	1	1
601	1	1
602	1	1
603	1	1
604	0	1
			MISSING_ELSE
606	1	1
607	0	1
			MISSING_ELSE
			MISSING_ELSE
611	1	1
612	1	1
613	1	1
614	1	1
			MISSING_ELSE
618	1	1
619	1	1
626	1	1
627	1	1
735	1	1
764	1	1
765	1	1
766	1	1
771	1	1
776	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
795	1	1
800	1	1
801	1	1
803	1	1
807	1	1
811	1	1
815	1	1
819	1	1
841	1	1
845	1	1
847	1	1
848	1	1
850	1	1
853	1	1
875	2	2
876	2	2
877	2	2
			MISSING_ELSE
882	2	2
883	2	2
884	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	164	137	83.54
Logical	164	137	83.54
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       245
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       245
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       245
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       246
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       246
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       252
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       258
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       286
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       318
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       319
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       320
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       321
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       330
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Covered	T18,T19,T11
1	1	0	1	Covered	T18,T11,T20
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       331
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       332
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       333
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       340
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       374
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       430
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       437
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       437
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       437
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       437
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T3,T4
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T3,T4

 LINE       445
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T22
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       447
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T7,T21,T22
1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Excluded		VC_COV_UNR

 LINE       494
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T7,T22,T23
1	1	1	Covered	T1,T3,T4

 LINE       510
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       510
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       516
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       519
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       519
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       519
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       535
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       583
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       613
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Unreachable	T7,T22,T23
1	1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       735
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T3,T4
1	1	Covered	T24,T25,T26

 LINE       764
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T18,T19,T11

 LINE       764
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       765
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T18,T11,T20

 LINE       765
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       766
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       771
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Covered	T3,T27,T14
0	1	0	Covered	T3,T4,T7
1	0	0	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       771
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T7,T28,T21
1	1	1	Covered	T3,T27,T14

 LINE       771
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       771
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       776
 EXPRESSION (reg_hash_start & invalid_config)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       795
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       795
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T3,T4,T5
0	0	0	1	0	Covered	T3,T4,T5
0	0	1	0	0	Covered	T18,T11,T20
0	1	0	0	0	Covered	T6,T9,T29
1	0	0	0	0	Covered	T18,T19,T11

 LINE       841
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T4
1	1	1	0	Covered	T5,T6,T7
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T29,T32	Yes	T3,T29,T32	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T10,T13,T11	Yes	T10,T13,T11	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T24,T25	Yes	T2,T24,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T24,T25	Yes	T2,T24,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T21,T33,T34	Yes	T21,T33,T34	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	165	Covered	T1,T2,T3
DoneAwaitHashComplete	173	Not Covered
DoneAwaitHashDone	155	Covered	T1,T3,T4
DoneAwaitMessageComplete	158	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	155	Covered	T1,T3,T4
DoneAwaitCmd->DoneAwaitMessageComplete	158	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	180	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	165	Covered	T1,T3,T4
DoneAwaitMessageComplete->DoneAwaitHashComplete	173	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		91	82	90.11
TERNARY	286	2	2	100.00
TERNARY	437	4	4	100.00
TERNARY	447	2	2	100.00
TERNARY	510	2	2	100.00
CASE	151	10	4	40.00
IF	189	2	2	100.00
IF	202	3	3	100.00
IF	215	2	2	100.00
IF	227	2	2	100.00
IF	235	5	5	100.00
CASE	274	4	4	100.00
IF	289	2	2	100.00
CASE	295	6	6	100.00
IF	336	4	4	100.00
IF	346	3	3	100.00
IF	381	4	4	100.00
IF	450	2	2	100.00
IF	514	4	3	75.00
IF	596	2	2	100.00
IF	602	5	3	60.00
IF	611	3	3	100.00
IF	780	2	2	100.00
CASE	801	6	6	100.00
IF	847	2	2	100.00
IF	875	4	4	100.00
IF	882	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	286	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	(fifo_full) ? 
-2-:	437	(fifo_empty_negedge) ? 
-3-:	437	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T21,T22

	LineNo.	Expression
-1-:	510	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	case (done_state_q)
-2-:	153	if (sha_hash_process)
-3-:	156	if (reg_hash_stop)
-4-:	163	if (reg_hash_done)
-5-:	170	if ((sha_message_length[8:0] == '0))
-6-:	178	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T3,T4
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T3,T4
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T3,T4
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if (wipe_secret)
-2-:	204	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	215	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((digest_size_started_q == SHA2_256))
-2-:	236	if ((i < 8))
-3-:	245	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))
-4-:	246	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T3,T4
1	0	-	-	Covered	T1,T3,T4
0	-	1	1	Covered	T3,T4,T5
0	-	1	0	Covered	T3,T4,T5
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T3,T4,T5
SHA2_512	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	295	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T3,T4,T5
Key_256	Covered	T1,T3,T4
Key_384	Covered	T3,T4,T5
Key_512	Covered	T3,T4,T5
Key_1024	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if ((!rst_ni))
-2-:	338	if (hash_start_or_continue)
-3-:	340	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	374	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	381	if ((!rst_ni))
-2-:	383	if (hash_start_or_continue)
-3-:	385	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if (hmac_fifo_wsel)
-2-:	516	if ((digest_size == SHA2_256))
-3-:	519	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T5
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	596	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if ((!cfg_block))
-2-:	603	if (reg2hw.msg_length_lower.qe)
-3-:	606	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	611	if (hash_start)
-2-:	613	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	780	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	801	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T18,T19,T11
update_seckey_inprocess	Covered	T6,T9,T29
hash_start_active	Covered	T18,T11,T20
msg_push_not_allowed	Covered	T3,T4,T5
invalid_config_atstart	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	847	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	875	if ((!rst_ni))
-2-:	876	if (hash_process)
-3-:	877	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	882	if ((!rst_ni))
-2-:	883	if (hash_start_or_continue)
-3-:	884	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	200993271	200948636	0	0
FpvSecCmRegWeOnehotCheck_A	200993271	120	0	0
IntrFifoEmptyOKnown	200993271	200948636	0	0
IntrHmacDoneOKnown	200993271	200948636	0	0
TlOAReadyKnown	200993271	200948636	0	0
TlODValidKnown	200993271	200948636	0	0
ValidHashProcessAssert	200993271	16492	0	0
ValidHmacEnConditionAssert	200993271	7230	0	0
ValidWriteAssert	200993271	10812454	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	200993271	10812454	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	200993271	10812454	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	120	0	0
T2	8058	30	0	0
T3	337146	0	0	0
T4	174183	0	0	0
T5	21781	0	0	0
T6	723395	0	0	0
T7	110952	0	0	0
T8	148534	0	0	0
T9	308067	0	0	0
T27	52084	0	0	0
T29	272793	0	0	0
T30	0	20	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	0	30	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	200948636	0	0
T1	5057	4991	0	0
T2	8058	5713	0	0
T3	337146	337088	0	0
T4	174183	174091	0	0
T5	21781	21709	0	0
T6	723395	723297	0	0
T7	110952	110871	0	0
T8	148534	148458	0	0
T9	308067	308057	0	0
T27	52084	52025	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	16492	0	0
T1	5057	4	0	0
T2	8058	0	0	0
T3	337146	18	0	0
T4	174183	13	0	0
T5	21781	13	0	0
T6	723395	194	0	0
T7	110952	24	0	0
T8	148534	5	0	0
T9	308067	194	0	0
T14	0	22	0	0
T27	52084	0	0	0
T29	0	194	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	7230	0	0
T1	5057	1	0	0
T2	8058	0	0	0
T3	337146	1	0	0
T4	174183	1	0	0
T5	21781	4	0	0
T6	723395	0	0	0
T7	110952	22	0	0
T8	148534	1	0	0
T9	308067	0	0	0
T14	0	27	0	0
T27	52084	3	0	0
T32	0	4	0	0
T41	0	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	200993271	10812454	0	0
T1	5057	47	0	0
T2	8058	0	0	0
T3	337146	63424	0	0
T4	174183	32629	0	0
T5	21781	153	0	0
T6	723395	74259	0	0
T7	110952	53298	0	0
T8	148534	28632	0	0
T9	308067	74387	0	0
T27	52084	1771	0	0
T29	0	74258	0	0