Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498269027	1818992	0	0
intr_enable_rd_A	498269027	3353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498269027	1818992	0	0
T12	127795	22861	0	0
T13	0	30688	0	0
T14	0	94969	0	0
T35	0	121880	0	0
T36	0	412362	0	0
T37	0	148282	0	0
T38	0	169551	0	0
T63	53051	0	0	0
T83	0	47115	0	0
T84	0	144088	0	0
T85	0	389896	0	0
T86	83085	0	0	0
T87	653849	0	0	0
T88	222955	0	0	0
T89	56633	0	0	0
T90	985	0	0	0
T91	33191	0	0	0
T92	27565	0	0	0
T93	205228	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498269027	3353	0	0
T12	127795	43	0	0
T13	0	121	0	0
T14	0	132	0	0
T35	0	243	0	0
T63	53051	0	0	0
T82	0	85	0	0
T83	0	94	0	0
T86	83085	0	0	0
T87	653849	0	0	0
T88	222955	0	0	0
T89	56633	0	0	0
T90	985	0	0	0
T91	33191	0	0	0
T92	27565	0	0	0
T93	205228	0	0	0
T94	0	7	0	0
T95	0	20	0	0
T96	0	37	0	0
T97	0	40	0	0