HMAC Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	22.930s	1.236ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.360s	115.400us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.510s	58.562us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.250s	3.142ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.400s	313.494us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.598m	775.490ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.510s	58.562us	20	20	100.00
		hmac_csr_aliasing	10.400s	313.494us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	5.227m	116.141ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.317m	7.026ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.634m	91.133ms	5	5	100.00
		hmac_test_sha384_vectors	49.228m	143.796ms	5	5	100.00
		hmac_test_sha512_vectors	49.451m	855.428ms	5	5	100.00
		hmac_test_hmac256_vectors	1.619m	10.043ms	5	5	100.00
		hmac_test_hmac384_vectors	1.822m	8.173ms	5	5	100.00
		hmac_test_hmac512_vectors	2.433m	8.793ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.603m	19.392ms	48	50	96.00
V2	datapath_stress	hmac_datapath_stress	38.001m	66.061ms	50	50	100.00
V2	error	hmac_error	4.922m	15.219ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.238m	12.187ms	50	50	100.00
V2	save_and_restore	hmac_smoke	22.930s	1.236ms	50	50	100.00
		hmac_long_msg	5.227m	116.141ms	50	50	100.00
		hmac_back_pressure	2.317m	7.026ms	50	50	100.00
		hmac_datapath_stress	38.001m	66.061ms	50	50	100.00
		hmac_burst_wr	1.603m	19.392ms	48	50	96.00
		hmac_stress_all	1.659h	104.399ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	22.930s	1.236ms	50	50	100.00
		hmac_long_msg	5.227m	116.141ms	50	50	100.00
		hmac_back_pressure	2.317m	7.026ms	50	50	100.00
		hmac_datapath_stress	38.001m	66.061ms	50	50	100.00
		hmac_wipe_secret	3.238m	12.187ms	50	50	100.00
		hmac_test_sha256_vectors	12.634m	91.133ms	5	5	100.00
		hmac_test_sha384_vectors	49.228m	143.796ms	5	5	100.00
		hmac_test_sha512_vectors	49.451m	855.428ms	5	5	100.00
		hmac_test_hmac256_vectors	1.619m	10.043ms	5	5	100.00
		hmac_test_hmac384_vectors	1.822m	8.173ms	5	5	100.00
		hmac_test_hmac512_vectors	2.433m	8.793ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	22.930s	1.236ms	50	50	100.00
		hmac_long_msg	5.227m	116.141ms	50	50	100.00
		hmac_back_pressure	2.317m	7.026ms	50	50	100.00
		hmac_datapath_stress	38.001m	66.061ms	50	50	100.00
		hmac_burst_wr	1.603m	19.392ms	48	50	96.00
		hmac_error	4.922m	15.219ms	50	50	100.00
		hmac_wipe_secret	3.238m	12.187ms	50	50	100.00
		hmac_test_sha256_vectors	12.634m	91.133ms	5	5	100.00
		hmac_test_sha384_vectors	49.228m	143.796ms	5	5	100.00
		hmac_test_sha512_vectors	49.451m	855.428ms	5	5	100.00
		hmac_test_hmac256_vectors	1.619m	10.043ms	5	5	100.00
		hmac_test_hmac384_vectors	1.822m	8.173ms	5	5	100.00
		hmac_test_hmac512_vectors	2.433m	8.793ms	5	5	100.00
		hmac_stress_all	1.659h	104.399ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.659h	104.399ms	50	50	100.00
V2	alert_test	hmac_alert_test	1.000s	15.910us	50	50	100.00
V2	intr_test	hmac_intr_test	0.980s	31.822us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.080s	1.350ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.080s	1.350ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.360s	115.400us	5	5	100.00
		hmac_csr_rw	1.510s	58.562us	20	20	100.00
		hmac_csr_aliasing	10.400s	313.494us	5	5	100.00
		hmac_same_csr_outstanding	3.280s	158.587us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.360s	115.400us	5	5	100.00
		hmac_csr_rw	1.510s	58.562us	20	20	100.00
		hmac_csr_aliasing	10.400s	313.494us	5	5	100.00
		hmac_same_csr_outstanding	3.280s	158.587us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.800s	86.201us	5	5	100.00
		hmac_tl_intg_err	5.820s	482.633us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.820s	482.633us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	22.930s	1.236ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.833m	10.470ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			651	660	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.77	95.37	97.17	100.00	88.24	98.25	98.52	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 2.hmac_stress_all_with_rand_reset.37233786762913706915765449449814602845018273730978155814897174891917240747479
      Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 198988881 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 198988881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.hmac_stress_all_with_rand_reset.109608089616598472560572792611785322079328260324536245020210189900616182092135
      Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  11942713 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @  11942713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:

  • Test hmac_burst_wr has 2 failures.

    • 33.hmac_burst_wr.23334960719574605757870193679769787357006346431420198758784613957431470200743
      Line 707, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 630077434 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 630077434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.hmac_burst_wr.63356849967284193711076022858260543617930637523721615316587916902746475186203
      Line 714, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 403704341 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 403704341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 1.hmac_stress_all_with_rand_reset.8326772851440560363363140428799088033648564989023486876464014534413396168193
      Line 3149, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1770809786 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1770809786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 3.hmac_stress_all_with_rand_reset.86366602546517022990543029767630251975331084204429371699149085139370238811755
      Line 27124, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10469679614 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10469679614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 4.hmac_stress_all_with_rand_reset.44147022641049990790688706037211089566634977783006654630559692232264403822113
      Line 28048, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4084612916 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4084612916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 8.hmac_stress_all_with_rand_reset.90294367524940188719431324727139765366793676088289871592986795654694364581155
      Line 5224, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1052229014 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1052229014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 9.hmac_stress_all_with_rand_reset.24007672644003802178820386289268273276043731219890045044588991503631476086272
      Line 6828, in log /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6606657863 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6606657863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.09.25_11.00.06
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• 2024.09.12_10.15.32
• 2024.09.10_08.10.25
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