HMAC Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	22.560s	1.272ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.320s	48.652us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.340s	17.509us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	22.100s	4.387ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	12.890s	6.286ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.150m	471.358ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.340s	17.509us	20	20	100.00
		hmac_csr_aliasing	12.890s	6.286ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.284m	16.401ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.514m	8.321ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.107m	133.804ms	5	5	100.00
		hmac_test_sha384_vectors	49.523m	607.478ms	5	5	100.00
		hmac_test_sha512_vectors	43.149m	704.777ms	5	5	100.00
		hmac_test_hmac256_vectors	1.427m	10.390ms	5	5	100.00
		hmac_test_hmac384_vectors	1.644m	10.177ms	5	5	100.00
		hmac_test_hmac512_vectors	2.680m	12.155ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.667m	5.488ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.908m	109.298ms	50	50	100.00
V2	error	hmac_error	4.623m	63.290ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.010m	8.157ms	50	50	100.00
V2	save_and_restore	hmac_smoke	22.560s	1.272ms	50	50	100.00
		hmac_long_msg	4.284m	16.401ms	50	50	100.00
		hmac_back_pressure	2.514m	8.321ms	50	50	100.00
		hmac_datapath_stress	25.908m	109.298ms	50	50	100.00
		hmac_burst_wr	1.667m	5.488ms	50	50	100.00
		hmac_stress_all	1.274h	259.760ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	22.560s	1.272ms	50	50	100.00
		hmac_long_msg	4.284m	16.401ms	50	50	100.00
		hmac_back_pressure	2.514m	8.321ms	50	50	100.00
		hmac_datapath_stress	25.908m	109.298ms	50	50	100.00
		hmac_wipe_secret	3.010m	8.157ms	50	50	100.00
		hmac_test_sha256_vectors	11.107m	133.804ms	5	5	100.00
		hmac_test_sha384_vectors	49.523m	607.478ms	5	5	100.00
		hmac_test_sha512_vectors	43.149m	704.777ms	5	5	100.00
		hmac_test_hmac256_vectors	1.427m	10.390ms	5	5	100.00
		hmac_test_hmac384_vectors	1.644m	10.177ms	5	5	100.00
		hmac_test_hmac512_vectors	2.680m	12.155ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	22.560s	1.272ms	50	50	100.00
		hmac_long_msg	4.284m	16.401ms	50	50	100.00
		hmac_back_pressure	2.514m	8.321ms	50	50	100.00
		hmac_datapath_stress	25.908m	109.298ms	50	50	100.00
		hmac_burst_wr	1.667m	5.488ms	50	50	100.00
		hmac_error	4.623m	63.290ms	50	50	100.00
		hmac_wipe_secret	3.010m	8.157ms	50	50	100.00
		hmac_test_sha256_vectors	11.107m	133.804ms	5	5	100.00
		hmac_test_sha384_vectors	49.523m	607.478ms	5	5	100.00
		hmac_test_sha512_vectors	43.149m	704.777ms	5	5	100.00
		hmac_test_hmac256_vectors	1.427m	10.390ms	5	5	100.00
		hmac_test_hmac384_vectors	1.644m	10.177ms	5	5	100.00
		hmac_test_hmac512_vectors	2.680m	12.155ms	5	5	100.00
		hmac_stress_all	1.274h	259.760ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.274h	259.760ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.970s	13.154us	50	50	100.00
V2	intr_test	hmac_intr_test	1.030s	26.021us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.910s	924.784us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.910s	924.784us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.320s	48.652us	5	5	100.00
		hmac_csr_rw	1.340s	17.509us	20	20	100.00
		hmac_csr_aliasing	12.890s	6.286ms	5	5	100.00
		hmac_same_csr_outstanding	3.750s	119.382us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.320s	48.652us	5	5	100.00
		hmac_csr_rw	1.340s	17.509us	20	20	100.00
		hmac_csr_aliasing	12.890s	6.286ms	5	5	100.00
		hmac_same_csr_outstanding	3.750s	119.382us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.300s	347.525us	5	5	100.00
		hmac_tl_intg_err	6.520s	879.049us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.520s	879.049us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	22.560s	1.272ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.238m	81.358ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			652	660	98.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	95.37	97.17	100.00	94.12	98.25	98.52	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 3 failures:
- Test hmac_stress_all_with_rand_reset has 3 failures.
  - 4.hmac_stress_all_with_rand_reset.94556709978192401040021821755690016633953295624777832557883640393588832707152
    Line 1030, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2671507246 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2671507246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.hmac_stress_all_with_rand_reset.15232371403387726500443307337106000405700306689945147363041268256111998059084
    Line 1998, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 653623157 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 653623157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 0.hmac_stress_all_with_rand_reset.109876958381251526426715637304029007180375268714493972197881856740973016968239
    Line 75, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34104132 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  34104132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.hmac_stress_all_with_rand_reset.31802297964796595625681613608906025701390220931371498174208201428310912521711
    Line 15122, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6915678343 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6915678343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 1.hmac_stress_all_with_rand_reset.90108959344935269823811002039241602563012435198914786212828967472219235732631
    Line 14265, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4464987456 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4464987456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.hmac_stress_all_with_rand_reset.68165061504378805519316546320623872464599160814797160760422347060683925674052
    Line 5156, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55929676648 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 55929676648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.111179720723586237369686361607900872952558341294834670084323647918917192782060
    Line 69, in log /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   8563184 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @   8563184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`