HMAC Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	20.030s	1.174ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.370s	40.972us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.330s	87.378us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	22.500s	3.269ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.280s	302.723us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.530m	429.629ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.330s	87.378us	20	20	100.00
		hmac_csr_aliasing	10.280s	302.723us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.533m	3.051ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.391m	3.799ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.066m	76.023ms	5	5	100.00
		hmac_test_sha384_vectors	48.156m	823.132ms	5	5	100.00
		hmac_test_sha512_vectors	43.976m	189.339ms	5	5	100.00
		hmac_test_hmac256_vectors	1.426m	23.012ms	5	5	100.00
		hmac_test_hmac384_vectors	2.099m	9.447ms	5	5	100.00
		hmac_test_hmac512_vectors	2.328m	11.058ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.732m	7.973ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.071m	133.237ms	50	50	100.00
V2	error	hmac_error	4.947m	41.382ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.622m	20.694ms	50	50	100.00
V2	save_and_restore	hmac_smoke	20.030s	1.174ms	50	50	100.00
		hmac_long_msg	3.533m	3.051ms	50	50	100.00
		hmac_back_pressure	2.391m	3.799ms	50	50	100.00
		hmac_datapath_stress	26.071m	133.237ms	50	50	100.00
		hmac_burst_wr	1.732m	7.973ms	50	50	100.00
		hmac_stress_all	1.534h	69.625ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	20.030s	1.174ms	50	50	100.00
		hmac_long_msg	3.533m	3.051ms	50	50	100.00
		hmac_back_pressure	2.391m	3.799ms	50	50	100.00
		hmac_datapath_stress	26.071m	133.237ms	50	50	100.00
		hmac_wipe_secret	2.622m	20.694ms	50	50	100.00
		hmac_test_sha256_vectors	12.066m	76.023ms	5	5	100.00
		hmac_test_sha384_vectors	48.156m	823.132ms	5	5	100.00
		hmac_test_sha512_vectors	43.976m	189.339ms	5	5	100.00
		hmac_test_hmac256_vectors	1.426m	23.012ms	5	5	100.00
		hmac_test_hmac384_vectors	2.099m	9.447ms	5	5	100.00
		hmac_test_hmac512_vectors	2.328m	11.058ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	20.030s	1.174ms	50	50	100.00
		hmac_long_msg	3.533m	3.051ms	50	50	100.00
		hmac_back_pressure	2.391m	3.799ms	50	50	100.00
		hmac_datapath_stress	26.071m	133.237ms	50	50	100.00
		hmac_burst_wr	1.732m	7.973ms	50	50	100.00
		hmac_error	4.947m	41.382ms	50	50	100.00
		hmac_wipe_secret	2.622m	20.694ms	50	50	100.00
		hmac_test_sha256_vectors	12.066m	76.023ms	5	5	100.00
		hmac_test_sha384_vectors	48.156m	823.132ms	5	5	100.00
		hmac_test_sha512_vectors	43.976m	189.339ms	5	5	100.00
		hmac_test_hmac256_vectors	1.426m	23.012ms	5	5	100.00
		hmac_test_hmac384_vectors	2.099m	9.447ms	5	5	100.00
		hmac_test_hmac512_vectors	2.328m	11.058ms	5	5	100.00
		hmac_stress_all	1.534h	69.625ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.534h	69.625ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.970s	34.873us	50	50	100.00
V2	intr_test	hmac_intr_test	0.890s	29.594us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	6.110s	460.692us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	6.110s	460.692us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.370s	40.972us	5	5	100.00
		hmac_csr_rw	1.330s	87.378us	20	20	100.00
		hmac_csr_aliasing	10.280s	302.723us	5	5	100.00
		hmac_same_csr_outstanding	3.530s	563.722us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.370s	40.972us	5	5	100.00
		hmac_csr_rw	1.330s	87.378us	20	20	100.00
		hmac_csr_aliasing	10.280s	302.723us	5	5	100.00
		hmac_same_csr_outstanding	3.530s	563.722us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.460s	64.088us	5	5	100.00
		hmac_tl_intg_err	5.830s	1.441ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.830s	1.441ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	20.030s	1.174ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	14.754m	11.075ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			655	660	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.37	97.22	100.00	94.12	98.25	98.52	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 3 failures:

  • Test hmac_stress_all_with_rand_reset has 3 failures.

    • 1.hmac_stress_all_with_rand_reset.56571655866676136011585760843100197447733282030820583594995705297413818444780
      Line 12868, in log /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7330048349 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 7330048349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.hmac_stress_all_with_rand_reset.32169506416722553635222514554242532849160272031489482913349761508750255606846
      Line 19515, in log /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3709701684 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3709701684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 0.hmac_stress_all_with_rand_reset.78705516895136400839696091758091473509771979468359095939730625621324505779513
      Line 9513, in log /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2979618991 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2979618991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 6.hmac_stress_all_with_rand_reset.86634798944960372114651719070852047746470015035032062610289969766827407586968
      Line 1269, in log /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 569381476 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 569381476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.04_00.41.06
• 2024.09.25_11.00.06
• 2024.09.19_09.03.53
• 2024.09.12_10.15.32
• 2024.09.10_08.10.25
• 2024.09.05_04.19.57