HMAC Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	24.340s	1.076ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.430s	35.475us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.440s	329.417us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	19.900s	2.138ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	11.490s	305.682us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.294m	351.332ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.440s	329.417us	20	20	100.00
		hmac_csr_aliasing	11.490s	305.682us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.940m	21.242ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.322m	8.466ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.478m	57.031ms	5	5	100.00
		hmac_test_sha384_vectors	45.908m	807.225ms	5	5	100.00
		hmac_test_sha512_vectors	49.232m	220.181ms	5	5	100.00
		hmac_test_hmac256_vectors	1.171m	4.449ms	5	5	100.00
		hmac_test_hmac384_vectors	1.945m	9.916ms	5	5	100.00
		hmac_test_hmac512_vectors	2.110m	95.526ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	2.112m	4.897ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.913m	8.866ms	50	50	100.00
V2	error	hmac_error	5.637m	201.263ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.499m	12.168ms	50	50	100.00
V2	save_and_restore	hmac_smoke	24.340s	1.076ms	50	50	100.00
		hmac_long_msg	3.940m	21.242ms	50	50	100.00
		hmac_back_pressure	2.322m	8.466ms	50	50	100.00
		hmac_datapath_stress	26.913m	8.866ms	50	50	100.00
		hmac_burst_wr	2.112m	4.897ms	50	50	100.00
		hmac_stress_all	1.061h	61.290ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	24.340s	1.076ms	50	50	100.00
		hmac_long_msg	3.940m	21.242ms	50	50	100.00
		hmac_back_pressure	2.322m	8.466ms	50	50	100.00
		hmac_datapath_stress	26.913m	8.866ms	50	50	100.00
		hmac_wipe_secret	3.499m	12.168ms	50	50	100.00
		hmac_test_sha256_vectors	12.478m	57.031ms	5	5	100.00
		hmac_test_sha384_vectors	45.908m	807.225ms	5	5	100.00
		hmac_test_sha512_vectors	49.232m	220.181ms	5	5	100.00
		hmac_test_hmac256_vectors	1.171m	4.449ms	5	5	100.00
		hmac_test_hmac384_vectors	1.945m	9.916ms	5	5	100.00
		hmac_test_hmac512_vectors	2.110m	95.526ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	24.340s	1.076ms	50	50	100.00
		hmac_long_msg	3.940m	21.242ms	50	50	100.00
		hmac_back_pressure	2.322m	8.466ms	50	50	100.00
		hmac_datapath_stress	26.913m	8.866ms	50	50	100.00
		hmac_burst_wr	2.112m	4.897ms	50	50	100.00
		hmac_error	5.637m	201.263ms	50	50	100.00
		hmac_wipe_secret	3.499m	12.168ms	50	50	100.00
		hmac_test_sha256_vectors	12.478m	57.031ms	5	5	100.00
		hmac_test_sha384_vectors	45.908m	807.225ms	5	5	100.00
		hmac_test_sha512_vectors	49.232m	220.181ms	5	5	100.00
		hmac_test_hmac256_vectors	1.171m	4.449ms	5	5	100.00
		hmac_test_hmac384_vectors	1.945m	9.916ms	5	5	100.00
		hmac_test_hmac512_vectors	2.110m	95.526ms	5	5	100.00
		hmac_stress_all	1.061h	61.290ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.061h	61.290ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.960s	16.286us	50	50	100.00
V2	intr_test	hmac_intr_test	1.000s	53.536us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.200s	76.086us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.200s	76.086us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.430s	35.475us	5	5	100.00
		hmac_csr_rw	1.440s	329.417us	20	20	100.00
		hmac_csr_aliasing	11.490s	305.682us	5	5	100.00
		hmac_same_csr_outstanding	3.720s	176.204us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.430s	35.475us	5	5	100.00
		hmac_csr_rw	1.440s	329.417us	20	20	100.00
		hmac_csr_aliasing	11.490s	305.682us	5	5	100.00
		hmac_same_csr_outstanding	3.720s	176.204us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.620s	150.169us	5	5	100.00
		hmac_tl_intg_err	6.870s	587.394us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.870s	587.394us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	24.340s	1.076ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	11.351m	48.175ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			655	660	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.37	97.22	100.00	94.12	98.25	98.52	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 1.hmac_stress_all_with_rand_reset.62461981061676829451538697088513881511479017281326700664918986750863851068474
    Line 13591, in log /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18167353654 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18167353654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 3.hmac_stress_all_with_rand_reset.39527381255122154125596629529180851844636218671225304894341019868248450463970
    Line 2887, in log /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1202936289 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1202936289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 5.hmac_stress_all_with_rand_reset.114864164685475390580317731581301884469200629995072083573794762836858270212855
    Line 8057, in log /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4974961874 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4974961874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.38948748321501733550326835886844629304547513811444509433931282520202945392451
    Line 3247, in log /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5721841371 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5721841371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 8.hmac_stress_all_with_rand_reset.66847085351380203257222116527236203678913658462218511664400856995705992027907
    Line 8595, in log /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2910864790 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2910864790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8a1401d614`