a9c19f09f3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.566m | 4.234ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 40.160s | 10.249ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.740s | 69.731us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.740s | 18.697us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.150s | 434.921us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.320s | 68.541us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.520s | 46.361us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.740s | 18.697us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.320s | 68.541us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.900s | 41.155us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.909m | 44.235ms | 38 | 50 | 76.00 |
| V2 | host_perf | i2c_host_perf | 23.470m | 28.739ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.680s | 19.165us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 15.168m | 21.986ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 16.940m | 128.599ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.230s | 141.775us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 40.780s | 9.091ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.330s | 1.941ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.793m | 13.647ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 52.410s | 4.876ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.202m | 5.948ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.470m | 2.616ms | 49 | 50 | 98.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.330s | 3.642ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.880s | 1.054ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 57.668m | 47.195ms | 39 | 50 | 78.00 |
| V2 | target_perf | i2c_target_perf | 5.910s | 1.006ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 3.225m | 7.736ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.812m | 10.570ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.260s | 2.400ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.281m | 10.151ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.751m | 10.031ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 58.600m | 50.041ms | 44 | 50 | 88.00 |
| i2c_target_stress_rd | 1.812m | 10.570ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 21.313m | 24.278ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.750s | 2.295ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 47.774m | 19.442ms | 42 | 50 | 84.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.860s | 1.395ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.610s | 1.583ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 35.353us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 58.240us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.160s | 163.389us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.160s | 163.389us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.740s | 69.731us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 18.697us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.320s | 68.541us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.050s | 53.623us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.740s | 69.731us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 18.697us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.320s | 68.541us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.050s | 53.623us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1453 | 1492 | 97.39 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.890s | 121.843us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.900s | 74.964us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.890s | 121.843us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.672m | 18.572ms | 4 | 50 | 8.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.693m | 100.303ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 4 | 100 | 4.00 | |||
| TOTAL | 1637 | 1772 | 92.38 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 26 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.81 | 99.07 | 96.52 | 100.00 | 98.26 | 98.13 | 100.00 | 92.65 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 81 failures:
0.i2c_host_stress_all.63808756821940596519116911806139128467011653170406601922547170212205404721060
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:e0ad2d51-c42c-4414-a423-027912f66ec0
1.i2c_host_stress_all.66824354903613297858314868887907899348748503302041247542714753462416531863453
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:367e4798-1379-4168-b3b0-095165623d45
... and 10 more failures.
0.i2c_host_stress_all_with_rand_reset.18464850641914668835773590544619686697536094465252398171664994814630094321462
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:81933fe3-13e5-4840-abfa-b6e20a2f8725
1.i2c_host_stress_all_with_rand_reset.6292648117575936137061753880143492888187620578509842169469928380283355269778
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:08f24c08-ccf6-4f54-a295-8131f7dea961
... and 40 more failures.
4.i2c_target_stress_wr.13784282774186958029899247361242206994937184573490465142241786416674179559236
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest/run.log
Job ID: smart:e2e7721a-22db-497c-a2f7-822b444f2576
8.i2c_target_stress_wr.34054609598592034229417136545121187610618504646621015822831451720088884064750
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest/run.log
Job ID: smart:5c9526e8-78f1-4a36-8a9d-74a1007a2835
... and 4 more failures.
5.i2c_target_stress_all.88051248171993755347272568660254436372684264996547440696079258541012351630434
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Job ID: smart:5c2db289-55e9-426b-b38c-f1caf2f112ee
11.i2c_target_stress_all.1076045433868173044984819490122907952710243989664076784321592741756385003204
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
Job ID: smart:74689830-662f-4cbd-ac3f-eb95ebf122d4
... and 9 more failures.
12.i2c_target_stretch.78096475574947390936555588371082822083024940674570897258188726777936428360898
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
Job ID: smart:d36b9f00-87f6-40fd-8959-92198acfae77
14.i2c_target_stretch.107224380890458546467787566513109228337568613401818169417187697414812325677152
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest/run.log
Job ID: smart:99d01918-490c-4bc6-8bd8-ed0e57c38acb
... and 6 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 15 failures:
0.i2c_target_stress_all_with_rand_reset.60529642327534265504561121197845782762168590470989243830432722267967010384507
Line 312, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13183597014 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 13183597014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.23725838258409211584522488839777167189780002104121801939788094158641340630642
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1671925047 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 1671925047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 11 failures:
3.i2c_target_stress_all_with_rand_reset.64772336718325203608398459351573139388221984252287819019416303993338135719424
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3235105059 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 8 [0x8])
UVM_INFO @ 3235105059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.30683723753774135321962984709351324958687026048569042787811642500616428046306
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1754511170 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 18 [0x12])
UVM_INFO @ 1754511170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 10 failures:
19.i2c_target_stress_all_with_rand_reset.351274551947606204641276353783335546961477815161143518735725047529641284292
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 602104727 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xdae1ad94) == 0x0
UVM_INFO @ 602104727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all_with_rand_reset.91149330721020908580127916513565011792771464243695446179566762461783341036205
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 329337147 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x1aa46294) == 0x0
UVM_INFO @ 329337147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 4 failures:
7.i2c_target_stress_all_with_rand_reset.30027049008587904784384268259022986975813493913523634782441735270454804077610
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 421517204 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (237 [0xed] vs 197 [0xc5])
UVM_INFO @ 421517204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stress_all_with_rand_reset.56347770799710642247834086836055243246093633429358187419674947872366620875249
Line 333, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25654079049 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (35 [0x23] vs 34 [0x22])
UVM_INFO @ 25654079049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 3 failures:
4.i2c_target_stress_all_with_rand_reset.41504111131086963631957697671794829494698157511470313655750814900488241394297
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 925396734 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 925396734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.102036448699043660547817197111998453957447921270007956726952369704147021309225
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 54707991 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 54707991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 3 failures:
20.i2c_host_stress_all_with_rand_reset.28154226424670708076645784320617493921748904454615385589390531423310156684535
Line 12098, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13124344995 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 13124344995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_host_stress_all_with_rand_reset.43027400296483490706498351929719595201822057575475048327393164955896976614964
Line 3507, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5193710557 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 5193710557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:698) scoreboard [scoreboard] has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
7.i2c_host_stress_all_with_rand_reset.30222159139948973227552259729303969381634614129294962510638427197492220256470
Line 639, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4270280567 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_mode_toggle has 1 failures.
12.i2c_host_mode_toggle.17580576237742172793457727360909600499972612179634445618233078623080637059490
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 653041222 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_ERROR (i2c_scoreboard.sv:791) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
8.i2c_target_stress_all_with_rand_reset.68865244392177592833467225368598525100208113990848959950128691005996043083163
Line 337, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6401457013 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 9 [0x9])
UVM_INFO @ 6401457013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_stress_all_with_rand_reset.53221393464680152763786494074425189141847609192635812983771828420851382850498
Line 452, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15386011053 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 96 [0x60])
UVM_INFO @ 15386011053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 2 failures:
9.i2c_target_stress_all_with_rand_reset.10154741673650499419682264269770936564799022585150464831793508278023584947756
Line 365, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100303102552 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100303102552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stress_all_with_rand_reset.47879691776154892852837962864076744340528675218547932045921399210550203760386
Line 387, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 134643668173 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 134643668173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
19.i2c_target_bad_addr.751549799813572626740208822051473522416414890540164048259627195226479192729
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
27.i2c_target_stress_all_with_rand_reset.78746954372494302586874208528359596148163304784828807156108848502133055223311
Line 340, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 9920460276 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 9920460276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---