I2C Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.615m	3.455ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	52.110s	1.274ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.800s	60.974us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.790s	26.763us	16	20	80.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.540s	1.130ms	0	5	0.00
V1	csr_aliasing	i2c_csr_aliasing	2.130s	514.639us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.520s	32.677us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.790s	26.763us	16	20	80.00
		i2c_csr_aliasing	2.130s	514.639us	5	5	100.00
V1		TOTAL			144	155	92.90
V2	host_error_intr	i2c_host_error_intr	2.100s	224.111us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	51.593m	25.265ms	48	50	96.00
V2	host_maxperf	i2c_host_perf	32.641m	49.493ms	50	50	100.00
V2	host_override	i2c_host_override	0.740s	204.290us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.737m	4.342ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.611m	2.063ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.270s	154.383us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.320s	1.687ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.020s	197.218us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.336m	8.791ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	40.050s	3.438ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.531m	2.092ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	8.390s	1.519ms	8	50	16.00
V2	target_glitch	i2c_target_glitch	10.860s	2.650ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	35.473m	45.194ms	3	50	6.00
V2	target_maxperf	i2c_target_perf	1.190s	246.900us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.380m	9.790ms	50	50	100.00
		i2c_target_intr_smoke	7.160s	18.008ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.462m	10.032ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.552m	10.026ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	50.846m	70.400ms	50	50	100.00
		i2c_target_stress_rd	1.380m	9.790ms	50	50	100.00
		i2c_target_intr_stress_wr	9.157m	23.680ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.220s	3.197ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	59.444m	31.491ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	5.870s	5.275ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.030s	558.806us	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.737m	4.342ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.690s	18.783us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	91.263us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.630s	518.653us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.630s	518.653us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.800s	60.974us	5	5	100.00
		i2c_csr_rw	0.790s	26.763us	16	20	80.00
		i2c_csr_aliasing	2.130s	514.639us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	121.771us	12	20	60.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.800s	60.974us	5	5	100.00
		i2c_csr_rw	0.790s	26.763us	16	20	80.00
		i2c_csr_aliasing	2.130s	514.639us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	121.771us	12	20	60.00
V2		TOTAL			1238	1392	88.94
V2S	tl_intg_err	i2c_tl_intg_err	2.340s	181.178us	13	20	65.00
		i2c_sec_cm	1.100s	120.367us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.340s	181.178us	13	20	65.00
V2S		TOTAL			18	25	72.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.325m	7.061ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	15.494m	128.418ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	21.670s	2.180ms	50	50	100.00
		TOTAL			1450	1722	84.20

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	4	57.14
V2	36	30	24	66.67
V2S	2	2	1	50.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.62	97.22	92.04	97.66	83.74	94.60	98.67	91.39

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 84 failures:
- Test i2c_target_perf has 50 failures.
  - 0.i2c_target_perf.43745112645610209000287549226652286013337240788572876455595459791900622163014
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  50136453 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  50136453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.103410472005482897195510043114435434048281802538870237145017372080181357920993
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 119637218 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 119637218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.
- Test i2c_target_stress_all has 19 failures.
  - 0.i2c_target_stress_all.53854670157172993155652557980904083945727106641906048317756459985080062188334
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  70066244 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  70066244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all.56979809309847950051605660638884214515491633197009214161875532371685463492132
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  87825144 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  87825144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
- Test i2c_target_stress_all_with_rand_reset has 15 failures.
  - 1.i2c_target_stress_all_with_rand_reset.66132112283209449289120685239824294142072017943545596485210207094711260859839
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 462176546 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 462176546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.52146552522339898524418779490478929499619422975510029440091034100637531676661
    Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3349337068 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 3349337068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 66 failures:
- Test i2c_target_unexp_stop has 41 failures.
  - 0.i2c_target_unexp_stop.12435975297276925293596848323212438761721069512707977940124221036000446925019
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2875407615 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2875407615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.106741450488898569736097501801465729842086127943174045873936166634572648038896
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 3133469781 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3133469781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 39 more failures.
- Test i2c_target_stress_all has 25 failures.
  - 2.i2c_target_stress_all.79486262604484188879103828097726020958983677145522881858246624859344300240775
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1785319660 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1785319660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all.83769432906762223597806590520802730304349403347849084034831027144369565107069
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2097664196 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2097664196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 64 failures:

Test i2c_host_stress_all_with_rand_reset has 45 failures.

0.i2c_host_stress_all_with_rand_reset.51500820633692199571664052574667877299842503025462917506948739765507780809009
Line 983, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 434998116 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 434998116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.104266785193418517692227744084008037288059544142665182284643400357651342567963
Line 6172, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31709844125 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31709844125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 43 more failures.

Test i2c_target_stress_all_with_rand_reset has 19 failures.

7.i2c_target_stress_all_with_rand_reset.13586124197443540372026684552241392544252588429644605421172754997325873815673
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1198579395 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1198579395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.i2c_target_stress_all_with_rand_reset.3559190463393951928452256916300754239490744554832777510510203046287718516240
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1835050750 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1835050750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test i2c_host_stress_all has 2 failures.
  - 5.i2c_host_stress_all.95083482917508820005014599197087656346480407709783858664536955387728282027225
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:09903440-2b4d-40e4-92e7-f332b1d04316
```
  - 43.i2c_host_stress_all.115503907620116781433896159045299654255409463897057408004265149073403242083948
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:b7a916d4-4f0f-42a0-99fb-c9202ff520f7
```
- Test i2c_target_stretch has 5 failures.
  - 6.i2c_target_stretch.80905232294510401210602500912067390140466117071506069444781247668721742916809
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  Job ID: smart:e79a958c-c914-4f73-bab1-39bc42e4ad67
```
  - 14.i2c_target_stretch.110369642983017076254784819258988873417060261024938330237166549084103033726765
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest/run.log
```
  Job ID: smart:23a42c97-8a57-42b1-9d55-ee1e5a690154
```
  - ... and 3 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 12.i2c_host_stress_all_with_rand_reset.10601973190469490597957604460226617223433232402445276115584443265473749642616
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9381b150-ed8f-4c48-addb-ff20c6419124
```
  - 14.i2c_host_stress_all_with_rand_reset.26479852424294901871163301866905556828673573018044410105248300821436916933608
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3db0fd0e-8641-4d82-8480-9d53e5f485e2
```
  - ... and 2 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 40.i2c_target_stress_all_with_rand_reset.97085120715039306515239881417923939659293005314968743878874461141710840212529
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e6ac911f-db9b-44db-b1b4-063d1be6ad21
```
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 8 failures:
- Test i2c_same_csr_outstanding has 8 failures.
  - 0.i2c_same_csr_outstanding.76329696954885455617613722976366030740237568728251074457738946052610967925105
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  66963176 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (2 [0x2] vs 0 [0x0]) addr 0xb61444f0 read out mismatch
  UVM_INFO @  66963176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_same_csr_outstanding.16593694496532306205169431177305562865754296853974314117897062978958773850046
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  23323936 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (3 [0x3] vs 0 [0x0]) addr 0x5d831a70 read out mismatch
  UVM_INFO @  23323936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:

Test i2c_target_stress_all_with_rand_reset has 6 failures.

2.i2c_target_stress_all_with_rand_reset.68142308170146187134432551521134893228907432181897834192626509445726323077549
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 13708693765 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 13708693765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.59590893905359831705415004222843927694790378255001202738905519140026520901509
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 555944948 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 555944948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_csr_bit_bash has 2 failures.

2.i2c_csr_bit_bash.66345618441548207127530761161532642421862022572628371803450295713579265220547
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1130001258 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1130001258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_csr_bit_bash.112489021735320966066037566388927808396706657839552643311521380754970972310728
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 243684582 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 243684582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * has 7 failures:

Test i2c_tl_intg_err has 2 failures.

0.i2c_tl_intg_err.73404290200830224639006427129304984521481790000459758943900484876691369906988
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @   3938281 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   3938281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_tl_intg_err.75877508089505601694651402440288698548502401333816026927439903923034781533942
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @  65363507 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @  65363507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_csr_mem_rw_with_rand_reset has 2 failures.

2.i2c_csr_mem_rw_with_rand_reset.30089577407173017903612220458695890725070959779253270205833403521168176608173
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 119963792 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @ 119963792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_csr_mem_rw_with_rand_reset.28389204042556813507756957489007288295798988813776219055838800204535615808577
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @   3404272 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   3404272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_csr_rw has 3 failures.

8.i2c_csr_rw.97463709764696577731715764206193697316586107276550328141853720133850854646380
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_csr_rw/latest/run.log

  UVM_ERROR @   5290700 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   5290700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_csr_rw.85960881109795128800813933454122136221186850293295957005036525812752175168283
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_csr_rw/latest/run.log

  UVM_ERROR @   9243691 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   9243691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: * has 6 failures:

Test i2c_tl_intg_err has 5 failures.

7.i2c_tl_intg_err.79783218578396605961260068320246966075851524473308324495643818030453678903468
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @ 106144433 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @ 106144433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_tl_intg_err.94810683710370413318819524615860789610855531892297045416425469551874622263192
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @   2030461 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   2030461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test i2c_csr_rw has 1 failures.

13.i2c_csr_rw.99097444230997877002726575542846013624166116866446545692814277097095385028357
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_csr_rw/latest/run.log

  UVM_ERROR @  41159922 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @  41159922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 0.i2c_target_stress_all_with_rand_reset.25557374376796836003416442264059828661775826608864202142528844769263867514945
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12982056847 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 12982056847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.i2c_target_stress_all_with_rand_reset.15691938862577768975934940683757943619837421337275546700343681791644591825010
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10506994039 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10506994039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 1 failures.
  - 13.i2c_target_unexp_stop.6446716431760492704224634322886457558156549746439837980809041079088522630083
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 10302391046 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10302391046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
- Test i2c_target_stress_all has 3 failures.
  - 8.i2c_target_stress_all.61735985146040854491662517014225758518184582453756360346917729119854430524523
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 30229992710 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (19 [0x13] vs 18 [0x12])
  UVM_INFO @ 30229992710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.i2c_target_stress_all.62222626735358182104955015803001554425941512725656050256039989264069854609499
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 7362394938 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 7362394938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 47.i2c_target_stress_all_with_rand_reset.98906262452447217446957463706928471085133342447904249024924589220665426871103
    Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8528375393 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 3 [0x3])
  UVM_INFO @ 8528375393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 11.i2c_target_stress_all_with_rand_reset.88826417625763986333767172672805569064917615111380511277602990981390260756762
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11092031717 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xeb3a614) == 0x0
  UVM_INFO @ 11092031717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.i2c_target_stress_all_with_rand_reset.56974612781752916045495648068547435295078159654497483035883485283940843082708
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10420988801 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x80160c94) == 0x0
  UVM_INFO @ 10420988801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * Wrote i2c_reg_block.acq_fifo_next_data[*]: * has 3 failures:

Test i2c_csr_bit_bash has 3 failures.

0.i2c_csr_bit_bash.88892527538488318776211654579271502235667760968548440614460496932705703252514
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log

  UVM_ERROR @ 454086820 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
  UVM_INFO @ 454086820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_csr_bit_bash.109203721407573335735505389946490595478623457725665405626839042732070074873238
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log

  UVM_ERROR @ 1639226524 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
  UVM_INFO @ 1639226524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 23.i2c_host_stress_all_with_rand_reset.58288340755258889129169790464920573941619880121523415563943594977057667971701
    Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 236326060 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction WRITE item mismatch!
  --> EXP:
  ------------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 28.i2c_target_stress_all_with_rand_reset.44525821240087301612821185761672402228383902116999736030502576792146954266221
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26446296 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  26446296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```