9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.563m | 1.813ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.136m | 11.978ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 25.916us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 18.625us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.870s | 2.123ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.870s | 224.129us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.460s | 102.209us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 18.625us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.870s | 224.129us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.180s | 123.581us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.000m | 53.946ms | 43 | 50 | 86.00 |
| V2 | host_maxperf | i2c_host_perf | 43.111m | 30.308ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.720s | 31.013us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.976m | 9.113ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.526m | 2.105ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.230s | 545.825us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 20.620s | 394.326us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.900s | 396.613us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.445m | 4.765ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 46.220s | 1.959ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.734m | 1.969ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.650s | 4.015ms | 9 | 50 | 18.00 |
| V2 | target_glitch | i2c_target_glitch | 10.460s | 6.767ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 12.693m | 47.747ms | 1 | 50 | 2.00 |
| V2 | target_maxperf | i2c_target_perf | 1.350s | 112.421us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.215m | 1.773ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.140s | 5.452ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.370m | 10.097ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.670m | 10.060ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 32.792m | 59.451ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.215m | 1.773ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.893m | 24.137ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.550s | 3.036ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 57.936m | 18.623ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.290s | 1.255ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.120s | 2.411ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 5.976m | 9.113ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.660s | 45.620us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 47.514us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.850s | 170.952us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.850s | 170.952us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 25.916us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 18.625us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.870s | 224.129us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 56.300us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 25.916us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 18.625us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.870s | 224.129us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 56.300us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1242 | 1392 | 89.22 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.330s | 128.870us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.150s | 106.221us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.330s | 128.870us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.801m | 39.445ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 16.737m | 25.672ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 27.150s | 609.851us | 50 | 50 | 100.00 | |
| TOTAL | 1470 | 1722 | 85.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 36 | 30 | 25 | 69.44 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.06 | 98.12 | 92.46 | 97.66 | 91.30 | 95.42 | 98.67 | 91.81 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 92 failures:
0.i2c_target_perf.93906822255040080180732097046019503223570041715756723059809628182769269540868
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 109601088 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 109601088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.33583471002068949522627604978310497678829056506087510645120268803186269769420
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 51303884 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 51303884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 46 more failures.
0.i2c_target_stress_all.316719597481811343456993161526485407677448568589858425994218808122860141409
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 37229987 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 37229987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.66151308052732258363290391556017357594747095236609019558897155358105163823164
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 11667639 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 11667639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
2.i2c_target_stress_all_with_rand_reset.107742852796644632102560284632107474850800307743608272064944856752447475416391
Line 300, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5123046493 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5123046493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.115041228449934407496958264203462067305541504687205181117563018531296347403726
Line 306, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5603413404 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5603413404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 61 failures:
0.i2c_host_stress_all_with_rand_reset.75024968165123773313040817044242990398768026408182114811890536233177997188706
Line 5854, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43392511924 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 43392511924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.68040721773342278654373387112907781671459043061163904889433201713957399349772
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 503325769 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 503325769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 43 more failures.
1.i2c_target_stress_all_with_rand_reset.79867648721976463110369337896453326733258215977181094889736554265372684485211
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2830808655 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2830808655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.17123847197804400091011006349715560366428724171537944944039451589381118681557
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1059913829 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1059913829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 60 failures:
0.i2c_target_unexp_stop.17059589273022407737373839715821673786515820500826994825797558472368814615471
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 715676044 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 715676044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.110059337502364144318664615554833604362186012935489686546165769183090045186075
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 7503576410 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 7503576410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
1.i2c_target_stress_all.108123406385846136692013141757044129128421552247660591163319007678901754328376
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2649335580 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2649335580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.28964811374350725373368519191234904036137792738838141352797410684846588956579
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7453322458 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 7453322458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
2.i2c_host_stress_all.96564706103890172795185045212089630310675099283573754161147832757594778943877
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:3a9747db-e8f2-44d5-bfe1-711b4f6b5f51
14.i2c_host_stress_all.73918465618890792327166924268442173644614117572451644234829889580730836960996
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
Job ID: smart:23fb1f6f-912d-4e1f-a720-6216658223e8
... and 4 more failures.
9.i2c_target_stretch.70963964700622059542117979305934487344170686774187230724593501034230451539281
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
Job ID: smart:600e4b95-15cf-4cf4-ba00-884180361fe0
22.i2c_target_stretch.98285328174507737079160623995525745278708004491319915265004153923016831767642
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
Job ID: smart:18ec5d21-ebef-4f3c-8745-fa0602047eee
... and 1 more failures.
16.i2c_host_stress_all_with_rand_reset.24425946894553130430217648035380654681703051376169669383415229059988789265884
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:751813a0-843d-4fd5-9a69-0d0ef7332ede
33.i2c_host_stress_all_with_rand_reset.109769153615539459763967289518681905204276782254917559403999031146157422824095
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:288464e1-b594-419e-997e-5606d7cfc661
... and 1 more failures.
30.i2c_target_stress_all_with_rand_reset.72540376175048655879094911911800005687896198814599157509278863762379389936296
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:dbdd752c-816b-454c-87ef-0cc5bfc8ce4c
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 6 failures:
Test i2c_target_perf has 2 failures.
13.i2c_target_perf.114356470473393950736990384352270332404287549248750918256398028616333365751563
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log
UVM_ERROR @ 238799863 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 238799863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_perf.64911728006897180805790783692583396770298469338390085401322077561151469286601
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_perf/latest/run.log
UVM_ERROR @ 79247481 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 79247481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 4 failures.
22.i2c_target_stress_all_with_rand_reset.69697435839463503099014993279957742201304014548004825656906776034350358133780
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3988310858 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3988310858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_stress_all_with_rand_reset.66095221988399709937704229086738725254308526302120300280429944293074372871878
Line 368, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10260700957 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 10260700957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 4 failures:
Test i2c_target_unexp_stop has 1 failures.
5.i2c_target_unexp_stop.84904073598873532130966333951074010587071273943583003657064743323083294516746
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 27148273718 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 27148273718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 3 failures.
16.i2c_target_stress_all_with_rand_reset.50169056052383344962465339286737247120335660139123750845606299255380791921567
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10447705715 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10447705715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stress_all_with_rand_reset.58220530987708867904778997292841290900990938321533380964250075309820557158029
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11803856808 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11803856808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
7.i2c_target_stress_all_with_rand_reset.78590669926555753923566755503337414136386647481940047683334558541404786695284
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4970913768 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 8 [0x8])
UVM_INFO @ 4970913768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.54697588945570694961605351328327504856610495533827871714061420358617067164239
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6350659025 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 4 [0x4])
UVM_INFO @ 6350659025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 2 failures.
12.i2c_target_stress_all.3222330155964481909448271891586084049109917854191026583407410230012659416264
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1482049224 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 11 [0xb])
UVM_INFO @ 1482049224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_stress_all.20821805261047401048792801027574064726415719910690175791409840005713340403100
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2947821758 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (18 [0x12] vs 14 [0xe])
UVM_INFO @ 2947821758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
0.i2c_target_stress_all_with_rand_reset.56190448043482594307352371476091670234253533493314602507323622511867567573899
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11374783380 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x960e6594) == 0x0
UVM_INFO @ 11374783380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.104776292445731903272665310200984793268566295475537686905981432283560440162785
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 45307526329 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xd06e6014) == 0x0
UVM_INFO @ 45307526329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
Test i2c_csr_bit_bash has 1 failures.
2.i2c_csr_bit_bash.115004499189699526131020711376772627016053761053999986092779499726691203453682
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 787121689 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 787121689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 2 failures.
3.i2c_target_stress_all_with_rand_reset.70845196401879010602381155103086668490043334865067869185040264453283673089815
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2077402244 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2077402244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_stress_all_with_rand_reset.30628156971199146873321215008623099216919837415094171726178510655648641828888
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 824024616 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 824024616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 3 failures:
Test i2c_host_stress_all has 1 failures.
26.i2c_host_stress_all.15664786625376572214388693263648286864022210206485723732723714045067810300408
Line 4837, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 100789826024 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all_with_rand_reset has 2 failures.
32.i2c_host_stress_all_with_rand_reset.51118008934387781686968619500990637591588838035592232488996796680547126196479
Line 9229, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55872819230 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
49.i2c_host_stress_all_with_rand_reset.19911556759372655038487850681457091166439649761074123734547539038452665446521
Line 6335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90422980533 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
4.i2c_csr_bit_bash.11552386295790481859314025685010824474082227693508719792227244473704685620573
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 817942441 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 817942441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
37.i2c_target_stress_all_with_rand_reset.54791091741006564602393116639863321238266792034399782767897833477562724552040
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2537675669 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (166 [0xa6] vs 132 [0x84])
UVM_INFO @ 2537675669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 1 failures:
43.i2c_target_stress_all_with_rand_reset.87524487976355902123397001481203933908010637408429369207205627590759257829283
Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11062729545 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 11062729545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---