I2C Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.664m	3.718ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	50.100s	2.528ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	87.149us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.770s	107.527us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.050s	527.555us	4	5	80.00
V1	csr_aliasing	i2c_csr_aliasing	1.870s	510.707us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.380s	295.415us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	107.527us	20	20	100.00
		i2c_csr_aliasing	1.870s	510.707us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	host_error_intr	i2c_host_error_intr	2.120s	126.089us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	56.210m	81.058ms	50	50	100.00
V2	host_maxperf	i2c_host_perf	32.704m	49.814ms	49	50	98.00
V2	host_override	i2c_host_override	0.720s	29.206us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.423m	4.194ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.682m	2.268ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.170s	609.565us	50	50	100.00
		i2c_host_fifo_fmt_empty	18.930s	372.500us	50	50	100.00
		i2c_host_fifo_reset_rx	10.670s	418.086us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.801m	9.640ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	41.880s	3.974ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.764m	2.367ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	7.080s	2.255ms	6	50	12.00
V2	target_glitch	i2c_target_glitch	9.970s	9.664ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	22.727m	53.392ms	3	50	6.00
V2	target_maxperf	i2c_target_perf	1.190s	534.494us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.345m	4.288ms	50	50	100.00
		i2c_target_intr_smoke	8.190s	7.251ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.220m	10.068ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.527m	10.048ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	34.823m	65.977ms	50	50	100.00
		i2c_target_stress_rd	1.345m	4.288ms	50	50	100.00
		i2c_target_intr_stress_wr	6.874m	21.817ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	7.520s	3.178ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	52.663m	35.388ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	5.620s	4.277ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	2.990s	568.315us	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.423m	4.194ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.660s	18.461us	50	50	100.00
V2	intr_test	i2c_intr_test	0.710s	27.535us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.740s	791.682us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.740s	791.682us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	87.149us	5	5	100.00
		i2c_csr_rw	0.770s	107.527us	20	20	100.00
		i2c_csr_aliasing	1.870s	510.707us	5	5	100.00
		i2c_same_csr_outstanding	1.120s	183.797us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	87.149us	5	5	100.00
		i2c_csr_rw	0.770s	107.527us	20	20	100.00
		i2c_csr_aliasing	1.870s	510.707us	5	5	100.00
		i2c_same_csr_outstanding	1.120s	183.797us	19	20	95.00
V2		TOTAL			1247	1392	89.58
V2S	tl_intg_err	i2c_tl_intg_err	2.450s	542.377us	20	20	100.00
		i2c_sec_cm	0.930s	244.251us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.450s	542.377us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.272m	40.995ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.113m	64.655ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	27.010s	678.391us	50	50	100.00
		TOTAL			1476	1722	85.71

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	36	30	24	66.67
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.73	97.85	92.37	97.66	89.57	95.18	98.67	91.81

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 98 failures:
- Test i2c_target_perf has 50 failures.
  - 0.i2c_target_perf.45959820473623928961637194136035605570571579497516542409635022153412980918434
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 277656859 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 277656859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.93221296141620225620067045987498137240557237427207367791846674639190047063999
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  43590332 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  43590332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.
- Test i2c_target_stress_all_with_rand_reset has 23 failures.
  - 0.i2c_target_stress_all_with_rand_reset.54362057133394842837087551422301928126116151680850770438424067191572285300390
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26882688 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  26882688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all_with_rand_reset.1527211242559720553662566387618294180647016802289724897098976021985807893424
    Line 317, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23384180617 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 23384180617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
- Test i2c_target_stress_all has 25 failures.
  - 2.i2c_target_stress_all.12905212373385394003953299985635427448765448006463118840111242952413244225274
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 127768859 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 127768859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_stress_all.52376054191042598320517170754077380185953676056628131416181203429131163675901
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 19291992118 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 19291992118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 61 failures:

Test i2c_target_unexp_stop has 44 failures.

0.i2c_target_unexp_stop.111035451615247264603550412707565454183407330450446735529614265195709924660194
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 1984597313 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1984597313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_unexp_stop.53351340045598912651200536787748421412543419805787020309996011278150219663069
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 4161741691 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4161741691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 42 more failures.

Test i2c_target_stress_all has 17 failures.

0.i2c_target_stress_all.27387839656712335817913620552215546011919474353460860728172842661523837808454
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 10362188230 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 10362188230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all.25304465786379898984703032438945773616347267276550855028827419565545340267961
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 20517863424 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 20517863424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:

Test i2c_host_stress_all_with_rand_reset has 39 failures.

0.i2c_host_stress_all_with_rand_reset.33922613826266365359910620296846268314274789744104679860242006234086562549385
Line 9764, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40995316781 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40995316781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.20185435028309017077370140033300064587342209382817458068464405420766504110747
Line 2232, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6342570486 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6342570486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 37 more failures.

Test i2c_target_stress_all_with_rand_reset has 11 failures.

5.i2c_target_stress_all_with_rand_reset.68637053128571989939902181853996488184840039402964530132979216422573534873088
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 200425577 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 200425577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.i2c_target_stress_all_with_rand_reset.23736639934970505315300314926080560152860180136143577070616726722495814388650
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 895495917 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 895495917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test i2c_host_stress_all_with_rand_reset has 7 failures.
  - 3.i2c_host_stress_all_with_rand_reset.32833944500271404768609102191673568876519070789877272124685964172498023128962
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3d6ad169-216f-426e-8ba3-05aeb7293f8d
```
  - 9.i2c_host_stress_all_with_rand_reset.26753042706285907966670015549183839565130118659717466358110685349314538513345
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1298bbaa-818e-42b5-a4a9-d7d3a811c884
```
  - ... and 5 more failures.
- Test i2c_target_stretch has 2 failures.
  - 23.i2c_target_stretch.80978649567747733665877707414350516934949773525546395980223154175855539034923
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stretch/latest/run.log
```
  Job ID: smart:66ebb400-8352-41ff-a408-d84aa792e075
```
  - 38.i2c_target_stretch.27138015648501744798859053793614770214206111840057944978266147263856242600245
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stretch/latest/run.log
```
  Job ID: smart:b87bbbed-c96d-4015-bc50-d0bf23e30fe0
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 1.i2c_target_stress_all_with_rand_reset.73381718095766616523780542025369630430801580081781976555950423091765970660333
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12905832572 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x62668014) == 0x0
  UVM_INFO @ 12905832572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.27483348593326324533251930710921686551730107054708960791197285430157705295992
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10270945462 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x50f23b94) == 0x0
  UVM_INFO @ 10270945462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 3.i2c_target_stress_all_with_rand_reset.49906935868286936635622621560201429460431912252687803997706036287357244437375
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 851556240 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 851556240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 7.i2c_target_stress_all_with_rand_reset.114006035097738729060221752581390883926450664474165799078923537299819203079620
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 8738845020 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 8738845020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.
- Test i2c_csr_bit_bash has 1 failures.
  - 3.i2c_csr_bit_bash.75187023506474323733040179443920933537168536399283958004495318788677132803302
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 527554735 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 527554735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 3 failures:
- Test i2c_host_stress_all_with_rand_reset has 3 failures.
  - 13.i2c_host_stress_all_with_rand_reset.67104428128446002156166991671039078502397966641772553754457564828185150664916
    Line 1850, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5447995990 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
  - 32.i2c_host_stress_all_with_rand_reset.40625402711929360612738898497549840432675305050452198616308324335795037415859
    Line 7410, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32677762630 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all has 3 failures.
  - 14.i2c_target_stress_all.15286860821817708536521105680801112871287926668955704608658215419201368320059
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 23327672759 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (20 [0x14] vs 19 [0x13])
  UVM_INFO @ 23327672759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.i2c_target_stress_all.1415376443590954592404480899469683561105895618057172620767899483250136288099
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 6105955136 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 4 [0x4])
  UVM_INFO @ 6105955136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 25.i2c_target_stress_all_with_rand_reset.52024573089674858360837462909006507701728134430004040045025260909135014384465
    Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9409994179 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (144 [0x90] vs 145 [0x91])
  UVM_INFO @ 9409994179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.i2c_target_stress_all_with_rand_reset.33066443106278900733597881276081514412629794088522756121174000328759005262700
    Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19258145576 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (205 [0xcd] vs 129 [0x81])
  UVM_INFO @ 19258145576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1148) [stop_interrupt_handler] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 13.i2c_target_stress_all.31844718143243571097512096843969659143412709818824944376277092679539750184079
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 38306262434 ps: (i2c_base_vseq.sv:1148) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 38306262434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_target_stress_all.92712081032147474579204037371892994462841314209276056723914914291071770894292
    Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 31996452187 ps: (i2c_base_vseq.sv:1148) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 31996452187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 20.i2c_target_stress_all_with_rand_reset.11782295004277742643253441421676075202939333455527656600325437855110319913606
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1060376984 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1060376984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.i2c_target_stress_all_with_rand_reset.105394980995451941436427415849683376640806206549473802561249461683031345966613
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1171712463 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1171712463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 4.i2c_target_stress_all_with_rand_reset.1228112099328829028661106583773608071023126172592994697940791793468044174114
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 815766682 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 815766682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_sync' has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 10.i2c_same_csr_outstanding.35276661718377350037196358584342104011494873636818713296219915727371336727835
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
```
      Offending 'scl_sync'
  UVM_ERROR @  16344456 ps: (i2c_core.sv:741) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @  16344456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 22.i2c_host_stress_all_with_rand_reset.83984095595704127559173976096680303295098010365762358926612225285228972158814
    Line 503, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1848356900 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (30 [0x1e] vs 31 [0x1f])
  UVM_INFO @ 1848356900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 42.i2c_host_perf.53399771857512681213882283085300959073541229557489848289346973652343311630442
    Line 1316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf/latest/run.log
```
  UVM_ERROR @ 20141970809 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 20141970809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 48.i2c_target_stress_all_with_rand_reset.114614186413870254240870204190320059265498029801657324661832123828545398867349
    Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 43449797044 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 43449797044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```