I2C Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.553m	1.877ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	51.720s	1.293ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.790s	29.377us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.790s	27.372us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.830s	2.367ms	3	5	60.00
V1	csr_aliasing	i2c_csr_aliasing	1.970s	112.872us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.370s	101.527us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.790s	27.372us	20	20	100.00
		i2c_csr_aliasing	1.970s	112.872us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	host_error_intr	i2c_host_error_intr	1.790s	903.800us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	50.550m	92.123ms	43	50	86.00
V2	host_maxperf	i2c_host_perf	31.400m	51.724ms	48	50	96.00
V2	host_override	i2c_host_override	0.790s	29.259us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.781m	8.308ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.744m	6.186ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.260s	343.028us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.190s	464.336us	50	50	100.00
		i2c_host_fifo_reset_rx	10.330s	186.198us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.971m	2.363ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	40.110s	3.620ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.554m	18.788ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	6.450s	1.622ms	9	50	18.00
V2	target_glitch	i2c_target_glitch	9.950s	4.477ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	6.157m	21.209ms	6	50	12.00
V2	target_maxperf	i2c_target_perf	1.110s	197.091us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.293m	7.412ms	50	50	100.00
		i2c_target_intr_smoke	7.920s	3.487ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.345m	10.039ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.523m	10.033ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	45.505m	71.976ms	50	50	100.00
		i2c_target_stress_rd	1.293m	7.412ms	50	50	100.00
		i2c_target_intr_stress_wr	4.455m	18.211ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	7.630s	23.634ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	38.596m	14.653ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	5.150s	1.199ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.370s	9.026ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.781m	8.308ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.660s	15.331us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	50.824us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.670s	127.732us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.670s	127.732us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.790s	29.377us	5	5	100.00
		i2c_csr_rw	0.790s	27.372us	20	20	100.00
		i2c_csr_aliasing	1.970s	112.872us	5	5	100.00
		i2c_same_csr_outstanding	1.230s	101.777us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.790s	29.377us	5	5	100.00
		i2c_csr_rw	0.790s	27.372us	20	20	100.00
		i2c_csr_aliasing	1.970s	112.872us	5	5	100.00
		i2c_same_csr_outstanding	1.230s	101.777us	20	20	100.00
V2		TOTAL			1241	1392	89.15
V2S	tl_intg_err	i2c_tl_intg_err	2.260s	226.905us	20	20	100.00
		i2c_sec_cm	1.030s	444.796us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.260s	226.905us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.908m	18.275ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.731m	18.136ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	26.750s	2.209ms	50	50	100.00
		TOTAL			1469	1722	85.31

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	36	30	24	66.67
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.65	97.85	92.15	97.66	89.57	95.18	98.67	91.49

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 99 failures:
- Test i2c_target_perf has 49 failures.
  - 0.i2c_target_perf.31232034564074284932073146891989070611220674922046905501603540206642984112650
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 179346368 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 179346368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.69330543940207773824785118810344382905588066624803526468305370532898006879526
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  58765617 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  58765617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 47 more failures.
- Test i2c_target_stress_all has 32 failures.
  - 0.i2c_target_stress_all.57370892415145085226032367007116582587802707258990483950299683284688960627884
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  37656042 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  37656042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all.72348083671576225695038520099055229544495753271241146891008428909812514386610
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 9175824146 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 9175824146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
- Test i2c_target_stress_all_with_rand_reset has 18 failures.
  - 0.i2c_target_stress_all_with_rand_reset.70737467371618720438902265659882906646510925160780716265149810779047422943806
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  13707886 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  13707886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_stress_all_with_rand_reset.41697530419829115360068089582875338490415254720761486168895950684232435242752
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 245054235 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 245054235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 56 failures:

Test i2c_host_stress_all_with_rand_reset has 41 failures.

1.i2c_host_stress_all_with_rand_reset.87120174928300285795663271955642266284383881927122385486457817532289237035468
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1279448291 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1279448291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_stress_all_with_rand_reset.113754922363384215125961152745803149365751484140491781066498631015678484216697
Line 1382, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2568473327 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2568473327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 39 more failures.

Test i2c_target_stress_all_with_rand_reset has 15 failures.

2.i2c_target_stress_all_with_rand_reset.12268274410269686376598694015255735070717726249945038341665435247808172009801
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 370677193 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 370677193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.100748845903374624226632639969754708160839836010616845678174440630787905409308
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 629480910 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 629480910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 51 failures:
- Test i2c_target_unexp_stop has 41 failures.
  - 0.i2c_target_unexp_stop.94885260000951312515601486093504227599307003596939800038062679198262057009863
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 3848046203 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3848046203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.43081309743532431925000071485351167228340608423258658708754439341459852961794
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2357788555 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2357788555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 39 more failures.
- Test i2c_target_stress_all has 10 failures.
  - 1.i2c_target_stress_all.28890329785013530770982628945073833151653945878778714107355372964494576879347
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 6394881382 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 6394881382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_stress_all.54010130127040808060051662463157739799082248025900253917203262960519147811257
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2501161085 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2501161085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test i2c_host_stress_all_with_rand_reset has 7 failures.
  - 0.i2c_host_stress_all_with_rand_reset.11376473897337813632351081226039734338006533371911284881203205405952693796089
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:517e1690-c5e0-492c-9aa1-b91ee28bcb19
```
  - 2.i2c_host_stress_all_with_rand_reset.113172534336492277477441273102263541876803599234471373242028900363539668911217
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3d7676a4-5aac-4714-acf9-defb19d79d80
```
  - ... and 5 more failures.
- Test i2c_target_stretch has 7 failures.
  - 3.i2c_target_stretch.75980107492943123926847805056787882725634598134871193176408402729929554812846
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  Job ID: smart:b9a4afc3-44e8-48b3-ab17-dfde699c6c98
```
  - 4.i2c_target_stretch.28638875455009470830067140229465472245964667650473397070465201449729309648674
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  Job ID: smart:a3930f53-49e1-4868-ae3f-961fb8366029
```
  - ... and 5 more failures.
- Test i2c_host_perf has 1 failures.
  - 7.i2c_host_perf.96125654072232394368349972767281917082855257594032090885854876010570268706164
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_perf/latest/run.log
```
  Job ID: smart:a2001814-9bd4-4229-ab59-ad90bd8e5b48
```
- Test i2c_host_stress_all has 6 failures.
  - 16.i2c_host_stress_all.9024109096231308230228786579292155594805640280022391482103058436046814846390
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:10bc8315-29ec-47d0-8609-9d7639a29e20
```
  - 21.i2c_host_stress_all.2804389870721957942637736402099371759710411770834641562579203174800090657803
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:18d6328b-bc07-491a-9d66-82762b026b2f
```
  - ... and 4 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 38.i2c_target_stress_all_with_rand_reset.102558355172984487618106351795739462609243211678090531738146475309846098935079
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a9e56e85-dde9-42d1-843d-ae01677da969
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 12 failures:
- Test i2c_target_stress_all_with_rand_reset has 11 failures.
  - 1.i2c_target_stress_all_with_rand_reset.19609394297721608950186925905436509762312325743373336885033808479478608500938
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1042605994 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1042605994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.i2c_target_stress_all_with_rand_reset.72353027638770787405060551348398965171933262402108360872738877315959656989777
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1105520443 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1105520443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 9 more failures.
- Test i2c_csr_bit_bash has 1 failures.
  - 4.i2c_csr_bit_bash.53103937117705594072787239928055954244797075206267220946963266616664656585425
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 195332560 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 195332560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 15.i2c_target_stress_all_with_rand_reset.61427228340345913237245136519356492272624405978635885668686940716342474401918
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12250269392 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x6769bd94) == 0x0
  UVM_INFO @ 12250269392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.i2c_target_stress_all_with_rand_reset.28757945261182073049284149033362174633409830912509983300940706216520057656060
    Line 311, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 18136081316 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf9519994) == 0x0
  UVM_INFO @ 18136081316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_host_stress_all_with_rand_reset.40809509963428051624306976364786385692896676396259547945485518746881729931256
    Line 1887, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2185670286 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
  - 34.i2c_host_stress_all_with_rand_reset.108072059696703730508822085430567056527716511497374115819682015665928498286059
    Line 648, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2253687101 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all has 1 failures.
  - 8.i2c_target_stress_all.80592306705655123689306918731707040197228321132563177788991454091364199886922
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2439044040 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 10 [0xa])
  UVM_INFO @ 2439044040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 28.i2c_target_stress_all_with_rand_reset.107854696564942025561904433296292789813560753454342468273934352210927903315674
    Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6694235953 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 5 [0x5])
  UVM_INFO @ 6694235953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 2 failures:
- Test i2c_host_perf has 1 failures.
  - 22.i2c_host_perf.27828427736092190423537083256422299871582736780417527227547771358779724583470
    Line 1292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_perf/latest/run.log
```
  UVM_ERROR @ 10613130813 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 10613130813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 1 failures.
  - 30.i2c_host_stress_all.64203189918435880825723174709355319639113699568565037039072499039035752142860
    Line 1845, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 51071692636 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 51071692636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
- Test i2c_csr_bit_bash has 1 failures.
  - 1.i2c_csr_bit_bash.55192456904574448266410722746612056014658423910858028201581350725404194904225
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
  UVM_ERROR @ 217116698 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
  UVM_INFO @ 217116698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 1 failures:
- Test i2c_target_perf has 1 failures.
  - 43.i2c_target_perf.29887559592920063789445340231305323182536727981242548682449350229677379535111
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 123545846 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 123545846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1148) [stop_interrupt_handler] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 45.i2c_target_stress_all.28116013995016332763448264091487811245816793333622695368239442756083621918555
    Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 80735169613 ps: (i2c_base_vseq.sv:1148) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 80735169613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```