ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.393m | 20.517ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.580s | 5.867ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.750s | 23.400us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 80.758us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.650s | 628.125us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.380s | 247.171us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.720s | 39.349us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 80.758us | 19 | 20 | 95.00 |
| i2c_csr_aliasing | 1.380s | 247.171us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.660s | 282.971us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 33.794m | 17.264ms | 44 | 50 | 88.00 |
| V2 | host_maxperf | i2c_host_perf | 35.624m | 48.687ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.720s | 46.763us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.619m | 8.970ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.987m | 12.093ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.200s | 705.536us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.600s | 638.168us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.390s | 431.620us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.211m | 8.865ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 42.210s | 1.010ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.958m | 8.829ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 6.930s | 4.592ms | 11 | 50 | 22.00 |
| V2 | target_glitch | i2c_target_glitch | 11.320s | 9.605ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 17.049m | 40.192ms | 3 | 50 | 6.00 |
| V2 | target_maxperf | i2c_target_perf | 1.090s | 83.394us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.359m | 3.610ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.610s | 6.143ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.308m | 10.114ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.509m | 10.031ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 44.814m | 65.070ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.359m | 3.610ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.092m | 23.022ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.690s | 1.475ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 53.285m | 24.760ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.060s | 6.362ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 2.980s | 495.058us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 5.619m | 8.970ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.660s | 45.058us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.790s | 19.833us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.010s | 737.546us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.010s | 737.546us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.750s | 23.400us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 80.758us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 1.380s | 247.171us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 279.182us | 10 | 20 | 50.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.750s | 23.400us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 80.758us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 1.380s | 247.171us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 279.182us | 10 | 20 | 50.00 | ||
| V2 | TOTAL | 1236 | 1392 | 88.79 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.480s | 150.900us | 15 | 20 | 75.00 |
| i2c_sec_cm | 1.040s | 98.083us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.480s | 150.900us | 15 | 20 | 75.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.646m | 36.154ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.270m | 29.863ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 32.940s | 3.237ms | 50 | 50 | 100.00 | |
| TOTAL | 1458 | 1722 | 84.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 36 | 30 | 23 | 63.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.67 | 97.22 | 92.08 | 97.66 | 83.74 | 94.60 | 98.67 | 91.70 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 92 failures:
0.i2c_target_perf.25613532178488744757263474818673403082746996823704901179092314768940022932305
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 24521092 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 24521092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.46760278182784082243323241111587086263862037161819498208265992013487861130436
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 5955347 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5955347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.i2c_target_stress_all_with_rand_reset.100375192034008371883750728638893440459874957992225021503328154605501635438338
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3538432800 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 3538432800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.47574490722691863588417614863930855813722514393703817831315496118952643018841
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 65450070 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 65450070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
2.i2c_target_stress_all.112696343405710960232881652059237541922908090477063138443890889299440589925838
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 40192059403 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 40192059403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.247335698928517468650467668778975921909098491041636694356508025323397681002
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 12981563254 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 12981563254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 55 failures:
0.i2c_target_unexp_stop.101652589494359949693290704079304546901311893718254543474159880462037872958014
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1577181313 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1577181313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.91356924790328705578213461150576090086891242137023798948658436826663209680779
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3399360947 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3399360947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
0.i2c_target_stress_all.112463261570414678955496541593822320470174085089020502653929802653529098710667
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1625879016 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1625879016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.4668176960438672807793328025704616230129297716197650283487339193027174082352
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 10584656940 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 10584656940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 55 failures:
1.i2c_host_stress_all_with_rand_reset.68289273554269404942643186411248497889167299563039588509814659111887420575445
Line 916, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1651568070 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1651568070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.106269468763520923301089792797897379202874174395699882117729936020923690896710
Line 1219, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4056155019 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4056155019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
2.i2c_target_stress_all_with_rand_reset.113397311740091215896436561508752302343099443049826360369590918483304067988274
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 108964543 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108964543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.100947375731810701335885941727949462293834087216984687224402097687690097411183
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5673815493 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5673815493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
Test i2c_host_stress_all_with_rand_reset has 8 failures.
0.i2c_host_stress_all_with_rand_reset.22960064930529275139293052670892256603365642236990772573927339811575972406184
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1a986d29-ee7c-4d7e-87cb-7f87270df822
6.i2c_host_stress_all_with_rand_reset.10435036746993222491023456617164483577753623594613264201183629467980308515191
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:5be0712a-fc70-4b42-9b54-70dceca69365
... and 6 more failures.
Test i2c_host_stress_all has 6 failures.
1.i2c_host_stress_all.114167588815704872786728457953585895121525229981444246570690684867643303156258
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:24353979-ae90-42d5-8b75-7c4979c8b6da
7.i2c_host_stress_all.77715179184023652280312578011717500444209601531895224575571880262660461870399
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:e0efbb43-2e1b-4d44-9140-59cc014f596a
... and 4 more failures.
Test i2c_target_stretch has 3 failures.
3.i2c_target_stretch.85196894659104710370658427592068708528959342082544882372504729480643850019191
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
Job ID: smart:8d4bca55-8799-4967-a774-21ba80082345
30.i2c_target_stretch.84224458298505431957954608368356778882563878159346757952953490466257307815610
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
Job ID: smart:12819a3b-8f4d-4bc9-8d04-18e114c339ee
... and 1 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
10.i2c_target_stress_all_with_rand_reset.70985549971966066533864897207230039052531563908371380423262711947423353609782
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:dd22661d-1c39-48a2-b926-6cf0b816acd0
47.i2c_target_stress_all_with_rand_reset.30822837320808827382489002100164343604113324669082972729481708248250961993900
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ecca6914-b61b-4fa6-bbde-4d3ecd19b338
Test i2c_host_perf has 1 failures.
22.i2c_host_perf.80993437813503330895315449594309299363953710669297446256014113081587831814922
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_perf/latest/run.log
Job ID: smart:970880b9-0c34-4d1a-abe8-f0437e0ad958
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 8 failures:
0.i2c_same_csr_outstanding.17853780213948264447668938999297497346976292902093708781620545122391634754242
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 13253495 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf7762c70 read out mismatch
UVM_INFO @ 13253495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_same_csr_outstanding.68305324211178400762548164729919767389886171527818760589841126423567014597721
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 28079774 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (3 [0x3] vs 0 [0x0]) addr 0x8d7c0970 read out mismatch
UVM_INFO @ 28079774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 5 failures:
4.i2c_target_stress_all_with_rand_reset.81080793698278584974363226176370929625169435454720646702004349935115512967752
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11538409354 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11538409354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.20941490018096015712011405126303680349284287009526122779180199024767602858206
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10067087553 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10067087553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
10.i2c_target_unexp_stop.51221962640168811938087721190726361884649400719282345504426751828508418890751
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 12610337006 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12610337006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_target_unexp_stop.57316992690975838394537883808202459734723236088244874788504642950152989807175
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 14949617613 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 14949617613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * has 5 failures:
Test i2c_csr_rw has 1 failures.
4.i2c_csr_rw.84357885462550551198040357411192073586512710598297002226037434220747546844900
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_rw/latest/run.log
UVM_ERROR @ 18251657 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 18251657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 3 failures.
8.i2c_tl_intg_err.17611135846144319530403925644185160000641223004439963865332366061629128247002
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 4262150 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 4262150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_tl_intg_err.24398774967825696785960585645063171605230313930905533321057834267404082703669
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 96624471 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 96624471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
12.i2c_csr_mem_rw_with_rand_reset.27693098491167962325609203233496242133408245358606988157083327017727642786784
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 7684210 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 7684210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
12.i2c_target_stress_all_with_rand_reset.71204745627181688511592340654621526401424748365674563009653184185313255530295
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2722756860 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2722756860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stress_all_with_rand_reset.113395541428397313684256639054418877467816708157478428146967324446831436572265
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 4414224837 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 4414224837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 5 failures:
Test i2c_target_stress_all has 2 failures.
13.i2c_target_stress_all.111721007638491359546108768426201410792779810906591287689624441505841519255244
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 15775630967 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (16 [0x10] vs 15 [0xf])
UVM_INFO @ 15775630967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_stress_all.76772276632415717054248119940004325421212046166451380481933242929388485685083
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 12095520140 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 7 [0x7])
UVM_INFO @ 12095520140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 3 failures.
17.i2c_target_stress_all_with_rand_reset.61352413387112543132821493272934399952691810597137230451183763478225457624734
Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2352393983 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (16 [0x10] vs 19 [0x13])
UVM_INFO @ 2352393983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all_with_rand_reset.78028175614997815013731851056503945277785829507538906777559589531425113715000
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 824254601 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 2 [0x2])
UVM_INFO @ 824254601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
19.i2c_target_stress_all_with_rand_reset.106896629126657430297834351957821449622097889045036267779329396841754679152813
Line 326, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14673032615 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x60fd8214) == 0x0
UVM_INFO @ 14673032615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all_with_rand_reset.22824315971389068845233952045645585790089449093367670472017777387543413396700
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25686954364 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xd3c2e194) == 0x0
UVM_INFO @ 25686954364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: * has 2 failures:
1.i2c_tl_intg_err.100768031360214631727344192832426780279656073611853675794400080206283498251853
Line 355, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 321801079 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 321801079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_tl_intg_err.14091162635659657927459509122372677732001061827913585388845863285487895750451
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 42721214 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 42721214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
11.i2c_same_csr_outstanding.70150164149005928236396756236336321386519047669455834807487567927517038108157
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 13965522 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 13965522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_same_csr_outstanding.102500197370247021459490704698389975345502823924631496099776063993495050588011
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 43003228 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 43003228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 2 failures:
Test i2c_target_perf has 1 failures.
13.i2c_target_perf.73133827140671919089155467743677364567290433234679118656184818737758711455948
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log
UVM_ERROR @ 145346946 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 145346946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
43.i2c_target_stress_all_with_rand_reset.21016406405922345794117868813531017212768125000797832847616428575390291186653
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50141799 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 50141799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1165) [stop_interrupt_handler] wait timeout occurred! has 2 failures:
25.i2c_target_stress_all.9888210850988857988957929420537500084240673818733325061497845560601935354113
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 26255117250 ps: (i2c_base_vseq.sv:1165) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 26255117250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stress_all.108915017140721208163687131197757670082683030155505913283340782358434308261415
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 12277598380 ps: (i2c_base_vseq.sv:1165) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12277598380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * Wrote i2c_reg_block.acq_fifo_next_data[*]: * has 1 failures:
2.i2c_csr_bit_bash.104245571597058238385429135779358182244399976887230771454291689255074072403682
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
UVM_ERROR @ 628124576 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
UVM_INFO @ 628124576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
5.i2c_host_stress_all_with_rand_reset.43641049558237733529266317759673287813449067036948370539359820969704033628035
Line 14174, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
6.i2c_target_stress_all_with_rand_reset.85066377930030855154085492889158539504951313129741582897234041077123472151239
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8938897990 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (40 [0x28] vs 90 [0x5a])
UVM_INFO @ 8938897990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---