0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.448m | 11.699ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.760s | 1.506ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 66.999us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 25.936us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.510s | 990.230us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.250s | 336.437us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.390s | 32.959us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 25.936us | 19 | 20 | 95.00 |
| i2c_csr_aliasing | 2.250s | 336.437us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 150 | 155 | 96.77 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.170s | 154.968us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 50.548m | 98.025ms | 46 | 50 | 92.00 |
| V2 | host_maxperf | i2c_host_perf | 55.860m | 18.359ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.740s | 86.972us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.265m | 16.497ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.736m | 2.330ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.160s | 480.326us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.370s | 2.094ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.790s | 1.796ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.218m | 4.878ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 38.450s | 816.571us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.507m | 7.957ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 6.740s | 7.186ms | 8 | 50 | 16.00 |
| V2 | target_glitch | i2c_target_glitch | 10.030s | 8.666ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 19.355m | 34.692ms | 3 | 50 | 6.00 |
| V2 | target_maxperf | i2c_target_perf | 1.110s | 228.174us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.181m | 7.995ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.970s | 1.619ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.284m | 10.053ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.400m | 10.150ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 30.646m | 58.212ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.181m | 7.995ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.007m | 23.704ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.090s | 3.337ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 52.963m | 33.754ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.380s | 2.190ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.320s | 618.350us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 5.265m | 16.497ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.690s | 29.130us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 23.394us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.630s | 129.171us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.630s | 129.171us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 66.999us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 25.936us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.250s | 336.437us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.550s | 947.601us | 11 | 20 | 55.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 66.999us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 25.936us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.250s | 336.437us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.550s | 947.601us | 11 | 20 | 55.00 | ||
| V2 | TOTAL | 1235 | 1392 | 88.72 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.450s | 128.029us | 17 | 20 | 85.00 |
| i2c_sec_cm | 1.060s | 151.692us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.450s | 128.029us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.740m | 53.667ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 10.937m | 28.197ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 22.070s | 536.990us | 50 | 50 | 100.00 | |
| TOTAL | 1457 | 1722 | 84.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 36 | 30 | 23 | 63.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.63 | 97.19 | 92.04 | 97.66 | 83.74 | 94.53 | 98.67 | 91.60 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 95 failures:
0.i2c_target_perf.63576864375835343718357299433761089385008375924260087604778332488065020321799
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 166709508 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 166709508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.84466336055616230437294586814715580322385843511641936065814253075412877879039
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 60387447 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 60387447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 46 more failures.
0.i2c_target_stress_all_with_rand_reset.42050989334388193158980836541296073176346281270038914026182440859047684679197
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38870864 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 38870864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.12869213202089939928663706472897186893727115258797621478788571415928006583918
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 148818552 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 148818552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
4.i2c_target_stress_all.10324843957961896484536328539406888003513479782364443927332885955405758025443
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1426499699 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 1426499699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.72895905620672584944091361477948978457691054496860145003706195703520358285988
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 41129264 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 41129264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 61 failures:
0.i2c_target_unexp_stop.94710829530411460997367490782969828473304934415359513173833801473457880124050
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3500622027 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3500622027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.6657857449243350809489260703641475473740015156456488954338663600291585473834
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3694341770 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3694341770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
0.i2c_target_stress_all.101549351976660798742756871121678522778836374774847463468536230236116825906008
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5648442882 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 5648442882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.25587542657488440815258263685899757954652393247752145864268178999727671359649
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1261959793 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1261959793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 59 failures:
0.i2c_host_stress_all_with_rand_reset.52281775704338252324581873299906277110488877381457305363084700702407849337163
Line 6379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9903189130 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9903189130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.18379911814989147755914473594908742677098878803392864462010472981357909167514
Line 1135, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24174204907 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24174204907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
3.i2c_target_stress_all_with_rand_reset.1025852442146498935725866902516780987649129400038860284321610939275194745882
Line 350, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13991447109 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13991447109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.59658108269992960899317307684190779453124184337174125644437687900425607253277
Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7901039501 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7901039501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
4.i2c_host_stress_all.67561496428755763942542233558043586254446665613018052523398010341124344941672
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
Job ID: smart:c462004a-c822-4eeb-a68b-cefd1dc33427
5.i2c_host_stress_all.56583409632058962747027310301031746467750800692555904553015799066010395646573
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:b91b7662-b5da-4b8d-9ad8-a290c3eb9d68
... and 2 more failures.
7.i2c_target_stretch.55367728064283675142397731079525112762832791435597278702744310982716822099429
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
Job ID: smart:b4ebe93c-607a-4248-9edd-41155bc249b7
19.i2c_target_stretch.43185341772956336163780173829152270893484137992409935922916178910363822752259
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
Job ID: smart:0090ca4a-0d32-489c-9197-519c5750c588
... and 1 more failures.
26.i2c_host_stress_all_with_rand_reset.12849031265345299657390817340551705988064828472918160174960476032669851563919
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b831ab6c-760a-4afc-a9d7-c17766e15872
32.i2c_host_stress_all_with_rand_reset.75368218379499711918425928982504230721551126541718150939734278837154257635386
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ed1f810f-5aef-47ed-b7ef-ed1c1af148ba
... and 1 more failures.
42.i2c_host_perf.96354976058785256773022996180913563308509848088922584798027941400803387295854
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf/latest/run.log
Job ID: smart:bbf2e7d6-c751-4af4-8119-9f5cb88aa401
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 8 failures:
2.i2c_same_csr_outstanding.112509062293482271813671905383547835446093108812308965575174141773250731160728
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 3920206 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (7 [0x7] vs 0 [0x0]) addr 0x28d8c70 read out mismatch
UVM_INFO @ 3920206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_same_csr_outstanding.113983904399469821919316483638015225464668708096218276046525012238716434248535
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 140087888 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (5 [0x5] vs 0 [0x0]) addr 0x695ed6f0 read out mismatch
UVM_INFO @ 140087888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 6 failures:
Test i2c_target_perf has 2 failures.
3.i2c_target_perf.106517010491979249641032795750757709557766739233090681320209519664810051458407
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
UVM_ERROR @ 53434335 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 53434335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.i2c_target_perf.108558444204570279209820571116386722090311605019802263179742923988663851380556
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_perf/latest/run.log
UVM_ERROR @ 187462751 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 187462751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 4 failures.
4.i2c_target_stress_all_with_rand_reset.5791981201277854685843721979184129369355556498467943234628533844132861027044
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 761953282 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 761953282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all_with_rand_reset.98938070062510101254196402346791325932728474121793828359418776382694637908487
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3827676059 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3827676059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * has 4 failures:
Test i2c_csr_aliasing has 1 failures.
2.i2c_csr_aliasing.65510691335244659077921218570764685156520110305082751832814574502918464753426
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_aliasing/latest/run.log
UVM_ERROR @ 98723680 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 98723680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 2 failures.
4.i2c_tl_intg_err.111644489127309074840629712256118085560930026797739294838223988360198602457625
Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 82462453 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 82462453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_tl_intg_err.93948619335774338239894010786065124520324851770926114008021070334220497086806
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 5669260 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 5669260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_csr_rw has 1 failures.
7.i2c_csr_rw.89972751074625242209583218104900047791804065501928491785483500415643391116239
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_csr_rw/latest/run.log
UVM_ERROR @ 4128792 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 4128792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
15.i2c_target_stress_all.47426522785307687527057639001296715980573331386415768124824953429830352932704
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 19817760199 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (27 [0x1b] vs 26 [0x1a])
UVM_INFO @ 19817760199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all.14129697843161075737691070091193621002762175161847401690029953073624113300763
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4875990458 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (19 [0x13] vs 16 [0x10])
UVM_INFO @ 4875990458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
32.i2c_target_stress_all_with_rand_reset.92550902452797690885451070405831561798015891906818700279955967881473830833610
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6285689812 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 3 [0x3])
UVM_INFO @ 6285689812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
1.i2c_target_stress_all_with_rand_reset.35868450586516962738996669388313081862446460544984152108584632508303882721537
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2043094694 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2043094694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.19952048980911471421050903663101534624627870803263211061481056189393527982763
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 78870457 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 78870457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * Wrote i2c_reg_block.acq_fifo_next_data[*]: * has 3 failures:
1.i2c_csr_bit_bash.103958107172111920098655185949420093084771586164469427796202316351965773271964
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
UVM_ERROR @ 619835989 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
UVM_INFO @ 619835989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_csr_bit_bash.102845388730164639931187220375190512676634016576408414946440404709248216588218
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
UVM_ERROR @ 143025976 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
UVM_INFO @ 143025976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 3 failures:
Test i2c_target_stress_all has 2 failures.
3.i2c_target_stress_all.103950953471430394712709830467568463155107158002386602771421095961472352926715
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 43033966581 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 43033966581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_stress_all.75010140034351978648398854408768871393320377430389078011845946487682346622695
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 15185863479 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 15185863479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
46.i2c_target_stress_all_with_rand_reset.96972926564031737998687895686425775432410980634959607801571098821102145506299
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25609015372 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 25609015372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
29.i2c_target_stress_all_with_rand_reset.107945530957404392600599546360450925937769784828221760872807702207350183887506
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10066265883 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xd411e194) == 0x0
UVM_INFO @ 10066265883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.i2c_target_stress_all_with_rand_reset.16019961095559366368129032198516312266590892804397384907217319121725097009176
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10473489533 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xbc834994) == 0x0
UVM_INFO @ 10473489533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
11.i2c_target_stress_all_with_rand_reset.13013892178042204735016054133775877785390364817982040259652968481877569325515
Line 478, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28196936769 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (205 [0xcd] vs 93 [0x5d])
UVM_INFO @ 28196936769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: * has 1 failures:
13.i2c_tl_intg_err.100263227531380674191791912968484635621505963951084803084005810445752214202749
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 17125278 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 17125278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_sync' has 1 failures:
17.i2c_same_csr_outstanding.99527720343652322299227871267985465386881407966773010903720854271047892557027
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_sync'
UVM_ERROR @ 31999683 ps: (i2c_core.sv:755) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 31999683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
24.i2c_host_perf.44322998568743939123616344105931252608059041161247197135603883591116155693031
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_perf/latest/run.log
UVM_ERROR @ 1110718556 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
UVM_INFO @ 1110718556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
25.i2c_target_stress_all_with_rand_reset.73643962130467910116517527338746259313357852144986839003312638380701562297323
Line 364, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7351680309 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (50 [0x32] vs 217 [0xd9])
UVM_INFO @ 7351680309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
34.i2c_host_stress_all_with_rand_reset.58631740064409200445332097039002295740851433558587403993552426666788059468737
Line 2339, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3243172297 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (8 [0x8] vs 3 [0x3])
UVM_INFO @ 3243172297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---