ecd9f08747| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.599m | 7.380ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.670s | 1.179ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 28.537us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.840s | 25.753us | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 2.870s | 1.888ms | 0 | 5 | 0.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.080s | 109.644us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.660s | 299.260us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.840s | 25.753us | 18 | 20 | 90.00 |
| i2c_csr_aliasing | 2.080s | 109.644us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 148 | 155 | 95.48 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.070s | 386.231us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 50.216m | 18.064ms | 44 | 50 | 88.00 |
| V2 | host_maxperf | i2c_host_perf | 40.548m | 24.573ms | 46 | 50 | 92.00 |
| V2 | host_override | i2c_host_override | 0.730s | 30.706us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.518m | 16.068ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.597m | 8.240ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.170s | 589.774us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 22.970s | 461.625us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.680s | 1.489ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.064m | 10.798ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 35.210s | 743.846us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.854m | 4.277ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 7.470s | 17.986ms | 6 | 50 | 12.00 |
| V2 | target_glitch | i2c_target_glitch | 10.040s | 2.194ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 17.587m | 32.917ms | 4 | 50 | 8.00 |
| V2 | target_maxperf | i2c_target_perf | 1.130s | 227.140us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.398m | 18.216ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.340s | 3.442ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.341m | 10.066ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.724m | 10.068ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 34.572m | 65.028ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.398m | 18.216ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.671m | 22.688ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.080s | 3.464ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 49.811m | 20.284ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.800s | 5.078ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.450s | 2.551ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 5.518m | 16.068ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.690s | 20.711us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 19.949us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.700s | 177.904us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.700s | 177.904us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 28.537us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 25.753us | 18 | 20 | 90.00 | ||
| i2c_csr_aliasing | 2.080s | 109.644us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 70.985us | 12 | 20 | 60.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 28.537us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 25.753us | 18 | 20 | 90.00 | ||
| i2c_csr_aliasing | 2.080s | 109.644us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 70.985us | 12 | 20 | 60.00 | ||
| V2 | TOTAL | 1227 | 1392 | 88.15 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.360s | 543.338us | 13 | 20 | 65.00 |
| i2c_sec_cm | 0.980s | 62.895us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.360s | 543.338us | 13 | 20 | 65.00 |
| V2S | TOTAL | 18 | 25 | 72.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.558m | 17.099ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 14.344m | 44.047ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 29.120s | 8.640ms | 50 | 50 | 100.00 | |
| TOTAL | 1443 | 1722 | 83.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 36 | 30 | 23 | 63.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.76 | 97.32 | 92.08 | 97.66 | 83.74 | 94.83 | 98.67 | 92.02 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 90 failures:
0.i2c_target_perf.15858827832371728628896805927408336338084601133058111386673010595433298324824
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 42616643 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 42616643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.74031939950523143696634679063425272196067040367623936962319796705223110680019
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 138262976 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 138262976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
1.i2c_target_stress_all.13998758400174294465946713682757672997010401762243546362571056181335302284645
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 30962646 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 30962646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.103517621402811134054760090436165475998426716050135865685896598775711256227665
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 19284836 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 19284836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
1.i2c_target_stress_all_with_rand_reset.81266013578006014543140760364962081080454493533155364323232246082845574475739
Line 337, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7988367715 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 7988367715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.110368886030256478304744676712310946940311212426652692597266413826711640037927
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 284828429 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 284828429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 68 failures:
0.i2c_target_unexp_stop.64107969524220910532775914490822685778942742779899416096794177162373300010120
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 977208159 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 977208159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.3697781403690851818209566763365139908545350071905694843708635588613386164420
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1262134425 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1262134425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 41 more failures.
0.i2c_target_stress_all.32846022319768364867717918248741585159960626756444914777844597838180768607590
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4587607464 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4587607464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.50549316756034644492856916292452617763120641377963934940302290591862556977957
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 34656059524 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 34656059524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.i2c_host_stress_all_with_rand_reset.88697593488839842537268799703751220546813064639451564229675918115034329475046
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3880307878 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3880307878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.32513739997875938499896106414372116499241948704756367297206190869561536404633
Line 3953, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 46152469695 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 46152469695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
3.i2c_target_stress_all_with_rand_reset.34431845722685059997774296776811836082039053847657333596576834630889147047349
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 281493010 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 281493010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.56402284144110300341576167525401892434508470673738093884491560650191596480036
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 107248546 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107248546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
Test i2c_host_stress_all has 5 failures.
0.i2c_host_stress_all.88154798036266956037043469174611363934700860883470553104762946871934085026780
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:a912c509-c255-4c97-b569-b76591a40e79
2.i2c_host_stress_all.13642216311030334466219134206056818282747906976900479337604490153115229902907
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:d4588ed9-f3ec-4d84-894e-09f506aef3b1
... and 3 more failures.
Test i2c_target_stretch has 7 failures.
2.i2c_target_stretch.45052551181155651897937445063463808062657743633521547537903307254068279186629
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:cd4644c9-9713-4987-af4a-a3b6262dc4c3
24.i2c_target_stretch.92291033816870146447577059082663257896818736726133942065408073658379294199509
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stretch/latest/run.log
Job ID: smart:2d253d07-e322-4111-9e2d-4b1aba4fa494
... and 5 more failures.
Test i2c_host_stress_all_with_rand_reset has 7 failures.
3.i2c_host_stress_all_with_rand_reset.6351347053534455297360165172493644861045751406899212748685749334283728934981
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:31aaae3b-629e-4da2-9487-349a6a8101c1
6.i2c_host_stress_all_with_rand_reset.12953088809660054949729899667835509882870739111559219131162892025807197101943
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d0f43dd1-1fbb-4eed-905b-f06e9254d56f
... and 5 more failures.
Test i2c_host_perf has 1 failures.
5.i2c_host_perf.73405758884056847702199583359482096145613471989169571946391970504034063520799
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
Job ID: smart:317b348a-3c33-47b7-aaf4-5a07b9f51563
Test i2c_target_stress_all_with_rand_reset has 1 failures.
24.i2c_target_stress_all_with_rand_reset.79531822668791996091109893134751641008512041011206252705369505335992302023039
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:dece1ee5-6dc7-426e-a6df-9f3b273c41ef
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 8 failures:
1.i2c_same_csr_outstanding.111416242240679061272230733551203978797199168233820822882685869206450441194950
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 75081861 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (4 [0x4] vs 0 [0x0]) addr 0xb236f870 read out mismatch
UVM_INFO @ 75081861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_same_csr_outstanding.111735142332285348222636312525656831538476876699207404537835802850655886622045
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 11795615 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xa70410f0 read out mismatch
UVM_INFO @ 11795615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
7.i2c_target_stress_all_with_rand_reset.61825816839523713713001324185046858421186654328997125647188302534608592288143
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 807849403 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 807849403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.99003229804703369591294691087263488375458552624944566586486024209768488627489
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2845916400 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2845916400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * Wrote i2c_reg_block.acq_fifo_next_data[*]: * has 5 failures:
0.i2c_csr_bit_bash.14407386246950248628645727681737177486052607250670606151610869453602926571540
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
UVM_ERROR @ 32704826 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
UVM_INFO @ 32704826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_csr_bit_bash.21802584788131052103534312230057177676167186662248903066525529222155021585370
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
UVM_ERROR @ 100534375 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
UVM_INFO @ 100534375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 5 failures:
11.i2c_target_stress_all_with_rand_reset.26226535393205647391021427070073144264113121574013062213920258387705152630372
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6812787587 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6812787587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.409583793602675223353149644423498966705463639152870207042931851529537175566
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 629844928 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 629844928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
22.i2c_target_perf.74368342672694100249930164960982542042700482219915244617967227249159137458236
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_perf/latest/run.log
UVM_ERROR @ 34742426 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 34742426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: * has 5 failures:
11.i2c_tl_intg_err.74938333459052671666724471149707471396576606450170444915444414936166579777310
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 113831145 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 113831145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_tl_intg_err.96571279923810588285627511895897803069502399768892796785365418098943727783564
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 2772894 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 2772894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
17.i2c_csr_rw.70597605356944637196350349599097062386235544615072968625612854833603378192252
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_csr_rw/latest/run.log
UVM_ERROR @ 14273657 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 14273657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * has 4 failures:
7.i2c_tl_intg_err.86556969119225693559988219457906228367938676585677916678760057035537472904083
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 57273409 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 57273409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_tl_intg_err.41585631755872254832369213347124454380858182684940588262236445439518992738068
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 61975184 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 61975184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
18.i2c_csr_rw.78853109703445970844447818022897482659949561159198376947278953449432655595605
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_csr_rw/latest/run.log
UVM_ERROR @ 53023955 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
UVM_INFO @ 53023955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
Test i2c_target_stress_all has 2 failures.
10.i2c_target_stress_all.101477420692997875921828145607743168402653241920563084217938451930752578721481
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3422613768 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (14 [0xe] vs 10 [0xa])
UVM_INFO @ 3422613768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_stress_all.74786000105410935891187120610743970906999461385009752711947627948553133063280
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1346294569 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 6 [0x6])
UVM_INFO @ 1346294569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 2 failures.
29.i2c_target_stress_all_with_rand_reset.91202237849660538779520435844838558583343605344971380969688910831890542599757
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2399892095 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 15 [0xf])
UVM_INFO @ 2399892095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_stress_all_with_rand_reset.109150327948537379483798881840230989546503623200038651704914947200229932079630
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6367454373 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 2 [0x2])
UVM_INFO @ 6367454373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
9.i2c_target_stress_all_with_rand_reset.47950892887405651295769393275295474279412736279855526381704192927891697107935
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12404189786 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf6ed3a14) == 0x0
UVM_INFO @ 12404189786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all_with_rand_reset.70940236447477122246507306440799997373868016683897267021965249506967903730589
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14672184159 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x53baa794) == 0x0
UVM_INFO @ 14672184159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 3 failures:
11.i2c_host_perf.87512852230375457820075194030055117091495086483611836338911054026899917574664
Line 344, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_perf/latest/run.log
UVM_ERROR @ 5378914803 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
UVM_INFO @ 5378914803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_perf.36299706732458412374312838737427410525584673525555400006091610478587415938877
Line 1316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf/latest/run.log
UVM_ERROR @ 7007800369 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
UVM_INFO @ 7007800369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 2 failures:
Test i2c_host_stress_all has 1 failures.
5.i2c_host_stress_all.81247170564466458376415207387842629080327682623747276065741672151441914577049
Line 433, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9411977401 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all_with_rand_reset has 1 failures.
20.i2c_host_stress_all_with_rand_reset.55278824104115158029185932570395041365949938241760763122224141975558066890309
Line 1006, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30582886247 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 2 failures:
Test i2c_target_unexp_stop has 1 failures.
9.i2c_target_unexp_stop.91888965096941953804647730909053756685223549906474696423116635826999777493509
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 19379014467 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 19379014467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
12.i2c_target_stress_all_with_rand_reset.43700309477575937929649873646152513602761516823775545623605781343011704292298
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11532755840 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11532755840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
25.i2c_host_stress_all_with_rand_reset.39688957582037577704514595196492390597380730737140383581082944881048716562550
Line 5036, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4480617223 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (12 [0xc] vs 3 [0x3])
UVM_INFO @ 4480617223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_host_stress_all_with_rand_reset.81430706430052034364797205354356776754909625110360969055016938578257791631480
Line 2207, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23007716685 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 23007716685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
0.i2c_target_stress_all_with_rand_reset.14495224476954100539555880487789499715223744210839157948208930836625744832343
Line 362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31589570978 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (234 [0xea] vs 12 [0xc])
UVM_INFO @ 31589570978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---