d0c52cdadd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.713m | 3.714ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.014m | 1.588ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 51.085us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 19.010us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.160s | 140.750us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.050s | 121.461us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.440s | 29.683us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 19.010us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.050s | 121.461us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.090s | 475.144us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 47.562m | 74.954ms | 40 | 50 | 80.00 |
| V2 | host_maxperf | i2c_host_perf | 46.101m | 72.278ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.780s | 31.584us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.065m | 4.452ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.670m | 2.218ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.220s | 165.827us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.570s | 1.823ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.430s | 773.205us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.357m | 16.509ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 34.320s | 4.692ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.561m | 4.097ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 7.080s | 5.777ms | 11 | 50 | 22.00 |
| V2 | target_glitch | i2c_target_glitch | 10.570s | 29.568ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 56.040m | 62.702ms | 2 | 50 | 4.00 |
| V2 | target_maxperf | i2c_target_perf | 1.080s | 83.007us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.139m | 1.699ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.240s | 6.287ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.458m | 10.081ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.545m | 10.066ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 33.347m | 61.122ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.139m | 1.699ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.056m | 26.056ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.760s | 2.748ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 51.648m | 33.379ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.830s | 3.880ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.240s | 530.404us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 6.065m | 4.452ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.660s | 28.331us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.720s | 31.958us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.730s | 113.288us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.730s | 113.288us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 51.085us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 19.010us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.050s | 121.461us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 67.541us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 51.085us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 19.010us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.050s | 121.461us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 67.541us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1242 | 1392 | 89.22 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.510s | 551.760us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.920s | 120.558us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.510s | 551.760us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.608m | 9.307ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.711m | 23.343ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 26.910s | 2.842ms | 50 | 50 | 100.00 | |
| TOTAL | 1472 | 1722 | 85.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 36 | 30 | 24 | 66.67 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.46 | 97.12 | 91.21 | 97.66 | 83.58 | 94.37 | 98.67 | 91.60 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 91 failures:
0.i2c_target_perf.21105120160859033100867742364099979512205535568015177342978971658375431514651
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 45517661 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 45517661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.3895126067483522751033613046476382198647300307334503260098773597940187961308
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 66037031 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 66037031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all.41562238056951023556241352549887374698618926643250261129823166606385918781757
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 26921829 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 26921829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.44231694197716059037063455397742827562004898738002790041556854600267538446031
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 19662999197 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 19662999197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
2.i2c_target_stress_all_with_rand_reset.18129360468488592448550645786666936827080364903828036259399477883201200933447
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27226800794 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 27226800794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.44795074421082854862767530913087069435758715617679206717104354773051886835214
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43624872 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 43624872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 63 failures:
0.i2c_host_stress_all_with_rand_reset.34622893933577721312818200016804195990057304770002822272818321309947167537135
Line 984, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8861129367 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8861129367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.57369339511473828844729883256747688168803724022998614797723207661825983657460
Line 5481, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50014102816 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 50014102816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 43 more failures.
0.i2c_target_stress_all_with_rand_reset.51578256156935729456566215240148547890201210292065469349916291942702609815324
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5381324697 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5381324697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.97588761365511582297766547981255345551518494173068839722174904114684702675536
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1430568109 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1430568109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 63 failures:
1.i2c_target_unexp_stop.90166782198364504554368173810170289926044217898294778081564511550164056526466
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3389583679 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3389583679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.19182215898056038949584403352302228400063157384200819877574432191934480316556
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2957309841 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2957309841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
1.i2c_target_stress_all.73705667959215136863279408013264897355478974304402816553829109958924662629449
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2889600567 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2889600567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.13168799814964770300807109338872153698669956916553166809916670104081989842848
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2430816734 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2430816734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
5.i2c_host_stress_all_with_rand_reset.44176427867821481758962028459331736266908703887346202653214715652584241708072
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ee6f7139-5e41-45c3-967c-0d82b5082961
31.i2c_host_stress_all_with_rand_reset.72034704836331173924828874954516377497480593595960756853177230223632091342394
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:22ca95a3-391f-4ae1-80df-229de205c3c4
... and 2 more failures.
8.i2c_host_stress_all.71262639470381011729163067073780139560510635296650063269107495352299382863077
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job ID: smart:123df4b4-5168-4207-86e5-d09a0e101321
26.i2c_host_stress_all.2127444266121173540799833547328710450943887164471285024968622379083202202317
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
Job ID: smart:8fa3871d-9b1f-4005-844b-2eae22ec9ed6
... and 7 more failures.
24.i2c_target_stretch.53664883631641845557570151423892048400274656011541301354921966838546629902691
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stretch/latest/run.log
Job ID: smart:017ffd92-3854-4437-bc7d-2156e3a8e127
45.i2c_target_stretch.22406567922665178350533635086889615172701518134215588692974989722740022196889
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stretch/latest/run.log
Job ID: smart:33de36e6-7684-4aef-8545-15ca518a98ce
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 3 failures.
8.i2c_target_stress_all_with_rand_reset.30575664885573672943514704511058643173366984562593444501821864916571338492585
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 16098140823 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 16098140823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_stress_all_with_rand_reset.21844831650469222141087889363559254356462143345543934345681200558757831526965
Line 352, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 45323336366 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 45323336366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_target_stress_all has 1 failures.
33.i2c_target_stress_all.7707217811916163028224361952365707604753727047405523697615070449367323709415
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 56784590690 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 56784590690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
41.i2c_target_unexp_stop.35298963153810886857082937604712628373853076391396337134477961314693618028826
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 12119761956 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12119761956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
5.i2c_target_stress_all_with_rand_reset.90037589593458791377077277940055040931274638092303818603603557937638961821921
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1861252707 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1861252707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stress_all_with_rand_reset.69536602052360660216587945471601165944553691001164730348090393267705717855745
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 5650657604 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 5650657604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
15.i2c_target_stress_all_with_rand_reset.10131903033350320630947360544832745903564635771869877368589150353865877586037
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10020779290 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x5a2c2694) == 0x0
UVM_INFO @ 10020779290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all_with_rand_reset.19881810347185918693075841049856236598994039111882363946802823402374957202194
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 15352513060 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x34db0d14) == 0x0
UVM_INFO @ 15352513060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
3.i2c_target_stress_all_with_rand_reset.62072669663585179406637283183465637238260158623146298133652790546398476270935
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3493145858 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 3 [0x3])
UVM_INFO @ 3493145858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
44.i2c_target_stress_all.114682746370598262194221169730363986958235060265612373277922368692335244128391
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7979099661 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (35 [0x23] vs 32 [0x20])
UVM_INFO @ 7979099661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
37.i2c_target_stress_all_with_rand_reset.14490478889294549070172703557301435630298576358945524566448717590016250969316
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14917446 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14917446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
45.i2c_target_stress_all.80174266518924834184579699425338595437364633274786382164808606341353595970091
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 170197971 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170197971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
13.i2c_host_stress_all.81853364440959714188008611716331134891138534493859819252005396130621452206042
Line 368, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8026277930 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
UVM_INFO @ 8026277930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_sync' has 1 failures:
18.i2c_same_csr_outstanding.32402356214445498951801228875653840745529950881591752880994877417572321888823
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_sync'
UVM_ERROR @ 10821756 ps: (i2c_core.sv:793) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 10821756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
20.i2c_host_stress_all_with_rand_reset.19443640152675670565724048611219964483755372780045574159956937277551330886048
Line 1440, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4170745380 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (5 [0x5] vs 20 [0x14])
UVM_INFO @ 4170745380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---