Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	826556	0	0	0
ctrl_rd_A	826556	1600	0	0
host_fifo_config_rd_A	826556	1188	0	0
host_nack_handler_timeout_rd_A	826556	975	0	0
host_timeout_ctrl_rd_A	826556	958	0	0
intr_enable_rd_A	826556	2764	0	0
ovrd_rd_A	826556	1112	0	0
target_fifo_config_rd_A	826556	1069	0	0
target_id_rd_A	826556	1292	0	0
target_timeout_ctrl_rd_A	826556	1036	0	0
timeout_ctrl_rd_A	826556	1199	0	0
timing0_rd_A	826556	979	0	0
timing1_rd_A	826556	1161	0	0
timing2_rd_A	826556	1131	0	0
timing3_rd_A	826556	950	0	0
timing4_rd_A	826556	920	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1600	0	0
T3	10313	1	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	67	0	0
T9	3663	56	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	3	0	0
T16	0	6	0	0
T21	0	27	0	0
T23	0	3	0	0
T25	0	52	0	0
T44	0	39	0	0
T45	0	17	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1188	0	0
T3	10313	9	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	7	0	0
T9	3663	33	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	8	0	0
T16	0	1	0	0
T21	0	14	0	0
T23	0	4	0	0
T25	0	75	0	0
T44	0	16	0	0
T45	0	46	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	975	0	0
T3	10313	9	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	12	0	0
T9	3663	13	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	21	0	0
T21	0	14	0	0
T23	0	3	0	0
T25	0	25	0	0
T44	0	7	0	0
T45	0	32	0	0
T46	0	10	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	958	0	0
T3	10313	17	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	5	0	0
T9	3663	20	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	12	0	0
T16	0	7	0	0
T21	0	9	0	0
T23	0	8	0	0
T25	0	39	0	0
T44	0	20	0	0
T45	0	57	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	2764	0	0
T3	10313	24	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	46	0	0
T9	3663	16	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	23	0	0
T16	0	16	0	0
T21	0	3	0	0
T23	0	4	0	0
T44	0	89	0	0
T47	0	15	0	0
T48	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1112	0	0
T3	10313	8	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	19	0	0
T9	3663	40	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	5	0	0
T16	0	14	0	0
T21	0	22	0	0
T23	0	8	0	0
T25	0	48	0	0
T44	0	42	0	0
T45	0	50	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1069	0	0
T3	10313	24	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	12	0	0
T9	3663	10	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	16	0	0
T16	0	6	0	0
T21	0	9	0	0
T23	0	3	0	0
T25	0	24	0	0
T44	0	24	0	0
T45	0	9	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1292	0	0
T3	10313	23	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	13	0	0
T9	3663	36	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	8	0	0
T21	0	18	0	0
T25	0	49	0	0
T44	0	36	0	0
T45	0	24	0	0
T46	0	12	0	0
T49	0	31	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1036	0	0
T3	10313	2	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	9	0	0
T9	3663	62	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	8	0	0
T16	0	3	0	0
T21	0	10	0	0
T23	0	6	0	0
T25	0	79	0	0
T44	0	24	0	0
T45	0	19	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1199	0	0
T3	10313	27	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	16	0	0
T9	3663	52	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	3	0	0
T16	0	4	0	0
T21	0	4	0	0
T23	0	4	0	0
T25	0	35	0	0
T44	0	41	0	0
T45	0	37	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	979	0	0
T3	10313	3	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	9	0	0
T9	3663	26	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	18	0	0
T16	0	3	0	0
T21	0	8	0	0
T23	0	3	0	0
T25	0	66	0	0
T44	0	15	0	0
T45	0	27	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1161	0	0
T3	10313	19	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	9	0	0
T9	3663	43	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	0	0	0
T16	0	8	0	0
T21	0	16	0	0
T23	0	2	0	0
T25	0	71	0	0
T44	0	24	0	0
T45	0	19	0	0
T46	0	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	1131	0	0
T3	10313	4	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	14	0	0
T9	3663	27	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	16	0	0
T16	0	6	0	0
T21	0	10	0	0
T23	0	6	0	0
T25	0	32	0	0
T44	0	29	0	0
T45	0	26	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	950	0	0
T3	10313	5	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	10	0	0
T9	3663	28	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	12	0	0
T16	0	4	0	0
T21	0	9	0	0
T23	0	3	0	0
T25	0	34	0	0
T44	0	22	0	0
T45	0	21	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826556	920	0	0
T3	10313	31	0	0
T4	11062	0	0	0
T5	2679	0	0	0
T6	4416	0	0	0
T7	3236	0	0	0
T8	1795	11	0	0
T9	3663	30	0	0
T10	943	0	0	0
T12	945	0	0	0
T14	6474	7	0	0
T16	0	12	0	0
T21	0	16	0	0
T23	0	2	0	0
T25	0	39	0	0
T44	0	17	0	0
T45	0	16	0	0