Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
31.30	0.00	0.00	93.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	31.30	0.00	0.00	93.91

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
31.30	0.00	0.00	93.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.46	40.66	40.72	90.72	0.00	42.98	99.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	0.00	0.00	0.00		0.00	0.00
i2c_csr_assert	93.75						93.75
tlul_assert_device	33.33	0.00				0.00	100.00
u_reg	95.88	98.37	95.92	87.50		97.58	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	133	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
132	0	1
133	0	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	51	45	88.24
Total Bits	394	370	93.91
Total Bits 0->1	197	185	93.91
Total Bits 1->0	197	185	93.91

Ports	51	45	88.24
Port Bits	394	370	93.91
Port Bits 0->1	197	185	93.91
Port Bits 1->0	197	185	93.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T8,T5	Yes	T4,T8,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T8,T5	Yes	T4,T8,T5	OUTPUT
cio_scl_i	Yes	Yes	T4,T8,T5	Yes	T4,T5,T6	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T4,T5,T6	Yes	T4,T8,T5	OUTPUT
cio_sda_i	Yes	Yes	T4,T5,T9	Yes	T4,T5,T9	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T4,T5,T9	Yes	T4,T5,T9	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T4,T8,T6	Yes	T4,T8,T6	OUTPUT
intr_rx_threshold_o	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	OUTPUT
intr_acq_threshold_o	Yes	Yes	T12,T10,T13	Yes	T12,T10,T13	OUTPUT
intr_rx_overflow_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_controller_halt_o	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	OUTPUT
intr_scl_interference_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	OUTPUT
intr_sda_unstable_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_cmd_complete_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_tx_stretch_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT
intr_tx_threshold_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
intr_acq_stretch_o	Yes	Yes	T1,T10,T13	Yes	T1,T10,T13	OUTPUT
intr_unexp_stop_o	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	OUTPUT
intr_host_timeout_o	Yes	Yes	T1,T12,T10	Yes	T1,T12,T10	OUTPUT

*Tests covering at least one bit in the range