I2C Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.888m	2.097ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	1.002m	5.979ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	28.526us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.840s	26.215us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.310s	912.789us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.920s	94.002us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.650s	35.403us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.840s	26.215us	20	20	100.00
		i2c_csr_aliasing	1.920s	94.002us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	15.480s	5.264ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	51.833m	80.791ms	44	50	88.00
V2	host_maxperf	i2c_host_perf	42.805m	48.575ms	48	50	96.00
V2	host_override	i2c_host_override	0.760s	18.772us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.963m	5.280ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.523m	10.757ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.350s	156.782us	50	50	100.00
		i2c_host_fifo_fmt_empty	31.320s	2.282ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.920s	295.404us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.532m	11.382ms	49	50	98.00
V2	host_timeout	i2c_host_stretch_timeout	47.910s	5.978ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.943m	10.790ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	57.878m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	12.360s	2.460ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	50.773m	105.872ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	32.191m	20.000ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.300m	1.914ms	50	50	100.00
		i2c_target_intr_smoke	8.390s	1.676ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.650s	263.671us	50	50	100.00
		i2c_target_fifo_reset_tx	1.620s	1.347ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	48.684m	74.018ms	50	50	100.00
		i2c_target_stress_rd	1.300m	1.914ms	50	50	100.00
		i2c_target_intr_stress_wr	10.762m	25.936ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.550s	9.547ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.864m	5.058ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	6.070s	4.469ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	49.430s	10.267ms	28	50	56.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.600s	721.150us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.450s	176.289us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	42.805m	48.575ms	48	50	96.00
		i2c_host_perf_precise	15.694m	23.203ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	47.910s	5.978ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	11.320s	917.650us	50	50	100.00
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	alert_test	i2c_alert_test	0.720s	17.954us	50	50	100.00
V2	intr_test	i2c_intr_test	0.740s	32.105us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	115.299us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	115.299us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	28.526us	5	5	100.00
		i2c_csr_rw	0.840s	26.215us	20	20	100.00
		i2c_csr_aliasing	1.920s	94.002us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	198.066us	18	20	90.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	28.526us	5	5	100.00
		i2c_csr_rw	0.840s	26.215us	20	20	100.00
		i2c_csr_aliasing	1.920s	94.002us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	198.066us	18	20	90.00
V2		TOTAL			1402	1592	88.07
V2S	tl_intg_err	i2c_tl_intg_err	2.460s	152.771us	20	20	100.00
		i2c_sec_cm	1.020s	65.529us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.460s	152.771us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.535m	59.428ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.944m	17.206ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	27.500s	2.915ms	50	50	100.00
		TOTAL			1632	1842	88.60

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	47	34	25	53.19
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.71	96.51	89.73	97.22	69.05	93.48	98.44	90.53

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:609) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 58 failures:

Test i2c_target_stress_all has 27 failures.

0.i2c_target_stress_all.108003373456354477141017143310860916918782615916823891153197650773302877908750
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 157657277 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 8 [0x8])
  UVM_INFO @ 157657277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all.84432150392734441909084338038345574875685279974197680318879030948116058836244
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 3811386287 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 6 [0x6])
  UVM_INFO @ 3811386287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test i2c_target_unexp_stop has 24 failures.

2.i2c_target_unexp_stop.18084266358031745186566278741727034386127357473097852900291648529814200795836
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  79699249 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
  UVM_INFO @  79699249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.106728238617216985468428829145802793753664959653230981887955004180968550489695
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 149702760 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 149702760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test i2c_target_hrst has 7 failures.

6.i2c_target_hrst.32978011201329829855517475368902404813982997794515326346450170079657670957216
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 157749582 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (12 [0xc] vs 7 [0x7])
  UVM_INFO @ 157749582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_target_hrst.33532928542567294507655615497465099974396447728859700806823654886806039153359
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 441573744 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 8 [0x8])
  UVM_INFO @ 441573744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred! has 45 failures:
- Test i2c_target_perf has 37 failures.
  - 1.i2c_target_perf.57060872706362330901922130574997057491360339817795935789276945442397769247546
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 12465592719 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 12465592719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_perf.83532544201293919731478033062496450081332810231078553755682279976091945229753
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 12396839029 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 12396839029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
- Test i2c_target_stress_all has 8 failures.
  - 11.i2c_target_stress_all.50023595260109881043695391931300554061047262864518414101062134399544730543541
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 11971917264 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11971917264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all.58537590966252097264970857605408692763568708763446256565969714255424510800762
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 15422876567 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 15422876567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 20 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 0.i2c_target_unexp_stop.29952799862463239625521755409654118800545702635584408804206490137331157655690
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.26164960862219738169154432918875471528197784036807269167724029242307558410203
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
- Test i2c_target_perf has 4 failures.
  - 0.i2c_target_perf.31913009596385095312900962202351672796850986040503488222073751364525480086717
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.i2c_target_perf.97928804973692612450919758506851913388749174471779198604551419876822108240539
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.17221679202934195764652878569200905763791282555046562293566781506136551234738
Line 4231, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8259746579 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8259746579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.25052743973526462935777990659260167214332695474943836311637832303804744936829
Line 3643, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7631068118 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7631068118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.56161572750525155057192233716699239378837080888450503865200820315093158491526
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 899382331 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 899382331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.105871649700908754313161915647870867423719027477277088818341613089267546655308
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 856690124 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 856690124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:613) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 16 failures:

Test i2c_target_stress_all_with_rand_reset has 2 failures.
- 1.i2c_target_stress_all_with_rand_reset.60817143934528543522077558031641882070649058750507344805004392931495611891839
  Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 148174695 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
  UVM_INFO @ 148174695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 4.i2c_target_stress_all_with_rand_reset.94935552955658089633524970039753426229858462981411127623161928778090661649441
  Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 351030440 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 117 [0x75])
  UVM_INFO @ 351030440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_target_perf has 9 failures.

7.i2c_target_perf.2165386220692710816110056930222716070070944030872205685232095358712012292105
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log

  UVM_ERROR @ 103549408 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 112 [0x70])
  UVM_INFO @ 103549408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_perf.81141979771112683709218420650554687172314383775186251358902730503748084512450
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log

  UVM_ERROR @ 335486481 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 100 [0x64])
  UVM_INFO @ 335486481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all has 4 failures.

8.i2c_target_stress_all.47702188956883332514202615658942786685173239561458904058908104496215372218544
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 232874994 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 78 [0x4e])
  UVM_INFO @ 232874994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_target_stress_all.71490106422571588148959602978676654700331611538061935530359741268821895967579
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  85566948 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 77 [0x4d])
  UVM_INFO @  85566948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_target_hrst has 1 failures.

22.i2c_target_hrst.108212507419743017768270713847462507634450428231825940871400660754463640903183
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 165800017 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (229 [0xe5] vs 65 [0x41])
  UVM_INFO @ 165800017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_host_stress_all_with_rand_reset.80883419811546381728366837723905574564396042445941895595774648308028840746449
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7b0e4ed1-6e90-4a74-abe1-b83b6f635de1
```
- Test i2c_target_stress_all has 3 failures.
  - 2.i2c_target_stress_all.7661688967522084577341591221077285937692037782418963030009952757785710183213
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:ce07438c-79b0-4cdf-9133-981017bce3c3
```
  - 24.i2c_target_stress_all.84820801018660393497290094575062944588032478950844452581424460532979065681926
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:185afa55-d37b-41e5-91a5-9fd1771b2e24
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 6 failures.
  - 6.i2c_target_unexp_stop.5905007688406517995589688098678243614396348113293047758908778078088086975861
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:ee928b14-cce0-4bab-b2dc-5b408cf54fee
```
  - 9.i2c_target_unexp_stop.13020023091238102062348197949547864742333367727067089367721822060395215104892
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:cb4a46d8-60bf-4a19-9d7f-27d7d3a5c14f
```
  - ... and 4 more failures.
- Test i2c_host_perf has 2 failures.
  - 16.i2c_host_perf.84382632639838944751568477523213883103357809935778309910491790616843129390766
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
```
  Job ID: smart:09cf659c-e3b2-4f21-b446-ec92d204bf0d
```
  - 42.i2c_host_perf.98103667853888666025798705332002923020433663879932595350137865022533475993185
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf/latest/run.log
```
  Job ID: smart:3d482e0e-f23a-4c02-a8a9-db898b3e6eb5
```
- Test i2c_host_stress_all has 2 failures.
  - 26.i2c_host_stress_all.35028017114059253681900965461694917398783533839700647103830727902661881329433
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:d5ec60d4-b09f-4ccf-b8c3-45ab0f1a17f5
```
  - 35.i2c_host_stress_all.113995104798599883687767247518863918761971599008005256119168817563779485900677
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:1990e3f3-124a-4ae6-aa36-5930795ba564
```
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 7 failures:
- Test i2c_target_hrst has 7 failures.
  - 2.i2c_target_hrst.25178569020126303857009847632707341150182468139871857180200580319327193423553
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @   5088144 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @   5088144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_hrst.45939107273546375110874351236333639404736917590416333240259807179539132771921
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  16884304 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  16884304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 7 failures:
- Test i2c_target_stress_all has 3 failures.
  - 3.i2c_target_stress_all.14727807019349476074725547338458181836731457781909746334334650780833403879018
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2375506038 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2375506038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.i2c_target_stress_all.109100419477245753957514711341290425730881961585977699595825242563603134935965
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 797891979 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 797891979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 4 failures.
  - 4.i2c_target_unexp_stop.26490841996337529663742024115750990535766152294190066130716041196705853497755
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 675341373 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 675341373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_target_unexp_stop.88692476050215328116236024524878623910516793163271978752311148545489061916620
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2969303405 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2969303405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred! has 7 failures:
- Test i2c_target_stretch has 7 failures.
  - 5.i2c_target_stretch.7291300542354494536367668247524866625108975532703042993876146374414405984608
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10009068911 ps: (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred!
  UVM_INFO @ 10009068911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stretch.26950407565346469678752769678539455077773355982252222682278211536499552291413
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10040603916 ps: (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred!
  UVM_INFO @ 10040603916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:590) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
- Test i2c_target_hrst has 6 failures.
  - 3.i2c_target_hrst.65306012089663244418400399395215075770097628903010651204904505727014072817389
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  22336722 ps: (i2c_scoreboard.sv:590) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (18 [0x12] vs 19 [0x13])
  UVM_INFO @  22336722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_hrst.23899886383523393871058751723284838713801131272550851277135746746403285703357
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  11672391 ps: (i2c_scoreboard.sv:590) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (210 [0xd2] vs 91 [0x5b])
  UVM_INFO @  11672391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred! has 5 failures:
- Test i2c_target_stress_all has 5 failures.
  - 19.i2c_target_stress_all.19895694979507797086920704356135964536343235554849917258169401655948263942978
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 102896619473 ps: (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 102896619473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.i2c_target_stress_all.46942522051085379232450474008076503570386757795185887311669969459672659016538
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 105871691019 ps: (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 105871691019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 4 failures:

Test i2c_host_stress_all has 4 failures.

4.i2c_host_stress_all.115407977010073030133107787313401512992871593249664348362401329894758004677544
Line 4086, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6865831762 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

12.i2c_host_stress_all.91209268302962857450804666532068044386792226579832187520951479380748805137297
Line 8162, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 29281740908 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test i2c_same_csr_outstanding has 2 failures.
  - 2.i2c_same_csr_outstanding.95658743038354312579990384628438098591739202411221882476653209245278927836587
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  93462638 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  93462638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.i2c_same_csr_outstanding.35989533730929871489099651084392754109195046793134137678292550319327704880090
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 379510711 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 379510711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 3.i2c_target_stress_all_with_rand_reset.7549324139404871652124551511060979388640606396067689143556276174609004680556
    Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17206020437 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xac405594) == 0x0
  UVM_INFO @ 17206020437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 33.i2c_target_hrst.6379602740244197345270442205796510635808423620773891359295291926216541838096
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10267013630 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10267013630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_fifo_full has 1 failures.
  - 36.i2c_host_fifo_full.67201659936731018084833923688941722395494500174088499169358954756082164892432
    Line 920, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_full/latest/run.log
```
  UVM_ERROR @ 339301423 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name              Type               Size  Value
  ----------------------------------------------------
```