eb56ef55d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 0 | 50 | 0.00 | ||
| V1 | target_smoke | i2c_target_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 31.406us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 30.324us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.530s | 521.903us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.250s | 157.200us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.350s | 29.690us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 30.324us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.250s | 157.200us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 54 | 155 | 34.84 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0 | 50 | 0.00 | ||
| V2 | host_stress_all | i2c_host_stress_all | 0 | 50 | 0.00 | ||
| V2 | host_maxperf | i2c_host_perf | 0 | 50 | 0.00 | ||
| V2 | host_override | i2c_host_override | 0 | 50 | 0.00 | ||
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 0 | 50 | 0.00 | ||
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 0 | 50 | 0.00 | ||
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0 | 50 | 0.00 | ||
| i2c_host_fifo_fmt_empty | 0 | 50 | 0.00 | ||||
| i2c_host_fifo_reset_rx | 0 | 50 | 0.00 | ||||
| V2 | host_fifo_full | i2c_host_fifo_full | 0 | 50 | 0.00 | ||
| V2 | host_timeout | i2c_host_stretch_timeout | 0 | 50 | 0.00 | ||
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 0 | 50 | 0.00 | ||
| V2 | target_error_intr | i2c_target_unexp_stop | 0 | 50 | 0.00 | ||
| V2 | target_glitch | i2c_target_glitch | 0 | 2 | 0.00 | ||
| V2 | target_stress_all | i2c_target_stress_all | 0 | 50 | 0.00 | ||
| V2 | target_maxperf | i2c_target_perf | 0 | 50 | 0.00 | ||
| V2 | target_fifo_empty | i2c_target_stress_rd | 0 | 50 | 0.00 | ||
| i2c_target_intr_smoke | 0 | 50 | 0.00 | ||||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0 | 50 | 0.00 | ||
| i2c_target_fifo_reset_tx | 0 | 50 | 0.00 | ||||
| V2 | target_fifo_full | i2c_target_stress_wr | 0 | 50 | 0.00 | ||
| i2c_target_stress_rd | 0 | 50 | 0.00 | ||||
| i2c_target_intr_stress_wr | 0 | 50 | 0.00 | ||||
| V2 | target_timeout | i2c_target_timeout | 0 | 50 | 0.00 | ||
| V2 | target_clock_stretch | i2c_target_stretch | 0 | 50 | 0.00 | ||
| V2 | bad_address | i2c_target_bad_addr | 0 | 50 | 0.00 | ||
| V2 | target_mode_glitch | i2c_target_hrst | 0 | 50 | 0.00 | ||
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 0 | 50 | 0.00 | ||
| i2c_target_fifo_watermarks_tx | 0 | 50 | 0.00 | ||||
| V2 | host_mode_config_perf | i2c_host_perf | 0 | 50 | 0.00 | ||
| i2c_host_perf_precise | 0 | 50 | 0.00 | ||||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 0 | 50 | 0.00 | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 0 | 50 | 0.00 | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | i2c_intr_test | 0.750s | 52.163us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.790s | 430.099us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.790s | 430.099us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 31.406us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 30.324us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.250s | 157.200us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 53.491us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 31.406us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 30.324us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.250s | 157.200us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 53.491us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 89 | 1592 | 5.59 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.690s | 623.798us | 17 | 20 | 85.00 |
| i2c_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.690s | 623.798us | 17 | 20 | 85.00 |
| V2S | TOTAL | 17 | 25 | 68.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 0 | 50 | 0.00 | |||
| TOTAL | 160 | 1842 | 8.69 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 47 | 34 | 2 | 4.26 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 52.68 | 40.66 | 40.72 | 90.72 | 0.00 | 42.98 | 99.68 | 54.00 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 839 failures:
0.i2c_host_smoke.9579822485876861980358149172343961858607545371631301725098765472039758871037
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_smoke/latest/run.log
2.i2c_host_smoke.61396217767636193376020381376491695620446504258069212701390386832161541911470
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_smoke/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_watermark.109869374653505894203551112527332414530721587910100115660096633527658786543857
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest/run.log
2.i2c_host_fifo_watermark.9406945335964446137620398778670796332448484289204198854594871175051379673999
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_reset_fmt.47197962245887009805243385208445805187754792963732654182197882309759751503442
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest/run.log
2.i2c_host_fifo_reset_fmt.15166660920984123365449010011411704094491884613107133598825167191816477503761
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_reset_rx.97828541715459787012735959705983890148840993132016484753118714915371498760109
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest/run.log
2.i2c_host_fifo_reset_rx.38199588624031719112941316286443928296950110889738211135144714696535918051919
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest/run.log
... and 25 more failures.
0.i2c_host_perf.105237970930563990588012293386430469712769016417705404549672982043226129160925
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf/latest/run.log
2.i2c_host_perf.6696583010740155624442282299935209347498425315882420832354905881954108028774
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
... and 25 more failures.
Job killed most likely because its dependent job failed. has 838 failures:
0.i2c_host_override.31179184862827906507042676133617371254701410496307232515790987659596424455760
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_override/latest/run.log
2.i2c_host_override.81786914505174772461599808725603595179182426110403415558961515120738340907536
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_override/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_overflow.16039510380753916839416430360114236497640366780972497365224607071105788031350
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log
2.i2c_host_fifo_overflow.36157380408826235278694063521165250111125226628973629648891611804554073504679
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_fmt_empty.21839580453840787553893133125401259671191877782040161752245328708382704943166
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest/run.log
2.i2c_host_fifo_fmt_empty.77679432790647320556161971536379197153676587252605703184942232741140731875798
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest/run.log
... and 25 more failures.
0.i2c_host_fifo_full.26924523461242101011225090422050162455805836720823719867413213673979394899892
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_full/latest/run.log
2.i2c_host_fifo_full.98783392841453495016752067131872808411159299982819886258171348121530670133118
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_full/latest/run.log
... and 25 more failures.
0.i2c_host_perf_precise.108241615861693367360215502881597926034313736208549613859825360329457272484995
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf_precise/latest/run.log
2.i2c_host_perf_precise.99685939758608695712255111515229774532706000295937633483824713413511896333430
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf_precise/latest/run.log
... and 25 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 2 failures:
5.i2c_tl_intg_err.49654765909044095332747053431161226969140614901186140507445905323609340893063
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 123529080 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 123529080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_tl_intg_err.55017924757423870308323988011659405754197425161235212916369652368640467058728
Line 330, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 225167413 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 225167413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
1.i2c_csr_bit_bash.40576146772348830561898819477499239761626832633615758197076606701451992828850
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 62986367 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 62986367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
9.i2c_same_csr_outstanding.3754641849920155953828392713061060252116183704783523731677346986421892467764
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 53490703 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x29b854f8 read out mismatch
UVM_INFO @ 53490703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
18.i2c_tl_intg_err.101987233874481313478317072577218148945725172623369439856624248081786555940098
Line 365, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 79523588 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 79523588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---