abd7ce57f2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.815m | 8.048ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 56.710s | 1.520ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 15.787us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.860s | 194.047us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.150s | 2.593ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.920s | 94.748us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.530s | 37.157us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.860s | 194.047us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.920s | 94.748us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 16.280s | 387.426us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 37.781m | 89.265ms | 46 | 50 | 92.00 |
| V2 | host_maxperf | i2c_host_perf | 34.479m | 600.000ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.740s | 54.897us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.532m | 5.271ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.189m | 2.531ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.310s | 161.568us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.240s | 599.008us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.290s | 427.810us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.822m | 3.013ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.700s | 1.077ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.120m | 5.731ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 55.602m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.030s | 2.376ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 38.946m | 110.870ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 42.625m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.351m | 3.652ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.520s | 1.585ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.610s | 424.694us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.720s | 286.856us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 33.723m | 61.353ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.351m | 3.652ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.582m | 21.967ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.750s | 1.664ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 46.592m | 36.802ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.720s | 2.103ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 9.950s | 10.003ms | 38 | 50 | 76.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.410s | 657.447us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.430s | 3.393ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 34.479m | 600.000ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 20.636m | 24.367ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.700s | 1.077ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 16.400s | 1.382ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.710s | 19.503us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.780s | 15.828us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.840s | 560.499us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.840s | 560.499us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 15.787us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 194.047us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 94.748us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 128.998us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 15.787us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 194.047us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 94.748us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 128.998us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1415 | 1592 | 88.88 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.380s | 1.274ms | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 122.259us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.380s | 1.274ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.079m | 38.684ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.954m | 38.551ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 23.560s | 3.058ms | 50 | 50 | 100.00 | |
| TOTAL | 1645 | 1842 | 89.31 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 47 | 34 | 25 | 53.19 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.72 | 96.51 | 89.73 | 97.22 | 69.05 | 93.48 | 98.44 | 90.63 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 53 failures:
0.i2c_target_unexp_stop.28272196085139237808137585457611662362624453553491181283618897490996561086415
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 25386515 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25386515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.15723495961661088190449446656744378434574586860976908306350956412986608812758
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 65743616 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 9 [0x9])
UVM_INFO @ 65743616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
1.i2c_target_stress_all.51092247485356833490479032201130449689701855028580555236031414714652408068433
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2633168297 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 3 [0x3])
UVM_INFO @ 2633168297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.33760710148355054160139275242579453247213600211205018328361334037656795491118
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8882848506 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 5 [0x5])
UVM_INFO @ 8882848506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
2.i2c_target_stress_all_with_rand_reset.65802413588224427812491707784814142880976568100861353776034906687297259434313
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4052329071 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 7 [0x7])
UVM_INFO @ 4052329071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.22348525843129837033443284674933178068541214697786861718744500512126406230531
Line 540, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38550585032 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 15 [0xf])
UVM_INFO @ 38550585032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
16.i2c_target_hrst.83644852367593833893176237051394741941962405135436729483534145035529360355526
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_hrst/latest/run.log
UVM_ERROR @ 1440374440 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 1 [0x1])
UVM_INFO @ 1440374440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_hrst.57589420905872262863962776145366359797530137350768449289736861623585919350756
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_hrst/latest/run.log
UVM_ERROR @ 445644560 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (19 [0x13] vs 3 [0x3])
UVM_INFO @ 445644560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 37 failures:
0.i2c_target_perf.41297914122110237507026214187316863965792403577705466269280869726626171007325
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 10307181196 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10307181196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.8633598405673514768343915823050855457845826168467109623610704218320448636446
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 12077526584 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12077526584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
10.i2c_target_stress_all.50773138294340957494213484846085753087369715061305785710625564294844810631565
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 12910606578 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12910606578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all.105976281859752216993557423581294295191994098813212273207557575681298442385547
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 14035091572 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 14035091572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 25 failures:
3.i2c_target_unexp_stop.24581744816529586165154971763814818916539846695416835876865422973119208230096
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.114052850076484780579348871147222380094152172019641925835708965626890742362643
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
5.i2c_target_perf.104772922158918393800553660278588390119538944113181344846322834614782860782623
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_perf.99023398811230760749416126163983607218656720325391525303034803345875612759100
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
9.i2c_host_perf.8381343461937964623255339373807205597918037363094426664475290133923428690349
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
Test i2c_target_stretch has 5 failures.
0.i2c_target_stretch.79414332062010061713528330856010948124195639078707930111496451960749038559321
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
Job ID: smart:e0f94049-0326-440b-afb3-02ab1bc6be89
7.i2c_target_stretch.42871500116388141472104772583380086872851466712746086586206762631817880613633
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
Job ID: smart:fda73ce0-679d-4d59-996b-8ff7eeb645f9
... and 3 more failures.
Test i2c_target_stress_all has 4 failures.
0.i2c_target_stress_all.37412146460639617566849517606426578192223372923668505782939019733060304517853
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
Job ID: smart:9a22a030-a3cd-407d-a28f-7bf5dfb0c4c0
15.i2c_target_stress_all.52524143282455363874741751770565353526593190650564101598879719516077402157939
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
Job ID: smart:a43297b3-335a-48e4-ab1f-fa66fe41fe6a
... and 2 more failures.
Test i2c_host_stress_all has 2 failures.
1.i2c_host_stress_all.22733982319839207133452894945752449950239377085554064328892648358958582547705
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:ad934e5d-ba96-432f-8252-7944e5c41218
18.i2c_host_stress_all.23482851607598422834832145819214560893453250838772411507217959377340760451856
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job ID: smart:e5c18b64-085d-4513-a546-d61f734bb5ae
Test i2c_host_stress_all_with_rand_reset has 1 failures.
3.i2c_host_stress_all_with_rand_reset.90795586754809117295801588461192434928859460580330468579938199656633049282590
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0ef0aa33-bbb2-4268-914c-42a0fc36053e
Test i2c_target_unexp_stop has 9 failures.
7.i2c_target_unexp_stop.91070275704938020782454319754346569039931554334031412997084297130829046070037
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Job ID: smart:39da0bd6-c0fe-4228-a0a4-205965bade53
11.i2c_target_unexp_stop.24281519404834736979959541039015430143799891344218423024134281556928532078733
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
Job ID: smart:317445d3-a6e7-483a-8747-dadd903c1d98
... and 7 more failures.
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 19 failures:
2.i2c_target_perf.10775513720393255326330701770427220231936115047821870550629250829729755127777
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_ERROR @ 11708556 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 118 [0x76])
UVM_INFO @ 11708556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_perf.36889671007389877782676838650530454902391797220459197223227001602471486513867
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
UVM_ERROR @ 31784065 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 110 [0x6e])
UVM_INFO @ 31784065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
4.i2c_target_stress_all.79992833890303222271240078403653890231809756185825549342742740430527972648041
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1331557682 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (96 [0x60] vs 239 [0xef])
UVM_INFO @ 1331557682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.63927097014372343643674112719130708757012168702143603958462960031445379875224
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 31657042 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 193 [0xc1])
UVM_INFO @ 31657042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
0.i2c_host_stress_all_with_rand_reset.46270186167539252118482748211840949308001070738846746552657814807640471634355
Line 392, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1378660749 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1378660749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.8605291493437052137148824419218277450040155916046262864179306841103772753050
Line 1529, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3188328502 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3188328502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all_with_rand_reset.49304575289280258873750524764538369172784264788608521186544023417077206891008
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2711373829 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2711373829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.60321978500002676826782786951475841748392557232086482435922640053160488852823
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111705703 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111705703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 7 failures:
6.i2c_target_stress_all.35327992128795270088092071217672095066869456302387510742370582468946929531739
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 110869812922 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 110869812922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.104313694876778107644359208787805080381329454124911139219376179737560620688457
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 142917335307 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 142917335307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.114147939997297366680449279774771785009495272846582754887350890670694096596100
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 205820031 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (110 [0x6e] vs 50 [0x32])
UVM_INFO @ 205820031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 4 failures.
19.i2c_target_hrst.47430079015621439861548400895224664498275709200544987014006574397830879468011
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_hrst/latest/run.log
UVM_ERROR @ 15477793 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (76 [0x4c] vs 161 [0xa1])
UVM_INFO @ 15477793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_hrst.78590957355878031171517732992815051798372482273355510749744912740603294751335
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_hrst/latest/run.log
UVM_ERROR @ 5964634 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (182 [0xb6] vs 183 [0xb7])
UVM_INFO @ 5964634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 4 failures:
2.i2c_target_unexp_stop.73848704536531999908021346315463659275314225989821374350413006576056421440184
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 821651527 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 821651527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.22196807243364176625767345120647921753575111184131256922993111487939329295526
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 824025863 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 824025863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 4 failures:
Test i2c_host_stress_all has 2 failures.
15.i2c_host_stress_all.97696677982432412733203687191192159826404205394244582744257499329331764379804
Line 2567, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 2856425242 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
23.i2c_host_stress_all.80299267989213412871174169619961177171039618399237350168879643524008183642351
Line 7792, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 26213268467 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
Test i2c_host_error_intr has 2 failures.
43.i2c_host_error_intr.83871768650205811990751099345701319452925014975294374836975259004645057178089
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 5023110 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
47.i2c_host_error_intr.105450700348163170208096924143279794665799238470860726152756742680700382010167
Line 418, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 32079066 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 3 failures:
7.i2c_target_hrst.76369765064125938684715625426584312791279101347932621504450733383710004917827
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_ERROR @ 66001149 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 66001149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_hrst.6649273153574030009793863761499257760804053974894340803142889499300104296595
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest/run.log
UVM_ERROR @ 37708804 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 37708804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
5.i2c_target_stress_all_with_rand_reset.89372431263907182665804679772293792847194247197584305105352597476527334651247
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10465762153 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x72dede94) == 0x0
UVM_INFO @ 10465762153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.45209513896948849294670403629296462475340210501061180660458476527237337578792
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 21481267772 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x59a54194) == 0x0
UVM_INFO @ 21481267772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
11.i2c_target_hrst.7049591491687604975204800621604224618883491387223619328829364619287027399138
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10002853556 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10002853556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
11.i2c_same_csr_outstanding.105503683486555614262244480692957190849780860683849570217422189899140917973250
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 202412945 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 202412945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_monitor.sv:587) monitor [monitor] ack_stop detected has 1 failures:
24.i2c_target_perf.92586461451172751077871809770730175679935634795488574447340397032695794916452
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_perf/latest/run.log
UVM_ERROR @ 503608610 ps: (i2c_monitor.sv:587) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 503608610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---