I2C Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.687m	4.027ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	49.470s	2.529ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.800s	88.882us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.830s	26.453us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.200s	2.398ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.980s	806.339us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.490s	30.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.830s	26.453us	20	20	100.00
		i2c_csr_aliasing	1.980s	806.339us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	9.400s	271.319us	48	50	96.00
V2	host_stress_all	i2c_host_stress_all	59.024m	21.720ms	45	50	90.00
V2	host_maxperf	i2c_host_perf	42.251m	24.394ms	48	50	96.00
V2	host_override	i2c_host_override	0.740s	34.969us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.800m	5.164ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.109m	4.903ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.250s	157.696us	50	50	100.00
		i2c_host_fifo_fmt_empty	27.690s	3.058ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.030s	994.585us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.157m	7.423ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	43.250s	1.845ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.896m	2.469ms	48	50	96.00
V2	target_error_intr	i2c_target_unexp_stop	24.536m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	10.560s	2.288ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	33.257m	100.772ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	17.177m	20.000ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.242m	9.084ms	50	50	100.00
		i2c_target_intr_smoke	7.480s	7.814ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.600s	304.530us	50	50	100.00
		i2c_target_fifo_reset_tx	1.590s	264.795us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	43.317m	65.944ms	50	50	100.00
		i2c_target_stress_rd	1.242m	9.084ms	50	50	100.00
		i2c_target_intr_stress_wr	7.965m	23.373ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.690s	3.308ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	35.585m	15.044ms	49	50	98.00
V2	bad_address	i2c_target_bad_addr	6.310s	7.965ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	23.540s	10.087ms	35	50	70.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.370s	1.897ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.520s	353.189us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	42.251m	24.394ms	48	50	96.00
		i2c_host_perf_precise	15.852m	23.206ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	43.250s	1.845ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.910s	1.139ms	50	50	100.00
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	alert_test	i2c_alert_test	0.700s	24.310us	50	50	100.00
V2	intr_test	i2c_intr_test	0.790s	33.666us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.190s	126.230us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.190s	126.230us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.800s	88.882us	5	5	100.00
		i2c_csr_rw	0.830s	26.453us	20	20	100.00
		i2c_csr_aliasing	1.980s	806.339us	5	5	100.00
		i2c_same_csr_outstanding	1.220s	101.848us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.800s	88.882us	5	5	100.00
		i2c_csr_rw	0.830s	26.453us	20	20	100.00
		i2c_csr_aliasing	1.980s	806.339us	5	5	100.00
		i2c_same_csr_outstanding	1.220s	101.848us	19	20	95.00
V2		TOTAL			1414	1592	88.82
V2S	tl_intg_err	i2c_tl_intg_err	2.350s	523.624us	20	20	100.00
		i2c_sec_cm	0.960s	126.069us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.350s	523.624us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.809m	36.805ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.374m	10.208ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	27.190s	674.767us	50	50	100.00
		TOTAL			1644	1842	89.25

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	47	34	24	51.06
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.83	96.57	89.88	97.22	69.64	93.55	98.44	90.53

Failure Buckets

UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 41 failures:
- Test i2c_target_perf has 31 failures.
  - 0.i2c_target_perf.34310237895663819342211477335819559522724103048227193966560419676855460227187
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 11116967280 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11116967280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.79321263529785445508110725464038696836251848829636333955931544658879334653427
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10954002783 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10954002783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
- Test i2c_target_stress_all has 10 failures.
  - 12.i2c_target_stress_all.43755179734861959099429662861799474887379130745995775483187623634175844846097
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 10433493357 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10433493357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all.31177862375193425014428318145611127697060984959970878417853147262358431699743
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 28977531507 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 28977531507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 38 failures:

Test i2c_target_stress_all_with_rand_reset has 2 failures.
- 0.i2c_target_stress_all_with_rand_reset.41253548858300779402779962122427617621683923254455618070273492126098100340058
  Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1148533680 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (23 [0x17] vs 6 [0x6])
  UVM_INFO @ 1148533680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 7.i2c_target_stress_all_with_rand_reset.43623511208940713695389401320928405054613089584267136302470528618040754464646
  Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 183755466 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 7 [0x7])
  UVM_INFO @ 183755466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_target_stress_all has 22 failures.

1.i2c_target_stress_all.52622058018256592750499734049797540660485569780521701516640226965646328256579
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 1883273452 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 8 [0x8])
  UVM_INFO @ 1883273452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all.114458044858594892352040505437262458823008405753961253002762449781930841408504
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  25985433 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 5 [0x5])
  UVM_INFO @  25985433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Test i2c_target_unexp_stop has 11 failures.

2.i2c_target_unexp_stop.73710888535797175178163173202994859094422138565374365632154973301973457872682
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 294736664 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 294736664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.1083750368798132524647710797497006382550595368209072979976040564720096126526
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  18866539 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 9 [0x9])
  UVM_INFO @  18866539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_target_hrst has 3 failures.

25.i2c_target_hrst.3749630213466773194982588018393895126159034134297096183952398890139301426534
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 105948163 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 24 [0x18])
  UVM_INFO @ 105948163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.i2c_target_hrst.87151947168263665805023981180786828691018914911892716113211023552330502834177
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_hrst/latest/run.log

  UVM_ERROR @  57156366 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 4 [0x4])
  UVM_INFO @  57156366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 26 failures:
- Test i2c_target_unexp_stop has 19 failures.
  - 1.i2c_target_unexp_stop.720974016254385949039975188357087538800604885099217652926396921811666921381
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_unexp_stop.67702202975053839028566015437309402903093228965205639600666514913876673082399
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
- Test i2c_target_perf has 7 failures.
  - 4.i2c_target_perf.97552631709938468013112823292405333422049864045576971682598278732451041695650
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_perf.13510222455831793714871934451820958915171768158890463983126428867650624106984
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.4227451231655966790537839669434374107320211728933209831867301752352617433273
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3695e23c-d3e5-4eee-8012-9ed5344788da
```
- Test i2c_host_perf has 2 failures.
  - 3.i2c_host_perf.55869566687353318487857524154552138972690465382962970017765824536845379835916
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_perf/latest/run.log
```
  Job ID: smart:e26ff79c-ef84-4f47-925c-3487949899fe
```
  - 29.i2c_host_perf.95825586172360251263233351082013113573552971988157457101481217280603260256055
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf/latest/run.log
```
  Job ID: smart:a4795a2e-ddd9-4e6c-b19d-110e697abcff
```
- Test i2c_target_stress_all has 5 failures.
  - 3.i2c_target_stress_all.88319441194400840654548084652565262884726109441740377367377007216691265846287
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:f9ed7a86-ad73-468d-9dc8-8d47ae64a201
```
  - 11.i2c_target_stress_all.6284546959898750311640674434747389822638791989909887805517834814472838369482
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:ecf6a9fe-a1c9-49f2-a55a-c451042257fc
```
  - ... and 3 more failures.
- Test i2c_target_unexp_stop has 14 failures.
  - 5.i2c_target_unexp_stop.102524406371282474576325803854006133665185760102604771996978416046001767816486
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:79d8627a-f02d-40cc-a5f5-534f372a0c37
```
  - 6.i2c_target_unexp_stop.67810058271244726371185100820081604375343214780251396228576099150347104383542
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:0e0e49d1-86a9-4c13-998e-54a0abe359f3
```
  - ... and 12 more failures.
- Test i2c_host_mode_toggle has 1 failures.
  - 15.i2c_host_mode_toggle.21319041950685831149584702552063325609218156264119685940038904700394921504399
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:7a019548-62de-4b2d-912b-1f042797309e
```
- ... and 2 more tests.

UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 16 failures:

Test i2c_target_perf has 12 failures.

7.i2c_target_perf.97115131732447343941318855823955069794062174217772071295713863190411034922572
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log

  UVM_ERROR @  26008177 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
  UVM_INFO @  26008177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.i2c_target_perf.28206463531006266803118627469379588898335736818046073756961039163457936276901
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_perf/latest/run.log

  UVM_ERROR @  56819484 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 115 [0x73])
  UVM_INFO @  56819484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test i2c_target_stress_all has 4 failures.

27.i2c_target_stress_all.51786862560756030635169856109100484232821501926751606178251599484139147424024
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  92621142 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 81 [0x51])
  UVM_INFO @  92621142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.i2c_target_stress_all.106249688284515746565495441310736134886847757567725625973337639600842437807761
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  84970499 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 71 [0x47])
  UVM_INFO @  84970499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

1.i2c_host_stress_all_with_rand_reset.76296850330145144211175062850932012800838248598246116716341597365809479866169
Line 4636, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16603289320 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16603289320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.19781051137104320169930181490635625658720277887627185107269017950856104853358
Line 4626, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10219903250 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10219903250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.112498885771922496581448116289381612718765201013880583430125389422306455723726
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4907958619 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4907958619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.1296534440332791284438815143153063455752996924077075287744002726511803534152
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2769773102 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2769773102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 8 failures:
- Test i2c_target_stress_all has 8 failures.
  - 5.i2c_target_stress_all.7927162570618624401849669657680135767614135192876112332340236670996608657275
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 101657619859 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 101657619859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_stress_all.113832036017757554511837418107006081808376352231883849064884316006853866438757
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 103176176154 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 103176176154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 7 failures:
- Test i2c_target_unexp_stop has 6 failures.
  - 0.i2c_target_unexp_stop.55719352821754553894403981863667170947999448897919128157481129773435019867213
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1271189823 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1271189823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_unexp_stop.51640932362227058549874426126930257814024257464658265824673078594810450953325
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 749230421 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 749230421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
- Test i2c_target_stress_all has 1 failures.
  - 0.i2c_target_stress_all.99963751950460235650183436200082689193110880292241427146549741731040406581751
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 707872412 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 707872412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 7 failures:
- Test i2c_target_hrst has 7 failures.
  - 24.i2c_target_hrst.101811534688587904164371436805010575526480899880560649112913849841014392128546
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  15744819 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  15744819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.i2c_target_hrst.79123034128054489300755882293151566294084303452055122520805314717133547638530
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  26653652 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  26653652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 6 failures:

Test i2c_host_stress_all has 4 failures.

14.i2c_host_stress_all.96641312491693283996481205611587969962183289108031165498939699866635416773795
Line 3248, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4539046953 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

17.i2c_host_stress_all.14555551785133095846599563423290545418736054465491901665005533528242748376978
Line 716, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log

  UVM_ERROR @  71035989 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

... and 2 more failures.

Test i2c_host_error_intr has 2 failures.

25.i2c_host_error_intr.82345306887587055938332548360311849891742938878649543695932199490147414180171
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  15296632 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

28.i2c_host_error_intr.55639480173374269193606455850522270692885460393948045827769328055551149071436
Line 410, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  15566038 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 4.i2c_target_stress_all_with_rand_reset.26590795241572519901552460384229262707894258934764592478021748990195418823056
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10207500045 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x2e747814) == 0x0
  UVM_INFO @ 10207500045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_stress_all_with_rand_reset.35825775292103963133405612441657885732431548154650495791282418459776141668455
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16111094804 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8d85c614) == 0x0
  UVM_INFO @ 16111094804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 3 failures:
- Test i2c_target_hrst has 3 failures.
  - 12.i2c_target_hrst.101084504697452895097177599546343157818717693507697683139356234221192019059582
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10015817148 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10015817148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.i2c_target_hrst.56772947740521038984948907031871114737085020061368359211973664624512843617859
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10026621284 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10026621284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 2 failures:

Test i2c_target_hrst has 2 failures.

13.i2c_target_hrst.107313782342792835503577202487258661265192117513213282366420251848294307653983
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10086811430 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10086811430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.i2c_target_hrst.39834809109574945020972945747161235992841114224547337349817472595941238793096
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10275776476 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10275776476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 15.i2c_same_csr_outstanding.84150315550314423418449617342887411422197766184508305559943318549011084972174
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 116679460 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 116679460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_o' has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 30.i2c_host_mode_toggle.15604497824533262909567156057987910185588317633139451107354786795059471285483
    Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_mode_toggle/latest/run.log
```
      Offending 'scl_o'
  UVM_ERROR @  80872769 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
  UVM_INFO @  80872769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```