3e678c112b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.743m | 11.447ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.330s | 4.757ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 24.959us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.850s | 25.117us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.230s | 522.213us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.040s | 290.574us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.810s | 124.837us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.850s | 25.117us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.040s | 290.574us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 11.310s | 974.912us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 51.741m | 243.337ms | 47 | 50 | 94.00 |
| V2 | host_maxperf | i2c_host_perf | 29.832m | 50.736ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.740s | 29.020us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.167m | 18.797ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.262m | 2.662ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.390s | 339.692us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.910s | 541.743us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.010s | 222.354us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.826m | 3.020ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 51.470s | 2.460ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.880m | 4.426ms | 49 | 50 | 98.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 22.050m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.610s | 8.236ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 51.069m | 102.729ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 32.480m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.198m | 7.197ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.650s | 1.886ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.680s | 899.223us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.660s | 450.181us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 33.641m | 63.764ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.198m | 7.197ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.211m | 26.144ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.210s | 1.349ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 56.955m | 29.760ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.040s | 4.078ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 2.266m | 10.064ms | 30 | 50 | 60.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.120s | 612.472us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.470s | 387.471us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 29.832m | 50.736ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 21.504m | 24.262ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 51.470s | 2.460ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 18.330s | 1.535ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.690s | 44.332us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 48.495us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.750s | 131.324us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.750s | 131.324us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 24.959us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 25.117us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.040s | 290.574us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 82.993us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 24.959us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 25.117us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.040s | 290.574us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 82.993us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1411 | 1592 | 88.63 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.460s | 565.279us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.210s | 998.990us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.460s | 565.279us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.906m | 25.224ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 7.146m | 48.237ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 31.970s | 1.503ms | 50 | 50 | 100.00 | |
| TOTAL | 1641 | 1842 | 89.09 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 47 | 34 | 25 | 53.19 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.87 | 96.57 | 89.80 | 97.22 | 69.64 | 93.55 | 98.44 | 90.84 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 56 failures:
0.i2c_target_stress_all.115365479805172635132361236082555339247421313019553875628497037799815389129507
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9750025479 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 14 [0xe])
UVM_INFO @ 9750025479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.70953916564319688977864807791990721112775275808937410718843065699941140186723
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6434425564 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 1 [0x1])
UVM_INFO @ 6434425564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
3.i2c_target_unexp_stop.74365810233304127037268893024502646803781445505526035417171180805018279174156
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 41122920 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 10 [0xa])
UVM_INFO @ 41122920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.109598854289644095558350486635944820707345537806800463622570494200813042903472
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 46909513 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46909513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
3.i2c_target_stress_all_with_rand_reset.48936418522501201609476526525695572699044383792405543507254421611774136364178
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 131631973 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
UVM_INFO @ 131631973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.58649936001232818077799210164431052849655066628481621010485442638602571914880
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21274085195 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 8 [0x8])
UVM_INFO @ 21274085195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
4.i2c_target_hrst.66553311936375177729830842685056231652790636711174159510897279324170532091788
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_ERROR @ 121992695 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (12 [0xc] vs 5 [0x5])
UVM_INFO @ 121992695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_hrst.65216691664414506297060879971295291315085701506537879904247415354675627011656
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_hrst/latest/run.log
UVM_ERROR @ 612989762 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 22 [0x16])
UVM_INFO @ 612989762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 35 failures:
1.i2c_target_stress_all.63092548153492446313068659020317214088197924053151732302126136636072948600703
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10579685058 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10579685058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all.12875031544620307745693673137087564797344302204395836551964790997176110297294
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10553368015 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10553368015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
2.i2c_target_perf.93648789323370054637083867395333886633460996013433791210834273248816537166477
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_FATAL @ 10607611746 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10607611746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_perf.91102868668494080741865328017161788484201908817494956678895173920986462328381
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
UVM_FATAL @ 13328169931 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 13328169931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 24 failures:
Test i2c_target_perf has 15 failures.
1.i2c_target_perf.75605375395251042648459216017316212116849823199049955635195608044008589966416
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 52195542 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 240 [0xf0])
UVM_INFO @ 52195542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_perf.23600269728019177485285635836668134358709840277450460138622516783988349695112
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log
UVM_ERROR @ 424629280 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 254 [0xfe])
UVM_INFO @ 424629280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
1.i2c_target_stress_all_with_rand_reset.23936867083012217468794106987584653331939765683671989366817962939189020316932
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19190081279 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (54 [0x36] vs 100 [0x64])
UVM_INFO @ 19190081279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.33116801029539540253537782166996139637753692248383621585537849576882426683800
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4594551086 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 179 [0xb3])
UVM_INFO @ 4594551086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 6 failures.
2.i2c_target_stress_all.22756815274303177621599474852407901929045095276893697690548004407992470572285
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 45694530 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 248 [0xf8])
UVM_INFO @ 45694530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.94966440410886673407859188824008192501511903103570234314845644358195423995415
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8864150404 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (105 [0x69] vs 192 [0xc0])
UVM_INFO @ 8864150404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test i2c_target_hrst has 1 failures.
9.i2c_target_hrst.84593725389032452137361892525213615930977481654736490133944235324958709651153
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
UVM_ERROR @ 117543660 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (9 [0x9] vs 82 [0x52])
UVM_INFO @ 117543660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
Test i2c_target_unexp_stop has 6 failures.
2.i2c_target_unexp_stop.113502628667344754183961402433655098722247269053778251944787914713067186142479
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Job ID: smart:6279c850-67e2-42a4-8fda-f6f35b755fd1
29.i2c_target_unexp_stop.34177860520452671983691673331115941318335963434922175337955609410560799544825
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
Job ID: smart:2a7bad3d-c31a-4227-9663-38f5f7f8252f
... and 4 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
3.i2c_host_stress_all_with_rand_reset.11698066005499501740173379308372931982677613725739600304198857548433649972613
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:65020d80-7c18-44fe-a6d0-19a329d82cb9
Test i2c_host_stress_all has 2 failures.
5.i2c_host_stress_all.92580545804616318513666575060447383100038597632348492746911538724543182761849
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:5235ef09-16ed-4504-9521-31bcfb4d36d8
26.i2c_host_stress_all.23636871479212688814001866362155827383993495812271383599129740805188668009509
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
Job ID: smart:6bb37188-6056-408e-8db3-87a133d964ea
Test i2c_target_stretch has 5 failures.
6.i2c_target_stretch.38471871243094974657970721226889961822203168126157010371588478249964896856524
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
Job ID: smart:48b49154-ad45-4e9b-83ce-beac1923fd16
20.i2c_target_stretch.109625672220646255088917573951283431103913909521352271078296275615540120977281
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stretch/latest/run.log
Job ID: smart:9402f540-4e26-4549-9849-bfb8152c21a6
... and 3 more failures.
Test i2c_target_stress_all has 5 failures.
6.i2c_target_stress_all.20397466564814341214164420027857595723029008235472219920023513098237294069657
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
Job ID: smart:73054f53-0f69-4922-b349-a99830ce25ca
7.i2c_target_stress_all.88202182607997133640995557121509615661658679917322324704125906659654670981100
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
Job ID: smart:cf0f947d-ca6d-4897-858d-a1fd5e0f2636
... and 3 more failures.
... and 1 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
0.i2c_target_unexp_stop.103351855241824348662201695700073254876526815579699975889564480513874881071614
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.94022916237846771901159500778628101800404101091095106680920566102621920172160
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_perf.28802835421537868303527315290382842647375840632203224819754206878118553167841
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_perf.53991537264972960738384686910390946551835802633277347777426415475659273373
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
0.i2c_host_stress_all_with_rand_reset.6284074970283939973365188502506710284664611357522606703413390860160641603295
Line 6022, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25224026948 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 25224026948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.92810253961979143114464016928939934539763383543648611259504961724966694450651
Line 3030, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2099000103 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2099000103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
2.i2c_target_stress_all_with_rand_reset.60832656721500043999696133248706440428090020884340157533198953348930592058526
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1549119068 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1549119068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.91080241684720103045117026633595975117565417588702105496647775111903377055966
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1154855315 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1154855315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 9 failures:
11.i2c_target_unexp_stop.53846483847226376974822022658146458962175560672976515946275297756881104442511
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 943573497 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 943573497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_unexp_stop.6318670784413048218614315728057875010435522254608742784493446638770700679940
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1587183602 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1587183602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
20.i2c_target_stress_all.5792383121431923794675640851641235696748393766784433438059544931282020004204
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1871977955 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1871977955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.i2c_target_stress_all.42648238719486043802260863747883621999654385188801435984304126220327006679015
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 37182620891 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 37182620891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
5.i2c_target_hrst.27114965951591157288956781243310806025263184950651889473955107853299201237433
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_ERROR @ 19400542 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (154 [0x9a] vs 155 [0x9b])
UVM_INFO @ 19400542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_hrst.14133850824315948663024184121010931066892178985223419283627054018212987889746
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_hrst/latest/run.log
UVM_ERROR @ 88039861 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (24 [0x18] vs 25 [0x19])
UVM_INFO @ 88039861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
6.i2c_target_stress_all_with_rand_reset.106079424640602626932992538860282676050019292366489149909617931911468680480993
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2527904354 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (224 [0xe0] vs 122 [0x7a])
UVM_INFO @ 2527904354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 5 failures:
3.i2c_target_hrst.3832949359565984606843610833556154961714331598044157407017580330866696806041
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_ERROR @ 32677996 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 32677996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_hrst.14129425231197730522205929247999504853788963817572614595591424369103555165696
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log
UVM_ERROR @ 65788175 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 65788175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 5 failures:
4.i2c_target_stress_all.64006981476195901666857431651254423589014106548148437338242289320614540249344
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 123228668636 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 123228668636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all.8362007982671540897913258960592344656795947794119578314349334568026517652321
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100929070325 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100929070325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 5 failures:
8.i2c_target_hrst.111507044469008485183858779773340749791092946066982980014354571340382681859606
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10054213652 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10054213652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_hrst.69003470775931090736186082385751242382296032310173868284640297647837858130413
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10012935442 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10012935442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
0.i2c_target_stress_all_with_rand_reset.39539586296398329265232569762653790599885254336457591551841218142295889375931
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 48237497957 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x424ffe94) == 0x0
UVM_INFO @ 48237497957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.113230603280336619730757179502646142710370373624725606428036877425962990190935
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10573342729 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x94982494) == 0x0
UVM_INFO @ 10573342729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 2 failures:
7.i2c_target_hrst.49485928919488758000118293742798171898125210692117560385631253623844157070913
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10063528279 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10063528279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_hrst.64662630325747475546220673557528185993654980004079206783792433470808137202005
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10018109187 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10018109187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
1.i2c_target_unexp_stop.74204665522205727180101989901453457605402312270388904830411207620387727963973
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 10903347707 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10903347707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
6.i2c_target_fifo_watermarks_tx.81467379006603377227945283425079529298738426164047703156970237126625106962647
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
44.i2c_host_stress_all.46863193044919868514366739324293390833976466864863633695913593564649052253920
Line 2119, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18046249549 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
Offending 'scl_o' has 1 failures:
47.i2c_host_mode_toggle.40985913963884781418175845893934316619164762560341774380419674065572137220149
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 50022409 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 50022409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---