I2C Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.827m	8.121ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	54.510s	5.056ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.800s	32.022us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.200s	238.325us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.900s	1.400ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	4.990s	2.984ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.640s	110.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.200s	238.325us	20	20	100.00
		i2c_csr_aliasing	4.990s	2.984ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.180s	273.865us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	59.551m	102.786ms	44	50	88.00
V2	host_maxperf	i2c_host_perf	38.646m	27.732ms	49	50	98.00
V2	host_override	i2c_host_override	0.760s	95.404us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.579m	100.224ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.218m	4.794ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.340s	191.160us	50	50	100.00
		i2c_host_fifo_fmt_empty	23.160s	1.565ms	50	50	100.00
		i2c_host_fifo_reset_rx	10.820s	695.048us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.335m	28.543ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	46.020s	8.435ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.433m	2.767ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	57.813m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	12.810s	2.313ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	45.976m	131.463ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	3.582m	10.551ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.353m	32.514ms	50	50	100.00
		i2c_target_intr_smoke	8.500s	1.377ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.640s	1.180ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.630s	853.397us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	24.058m	55.276ms	50	50	100.00
		i2c_target_stress_rd	1.353m	32.514ms	50	50	100.00
		i2c_target_intr_stress_wr	6.882m	21.050ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.510s	3.084ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	4.643m	6.032ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	5.590s	1.200ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	2.351m	10.043ms	32	50	64.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.270s	653.945us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.370s	148.312us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	38.646m	27.732ms	49	50	98.00
		i2c_host_perf_precise	31.281m	24.280ms	49	50	98.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	46.020s	8.435ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	20.460s	1.764ms	50	50	100.00
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	alert_test	i2c_alert_test	0.680s	18.958us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	15.841us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.620s	199.400us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.620s	199.400us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.800s	32.022us	5	5	100.00
		i2c_csr_rw	1.200s	238.325us	20	20	100.00
		i2c_csr_aliasing	4.990s	2.984ms	5	5	100.00
		i2c_same_csr_outstanding	1.260s	185.477us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.800s	32.022us	5	5	100.00
		i2c_csr_rw	1.200s	238.325us	20	20	100.00
		i2c_csr_aliasing	4.990s	2.984ms	5	5	100.00
		i2c_same_csr_outstanding	1.260s	185.477us	19	20	95.00
V2		TOTAL			1409	1592	88.51
V2S	tl_intg_err	i2c_tl_intg_err	2.510s	909.156us	20	20	100.00
		i2c_sec_cm	0.980s	79.464us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.510s	909.156us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.744m	19.316ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.058m	24.507ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	23.320s	1.107ms	50	50	100.00
		TOTAL			1639	1842	88.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	47	34	24	51.06
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.85	96.60	90.03	97.22	69.64	93.62	98.44	90.42

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:609) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 62 failures:

Test i2c_target_unexp_stop has 24 failures.

0.i2c_target_unexp_stop.87611628837067310251617358369249786274137712191744777708508798531047168667284
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  64723781 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 7 [0x7])
  UVM_INFO @  64723781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.2902809445041278935387606939198922067364556836470099732508012394150951544087
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  44014179 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
  UVM_INFO @  44014179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test i2c_target_stress_all has 26 failures.

0.i2c_target_stress_all.80499081065896710099156008357461548666624251932625587542102194578340264358266
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 5425958924 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 3 [0x3])
  UVM_INFO @ 5425958924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all.38537778666643409553207977564756962646837967606270398752024682546351195781232
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  31409241 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
  UVM_INFO @  31409241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.
- 0.i2c_target_stress_all_with_rand_reset.20122440158738729024121930344864105468496799911551412243705339685416759768332
  Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23729303756 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 23729303756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 3.i2c_target_stress_all_with_rand_reset.60705668159503134646995075694555923018867145357704770341074934916561265625597
  Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5256024092 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 3 [0x3])
  UVM_INFO @ 5256024092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- ... and 3 more failures.

Test i2c_target_hrst has 7 failures.

6.i2c_target_hrst.47693965538785359941528104670726057283997545081080826082161297840629547326401
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 174441009 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (15 [0xf] vs 7 [0x7])
  UVM_INFO @ 174441009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_target_hrst.78077135824086309867828553416516615517906680052626025766402644076626616081772
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 494704114 ps: (i2c_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 5 [0x5])
  UVM_INFO @ 494704114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred! has 46 failures:
- Test i2c_target_perf has 37 failures.
  - 0.i2c_target_perf.104364289294882071136132082809920086917199960747161352347259051329574048863033
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 11160545023 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11160545023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_perf.28045231419779198697923124497937263184877758970062385261276182290309727852287
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10724606998 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10724606998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
- Test i2c_target_stress_all has 9 failures.
  - 1.i2c_target_stress_all.96572214352261831206977151680051372720830544577556279076412473582320811676955
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 12922352759 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 12922352759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.i2c_target_stress_all.405381567265122334433033398105750853035694896828764421896245798068992714796
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 11602987428 ps: (i2c_base_vseq.sv:1172) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11602987428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_host_stress_all_with_rand_reset.2156270474087260220516318813245333781278324172293055410728206079251673633309
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:853b0cde-89fe-443b-a5da-7afe5474d43c
```
- Test i2c_target_unexp_stop has 5 failures.
  - 4.i2c_target_unexp_stop.72956850892167679492240388307784150717923455914626912234595455396236561705235
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:a80011f7-bc68-43db-9360-49af568d2d52
```
  - 13.i2c_target_unexp_stop.81864402695576740625026795523611347299393865405625235184182913558401788323835
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:d1401bf2-57d2-4aff-b4e4-3c1344940995
```
  - ... and 3 more failures.
- Test i2c_target_stress_all has 6 failures.
  - 5.i2c_target_stress_all.6931525781218279705549127803176761701985499089086899840389495617436784792753
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:494c63f4-b177-4b60-a155-d582a992e2aa
```
  - 12.i2c_target_stress_all.38800672272489698035800327057485045629157514802259703488582627806897504016064
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:51fea3d1-43c3-4376-9f0d-6e98d7e6f153
```
  - ... and 4 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.45911681913349312629099127564657506357385787344791255592985580304739420154615
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c6cfcb18-5a6d-47e6-b725-3bfc64f4c31f
```
- Test i2c_host_perf_precise has 1 failures.
  - 12.i2c_host_perf_precise.100335966874601125159837173061543079419488017979009971592127717839733444254455
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf_precise/latest/run.log
```
  Job ID: smart:8864a65d-4ab3-44f1-918d-4b167d344c92
```
- ... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
- Test i2c_target_unexp_stop has 15 failures.
  - 1.i2c_target_unexp_stop.34040660660345274869225757272504444693235070290142197736218385672798306318590
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_unexp_stop.48757621105337267796391940345673104483143250685658228061598254810522546572954
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
- Test i2c_target_perf has 2 failures.
  - 35.i2c_target_perf.14306706726430843169756146961992393479258989829507302236116423368884270675776
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.i2c_target_perf.6301583998824625172885406351798224123358820867463340416905617243326314132009
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:613) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 15 failures:

Test i2c_target_perf has 11 failures.

1.i2c_target_perf.97720166259820343518033266620923406467731959695710325510994783553807967565841
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log

  UVM_ERROR @  38220004 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 37 [0x25])
  UVM_INFO @  38220004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_perf.63033098669957220133943170607940674099931452754586158322861907994138579437368
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log

  UVM_ERROR @  14165803 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 243 [0xf3])
  UVM_INFO @  14165803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_target_stress_all has 4 failures.

14.i2c_target_stress_all.96625663534502284718100862376368425343264065201164628667823498606625696336738
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 26109700027 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (79 [0x4f] vs 190 [0xbe])
  UVM_INFO @ 26109700027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.i2c_target_stress_all.5527518618927962302757235568927729450022191912717851005838328850241446944419
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 144545173 ps: (i2c_scoreboard.sv:613) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 228 [0xe4])
  UVM_INFO @ 144545173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.77240815802003341730991575513633702896755640518559108994100847435297127002233
Line 2085, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4873209249 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4873209249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.31719387164765247066718305780870124987464954006147280817817842290748173332629
Line 614, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2141447399 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2141447399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.

4.i2c_target_stress_all_with_rand_reset.59498960437872717433389891528661549330421659866112526422215742521790779851676
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 580642707 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 580642707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.25944540185508418539192761109252226819383697531372682907461465030523698206534
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4391513223 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4391513223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
- Test i2c_target_unexp_stop has 6 failures.
  - 7.i2c_target_unexp_stop.64112742234659841922875532336720959313818499457121489482733933364199654836774
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 3427347739 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3427347739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_unexp_stop.66613880775095997639193643002020596214127228698797835789849620112150052661628
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 719146141 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 719146141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 2.i2c_target_stretch.67074432372072849055777358589857823737540373119308078179063900610965044146609
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10057318962 ps: (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred!
  UVM_INFO @ 10057318962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stretch.21120650997538436446082835165576954893320127569247595953286446040051985821527
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012832324 ps: (i2c_base_vseq.sv:694) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012832324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 5 failures:

Test i2c_target_hrst has 5 failures.

3.i2c_target_hrst.113380656974818420677190607413282797742750078963730779468487438465771159422535
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10087883222 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10087883222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_hrst.109967519028378798600793708491736152639041544414318114501244362527437973232981
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10043193491 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10043193491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred! has 5 failures:
- Test i2c_target_stress_all has 5 failures.
  - 8.i2c_target_stress_all.72039392302487937734499104302976733837946458679071351162415138692010981566708
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 100806547069 ps: (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 100806547069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.i2c_target_stress_all.33181784452343814882212093782888056812514097279156755949378049346091621400034
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 158956698607 ps: (i2c_driver.sv:239) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 158956698607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 4 failures:
- Test i2c_target_hrst has 4 failures.
  - 1.i2c_target_hrst.86741606714193552352223699299455200638846648637895067520899740629255786057518
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  20024634 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  20024634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_hrst.37146920220531474218357839306984709994293777902576154799686317156144095096938
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  13277677 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  13277677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:590) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.41917816237475940022086162403832710131936572879636036514799995946871482614035
    Line 331, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14758391024 ps: (i2c_scoreboard.sv:590) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (193 [0xc1] vs 192 [0xc0])
  UVM_INFO @ 14758391024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_hrst has 2 failures.
  - 26.i2c_target_hrst.44193102431240694273781107177132994562639355538986511136662327828658820426555
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @   3712812 ps: (i2c_scoreboard.sv:590) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (216 [0xd8] vs 217 [0xd9])
  UVM_INFO @   3712812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.i2c_target_hrst.11640655250592061675979628693519094406857358319968683384854208899261504673893
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  59747543 ps: (i2c_scoreboard.sv:590) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (194 [0xc2] vs 195 [0xc3])
  UVM_INFO @  59747543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 3 failures:

Test i2c_host_stress_all has 3 failures.

2.i2c_host_stress_all.79909300689633883985424721318645668850440219908853549445367147582643575195742
Line 2185, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 8520164780 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

7.i2c_host_stress_all.1505192281764699467227275395138029727407236906443582821893408000238706413483
Line 8586, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 17512957060 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.96520636191845582162527029828725199208559667746988009603884080468041329588388
    Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13757911448 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x26d5214) == 0x0
  UVM_INFO @ 13757911448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 12.i2c_same_csr_outstanding.24801125155299540791087887981224680152424819285116883133020258338761064193141
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  67936356 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  67936356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 47.i2c_target_fifo_watermarks_tx.7456061842474182856253043968143351920008158852291282256097564000375389931132
    Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 713
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```