| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1694761337 |
|
|
Aug 25 06:25:48 AM UTC 24 |
Aug 25 06:25:51 AM UTC 24 |
157983281 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.2439506136 |
|
|
Aug 25 06:25:25 AM UTC 24 |
Aug 25 06:25:51 AM UTC 24 |
997376313 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2959467322 |
|
|
Aug 25 06:25:51 AM UTC 24 |
Aug 25 06:25:57 AM UTC 24 |
2546476902 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.3182342434 |
|
|
Aug 25 06:25:47 AM UTC 24 |
Aug 25 06:25:53 AM UTC 24 |
545251222 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1295468189 |
|
|
Aug 25 06:25:50 AM UTC 24 |
Aug 25 06:25:53 AM UTC 24 |
1091175815 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_alert_test.254016750 |
|
|
Aug 25 06:25:52 AM UTC 24 |
Aug 25 06:25:54 AM UTC 24 |
17220261 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3181294486 |
|
|
Aug 25 06:25:52 AM UTC 24 |
Aug 25 06:25:55 AM UTC 24 |
146840981 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2169668509 |
|
|
Aug 25 06:25:56 AM UTC 24 |
Aug 25 06:25:59 AM UTC 24 |
134148509 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2625118544 |
|
|
Aug 25 06:25:49 AM UTC 24 |
Aug 25 06:25:59 AM UTC 24 |
461334169 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2359947938 |
|
|
Aug 25 06:25:43 AM UTC 24 |
Aug 25 06:26:02 AM UTC 24 |
3431175853 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1094391635 |
|
|
Aug 25 06:23:20 AM UTC 24 |
Aug 25 06:26:02 AM UTC 24 |
19655601630 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.3207636618 |
|
|
Aug 25 06:25:20 AM UTC 24 |
Aug 25 06:26:06 AM UTC 24 |
6178023409 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.3350101835 |
|
|
Aug 25 06:25:57 AM UTC 24 |
Aug 25 06:26:06 AM UTC 24 |
213766679 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3409214402 |
|
|
Aug 25 06:26:03 AM UTC 24 |
Aug 25 06:26:06 AM UTC 24 |
195941599 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_perf.3350814972 |
|
|
Aug 25 06:26:00 AM UTC 24 |
Aug 25 06:26:08 AM UTC 24 |
543093707 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2998324308 |
|
|
Aug 25 06:24:39 AM UTC 24 |
Aug 25 06:26:13 AM UTC 24 |
4646817829 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3674735329 |
|
|
Aug 25 06:26:00 AM UTC 24 |
Aug 25 06:26:17 AM UTC 24 |
3069589216 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.2913536049 |
|
|
Aug 25 06:24:51 AM UTC 24 |
Aug 25 06:26:21 AM UTC 24 |
6386406405 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2600054779 |
|
|
Aug 25 06:25:34 AM UTC 24 |
Aug 25 06:26:21 AM UTC 24 |
19252939442 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.2294312943 |
|
|
Aug 25 06:26:14 AM UTC 24 |
Aug 25 06:26:28 AM UTC 24 |
1127817522 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.336845089 |
|
|
Aug 25 06:25:57 AM UTC 24 |
Aug 25 06:26:29 AM UTC 24 |
907333307 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3241094309 |
|
|
Aug 25 06:12:32 AM UTC 24 |
Aug 25 06:26:29 AM UTC 24 |
44446339156 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.293792403 |
|
|
Aug 25 06:26:17 AM UTC 24 |
Aug 25 06:26:30 AM UTC 24 |
1089065366 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1963683853 |
|
|
Aug 25 06:25:09 AM UTC 24 |
Aug 25 06:26:30 AM UTC 24 |
12339725495 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.2117721097 |
|
|
Aug 25 06:25:53 AM UTC 24 |
Aug 25 06:26:31 AM UTC 24 |
5776676782 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.3542459075 |
|
|
Aug 25 06:26:21 AM UTC 24 |
Aug 25 06:26:32 AM UTC 24 |
1196702369 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.2171706184 |
|
|
Aug 25 06:26:08 AM UTC 24 |
Aug 25 06:26:33 AM UTC 24 |
1644199791 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3675353109 |
|
|
Aug 25 06:26:31 AM UTC 24 |
Aug 25 06:26:33 AM UTC 24 |
352988036 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.616166985 |
|
|
Aug 25 06:26:30 AM UTC 24 |
Aug 25 06:26:34 AM UTC 24 |
346868164 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.3142700031 |
|
|
Aug 25 05:58:52 AM UTC 24 |
Aug 25 06:27:28 AM UTC 24 |
55409067221 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.1855291390 |
|
|
Aug 25 06:24:41 AM UTC 24 |
Aug 25 06:26:35 AM UTC 24 |
24641728903 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.2124116028 |
|
|
Aug 25 06:26:42 AM UTC 24 |
Aug 25 06:27:28 AM UTC 24 |
6986622762 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.2103461860 |
|
|
Aug 25 06:25:28 AM UTC 24 |
Aug 25 06:26:38 AM UTC 24 |
4409963609 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1352848953 |
|
|
Aug 25 06:26:34 AM UTC 24 |
Aug 25 06:26:39 AM UTC 24 |
478093858 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.972342694 |
|
|
Aug 25 06:26:03 AM UTC 24 |
Aug 25 06:26:39 AM UTC 24 |
1290001955 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.3343660473 |
|
|
Aug 25 06:24:01 AM UTC 24 |
Aug 25 06:26:39 AM UTC 24 |
16430502970 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.344029135 |
|
|
Aug 25 06:05:36 AM UTC 24 |
Aug 25 06:27:29 AM UTC 24 |
54828077459 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3474640241 |
|
|
Aug 25 06:26:32 AM UTC 24 |
Aug 25 06:26:41 AM UTC 24 |
15919104281 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3809855282 |
|
|
Aug 25 06:26:32 AM UTC 24 |
Aug 25 06:26:41 AM UTC 24 |
807099736 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2660567582 |
|
|
Aug 25 06:26:34 AM UTC 24 |
Aug 25 06:26:42 AM UTC 24 |
353347765 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_alert_test.270472819 |
|
|
Aug 25 06:26:41 AM UTC 24 |
Aug 25 06:26:43 AM UTC 24 |
28443392 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2730561204 |
|
|
Aug 25 06:25:24 AM UTC 24 |
Aug 25 06:26:43 AM UTC 24 |
18779396956 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.3008581145 |
|
|
Aug 25 06:26:40 AM UTC 24 |
Aug 25 06:26:43 AM UTC 24 |
313243781 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.482608057 |
|
|
Aug 25 06:26:39 AM UTC 24 |
Aug 25 06:26:44 AM UTC 24 |
2240070883 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3882265133 |
|
|
Aug 25 06:26:35 AM UTC 24 |
Aug 25 06:26:44 AM UTC 24 |
402369782 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.430385458 |
|
|
Aug 25 06:26:40 AM UTC 24 |
Aug 25 06:26:44 AM UTC 24 |
477916595 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_override.3070099914 |
|
|
Aug 25 06:26:42 AM UTC 24 |
Aug 25 06:26:44 AM UTC 24 |
47653938 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2666222108 |
|
|
Aug 25 06:26:38 AM UTC 24 |
Aug 25 06:26:45 AM UTC 24 |
665008679 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2871958882 |
|
|
Aug 25 06:26:07 AM UTC 24 |
Aug 25 06:26:46 AM UTC 24 |
930222519 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.836192640 |
|
|
Aug 25 06:26:43 AM UTC 24 |
Aug 25 06:26:46 AM UTC 24 |
555241284 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.4101300835 |
|
|
Aug 25 06:27:19 AM UTC 24 |
Aug 25 06:27:33 AM UTC 24 |
2599242712 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1441266187 |
|
|
Aug 25 06:26:46 AM UTC 24 |
Aug 25 06:26:49 AM UTC 24 |
80409045 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.2114140918 |
|
|
Aug 25 06:22:51 AM UTC 24 |
Aug 25 06:26:53 AM UTC 24 |
16412331026 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.4277701026 |
|
|
Aug 25 06:26:44 AM UTC 24 |
Aug 25 06:26:53 AM UTC 24 |
212542747 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_perf.3361996995 |
|
|
Aug 25 06:04:37 AM UTC 24 |
Aug 25 06:26:54 AM UTC 24 |
73253991699 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.2646333300 |
|
|
Aug 25 06:21:19 AM UTC 24 |
Aug 25 06:26:56 AM UTC 24 |
18349432491 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.121705151 |
|
|
Aug 25 06:26:47 AM UTC 24 |
Aug 25 06:27:01 AM UTC 24 |
1323282248 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.946147196 |
|
|
Aug 25 06:25:22 AM UTC 24 |
Aug 25 06:27:03 AM UTC 24 |
9872329465 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.1679001689 |
|
|
Aug 25 06:26:46 AM UTC 24 |
Aug 25 06:27:03 AM UTC 24 |
4357785649 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_perf.2211121250 |
|
|
Aug 25 06:19:19 AM UTC 24 |
Aug 25 06:27:04 AM UTC 24 |
50964972426 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3119174123 |
|
|
Aug 25 06:26:46 AM UTC 24 |
Aug 25 06:27:05 AM UTC 24 |
2959105613 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3985305047 |
|
|
Aug 25 06:27:26 AM UTC 24 |
Aug 25 06:27:36 AM UTC 24 |
1985232076 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2867427196 |
|
|
Aug 25 06:27:03 AM UTC 24 |
Aug 25 06:27:06 AM UTC 24 |
168754359 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.4135827957 |
|
|
Aug 25 06:26:54 AM UTC 24 |
Aug 25 06:27:06 AM UTC 24 |
6222640812 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3352651645 |
|
|
Aug 25 06:26:49 AM UTC 24 |
Aug 25 06:27:07 AM UTC 24 |
709756483 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.719414978 |
|
|
Aug 25 06:25:24 AM UTC 24 |
Aug 25 06:27:07 AM UTC 24 |
3183111105 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.1589246636 |
|
|
Aug 25 06:27:05 AM UTC 24 |
Aug 25 06:27:07 AM UTC 24 |
151878773 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3807242921 |
|
|
Aug 25 06:25:55 AM UTC 24 |
Aug 25 06:27:10 AM UTC 24 |
45174212121 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3559193158 |
|
|
Aug 25 06:27:08 AM UTC 24 |
Aug 25 06:27:11 AM UTC 24 |
344907221 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.3487998862 |
|
|
Aug 25 06:27:07 AM UTC 24 |
Aug 25 06:27:11 AM UTC 24 |
279046533 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.3869935506 |
|
|
Aug 25 06:26:57 AM UTC 24 |
Aug 25 06:27:12 AM UTC 24 |
1425622792 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1884324674 |
|
|
Aug 25 06:27:08 AM UTC 24 |
Aug 25 06:27:12 AM UTC 24 |
283905148 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2141626140 |
|
|
Aug 25 06:27:11 AM UTC 24 |
Aug 25 06:27:15 AM UTC 24 |
82443251 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_perf.2850524369 |
|
|
Aug 25 06:27:05 AM UTC 24 |
Aug 25 06:27:15 AM UTC 24 |
4239130393 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.1897519276 |
|
|
Aug 25 06:27:13 AM UTC 24 |
Aug 25 06:27:16 AM UTC 24 |
1752124077 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.2748147412 |
|
|
Aug 25 06:27:11 AM UTC 24 |
Aug 25 06:27:16 AM UTC 24 |
884043519 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.550452657 |
|
|
Aug 25 06:26:44 AM UTC 24 |
Aug 25 06:27:16 AM UTC 24 |
678356044 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2725813852 |
|
|
Aug 25 06:27:15 AM UTC 24 |
Aug 25 06:27:17 AM UTC 24 |
41348667 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.279850246 |
|
|
Aug 25 06:26:53 AM UTC 24 |
Aug 25 06:27:17 AM UTC 24 |
3163716106 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2170263649 |
|
|
Aug 25 06:27:12 AM UTC 24 |
Aug 25 06:27:18 AM UTC 24 |
537147420 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2097993028 |
|
|
Aug 25 06:27:07 AM UTC 24 |
Aug 25 06:27:18 AM UTC 24 |
6231061597 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_override.2045723410 |
|
|
Aug 25 06:27:17 AM UTC 24 |
Aug 25 06:27:19 AM UTC 24 |
71874207 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.4148336112 |
|
|
Aug 25 06:27:12 AM UTC 24 |
Aug 25 06:27:19 AM UTC 24 |
1049315609 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3797674076 |
|
|
Aug 25 06:27:17 AM UTC 24 |
Aug 25 06:27:20 AM UTC 24 |
446122360 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3425238200 |
|
|
Aug 25 06:27:08 AM UTC 24 |
Aug 25 06:27:21 AM UTC 24 |
4358970715 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1537512476 |
|
|
Aug 25 06:27:20 AM UTC 24 |
Aug 25 06:27:25 AM UTC 24 |
596679641 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2896293629 |
|
|
Aug 25 06:27:18 AM UTC 24 |
Aug 25 06:27:27 AM UTC 24 |
257893502 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.1124144992 |
|
|
Aug 25 06:27:29 AM UTC 24 |
Aug 25 06:27:37 AM UTC 24 |
5659651477 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.1655850064 |
|
|
Aug 25 06:27:37 AM UTC 24 |
Aug 25 06:27:40 AM UTC 24 |
410521247 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.1737008431 |
|
|
Aug 25 06:27:30 AM UTC 24 |
Aug 25 06:27:43 AM UTC 24 |
5544594020 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3317426417 |
|
|
Aug 25 06:27:39 AM UTC 24 |
Aug 25 06:27:43 AM UTC 24 |
958133242 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.773587183 |
|
|
Aug 25 06:27:20 AM UTC 24 |
Aug 25 06:27:43 AM UTC 24 |
3832216532 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.4265081398 |
|
|
Aug 25 06:27:29 AM UTC 24 |
Aug 25 06:27:46 AM UTC 24 |
614653123 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1976452763 |
|
|
Aug 25 06:27:34 AM UTC 24 |
Aug 25 06:27:46 AM UTC 24 |
1783444020 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_perf.1861799493 |
|
|
Aug 25 06:27:41 AM UTC 24 |
Aug 25 06:27:49 AM UTC 24 |
749552702 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.273837460 |
|
|
Aug 25 06:27:18 AM UTC 24 |
Aug 25 06:27:49 AM UTC 24 |
2053261454 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1453175680 |
|
|
Aug 25 06:27:19 AM UTC 24 |
Aug 25 06:27:50 AM UTC 24 |
6822752523 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.958204430 |
|
|
Aug 25 06:27:44 AM UTC 24 |
Aug 25 06:27:51 AM UTC 24 |
702019810 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1365859060 |
|
|
Aug 25 06:27:45 AM UTC 24 |
Aug 25 06:27:51 AM UTC 24 |
460468681 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2235514705 |
|
|
Aug 25 06:27:47 AM UTC 24 |
Aug 25 06:27:52 AM UTC 24 |
371265903 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1401003942 |
|
|
Aug 25 06:27:47 AM UTC 24 |
Aug 25 06:27:53 AM UTC 24 |
1246377105 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1357252422 |
|
|
Aug 25 06:27:50 AM UTC 24 |
Aug 25 06:27:54 AM UTC 24 |
263036611 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1924472987 |
|
|
Aug 25 06:27:51 AM UTC 24 |
Aug 25 06:27:57 AM UTC 24 |
2006324733 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.341381808 |
|
|
Aug 25 06:27:52 AM UTC 24 |
Aug 25 06:27:57 AM UTC 24 |
544381757 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.1855998149 |
|
|
Aug 25 06:26:32 AM UTC 24 |
Aug 25 06:27:57 AM UTC 24 |
39403941010 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.71487419 |
|
|
Aug 25 06:26:42 AM UTC 24 |
Aug 25 06:27:57 AM UTC 24 |
12999689727 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3264148303 |
|
|
Aug 25 06:27:55 AM UTC 24 |
Aug 25 06:27:57 AM UTC 24 |
26095103 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2011278688 |
|
|
Aug 25 06:27:52 AM UTC 24 |
Aug 25 06:27:58 AM UTC 24 |
458939753 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4253584459 |
|
|
Aug 25 06:27:51 AM UTC 24 |
Aug 25 06:27:58 AM UTC 24 |
2203142153 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2302592105 |
|
|
Aug 25 06:26:07 AM UTC 24 |
Aug 25 06:27:59 AM UTC 24 |
23568716046 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.325860377 |
|
|
Aug 25 06:27:50 AM UTC 24 |
Aug 25 06:28:00 AM UTC 24 |
266589807 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_override.2726483487 |
|
|
Aug 25 06:27:58 AM UTC 24 |
Aug 25 06:28:00 AM UTC 24 |
45959351 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.3866469300 |
|
|
Aug 25 06:27:58 AM UTC 24 |
Aug 25 06:28:01 AM UTC 24 |
348296690 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3715288957 |
|
|
Aug 25 06:23:30 AM UTC 24 |
Aug 25 06:28:01 AM UTC 24 |
39915370821 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.1089026288 |
|
|
Aug 25 06:28:01 AM UTC 24 |
Aug 25 06:28:05 AM UTC 24 |
210443635 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1935059899 |
|
|
Aug 25 06:25:20 AM UTC 24 |
Aug 25 06:28:09 AM UTC 24 |
5054431769 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2679403438 |
|
|
Aug 25 06:28:01 AM UTC 24 |
Aug 25 06:28:09 AM UTC 24 |
153664221 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2883314757 |
|
|
Aug 25 06:27:59 AM UTC 24 |
Aug 25 06:28:10 AM UTC 24 |
273963732 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2478334486 |
|
|
Aug 25 06:28:01 AM UTC 24 |
Aug 25 06:28:18 AM UTC 24 |
650321882 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.3360257581 |
|
|
Aug 25 06:27:58 AM UTC 24 |
Aug 25 06:28:18 AM UTC 24 |
4080047321 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4026446898 |
|
|
Aug 25 06:25:55 AM UTC 24 |
Aug 25 06:28:19 AM UTC 24 |
9164123896 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1649894792 |
|
|
Aug 25 06:28:19 AM UTC 24 |
Aug 25 06:28:29 AM UTC 24 |
9352049240 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1357661633 |
|
|
Aug 25 06:27:55 AM UTC 24 |
Aug 25 06:28:32 AM UTC 24 |
5656937313 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2207108967 |
|
|
Aug 25 06:24:39 AM UTC 24 |
Aug 25 06:28:32 AM UTC 24 |
12386554087 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.786468954 |
|
|
Aug 25 06:28:20 AM UTC 24 |
Aug 25 06:28:34 AM UTC 24 |
1575359037 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.4229866297 |
|
|
Aug 25 06:24:40 AM UTC 24 |
Aug 25 06:28:36 AM UTC 24 |
3474422969 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2712482308 |
|
|
Aug 25 06:27:18 AM UTC 24 |
Aug 25 06:28:36 AM UTC 24 |
4577457017 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1602770085 |
|
|
Aug 25 06:28:33 AM UTC 24 |
Aug 25 06:28:36 AM UTC 24 |
242523485 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.981772416 |
|
|
Aug 25 06:28:33 AM UTC 24 |
Aug 25 06:28:37 AM UTC 24 |
227849698 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3100935783 |
|
|
Aug 25 06:28:19 AM UTC 24 |
Aug 25 06:28:41 AM UTC 24 |
20250342763 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.29624053 |
|
|
Aug 25 06:25:40 AM UTC 24 |
Aug 25 06:28:42 AM UTC 24 |
63704520644 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_perf.1655007548 |
|
|
Aug 25 06:28:33 AM UTC 24 |
Aug 25 06:28:42 AM UTC 24 |
687208924 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.411979570 |
|
|
Aug 25 06:27:58 AM UTC 24 |
Aug 25 06:28:43 AM UTC 24 |
6126778245 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2839531478 |
|
|
Aug 25 06:27:06 AM UTC 24 |
Aug 25 06:33:04 AM UTC 24 |
60988123196 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.2760190961 |
|
|
Aug 25 06:28:42 AM UTC 24 |
Aug 25 06:28:45 AM UTC 24 |
512050598 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3326756208 |
|
|
Aug 25 06:28:38 AM UTC 24 |
Aug 25 06:28:45 AM UTC 24 |
317334349 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.947252369 |
|
|
Aug 25 06:28:43 AM UTC 24 |
Aug 25 06:28:47 AM UTC 24 |
68756312 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1344763255 |
|
|
Aug 25 06:28:41 AM UTC 24 |
Aug 25 06:28:47 AM UTC 24 |
1930994511 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1963111755 |
|
|
Aug 25 06:28:43 AM UTC 24 |
Aug 25 06:28:49 AM UTC 24 |
2387663219 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.1391014173 |
|
|
Aug 25 06:28:37 AM UTC 24 |
Aug 25 06:28:49 AM UTC 24 |
1093889619 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.307264216 |
|
|
Aug 25 06:28:44 AM UTC 24 |
Aug 25 06:28:49 AM UTC 24 |
1787489878 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_alert_test.236335515 |
|
|
Aug 25 06:28:47 AM UTC 24 |
Aug 25 06:28:50 AM UTC 24 |
16594385 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1092521764 |
|
|
Aug 25 06:28:46 AM UTC 24 |
Aug 25 06:28:50 AM UTC 24 |
132639740 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.735182489 |
|
|
Aug 25 06:28:12 AM UTC 24 |
Aug 25 06:28:51 AM UTC 24 |
2962869850 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3271956780 |
|
|
Aug 25 06:28:45 AM UTC 24 |
Aug 25 06:28:51 AM UTC 24 |
1147785654 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.3904254345 |
|
|
Aug 25 06:27:33 AM UTC 24 |
Aug 25 06:28:54 AM UTC 24 |
10852245924 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3691028325 |
|
|
Aug 25 06:27:41 AM UTC 24 |
Aug 25 06:28:57 AM UTC 24 |
73183263662 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.3579955752 |
|
|
Aug 25 06:28:06 AM UTC 24 |
Aug 25 06:28:59 AM UTC 24 |
1358749552 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1004777193 |
|
|
Aug 25 06:28:11 AM UTC 24 |
Aug 25 06:29:02 AM UTC 24 |
1665290723 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.109543575 |
|
|
Aug 25 06:27:17 AM UTC 24 |
Aug 25 06:29:08 AM UTC 24 |
9000055941 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2828779195 |
|
|
Aug 25 06:26:54 AM UTC 24 |
Aug 25 06:29:16 AM UTC 24 |
13218436441 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1804225370 |
|
|
Aug 25 06:27:17 AM UTC 24 |
Aug 25 06:29:16 AM UTC 24 |
8523179801 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.4170224557 |
|
|
Aug 25 06:26:45 AM UTC 24 |
Aug 25 06:29:18 AM UTC 24 |
2528029645 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1070644442 |
|
|
Aug 25 06:28:11 AM UTC 24 |
Aug 25 06:29:25 AM UTC 24 |
61772494417 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1320793278 |
|
|
Aug 25 06:26:42 AM UTC 24 |
Aug 25 06:29:29 AM UTC 24 |
2078619299 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_perf.2187360181 |
|
|
Aug 25 06:26:45 AM UTC 24 |
Aug 25 06:29:41 AM UTC 24 |
12642347418 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.4123135087 |
|
|
Aug 25 06:11:36 AM UTC 24 |
Aug 25 06:29:43 AM UTC 24 |
51529544887 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_stress_all.3812277044 |
|
|
Aug 25 06:26:06 AM UTC 24 |
Aug 25 06:29:54 AM UTC 24 |
23789939199 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3872627005 |
|
|
Aug 25 06:23:59 AM UTC 24 |
Aug 25 06:30:03 AM UTC 24 |
20011447850 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2242413660 |
|
|
Aug 25 06:27:58 AM UTC 24 |
Aug 25 06:30:19 AM UTC 24 |
20617138479 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2975030185 |
|
|
Aug 25 06:25:57 AM UTC 24 |
Aug 25 06:30:27 AM UTC 24 |
58886795986 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.2749695924 |
|
|
Aug 25 06:05:32 AM UTC 24 |
Aug 25 06:31:07 AM UTC 24 |
61455671894 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.602084564 |
|
|
Aug 25 06:27:59 AM UTC 24 |
Aug 25 06:31:23 AM UTC 24 |
22167564188 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.3408327602 |
|
|
Aug 25 06:13:44 AM UTC 24 |
Aug 25 06:31:31 AM UTC 24 |
24415725103 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_perf.3216454957 |
|
|
Aug 25 06:28:00 AM UTC 24 |
Aug 25 06:32:22 AM UTC 24 |
6669876548 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.1898805995 |
|
|
Aug 25 06:24:14 AM UTC 24 |
Aug 25 06:32:31 AM UTC 24 |
24006378160 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2487316536 |
|
|
Aug 25 06:24:10 AM UTC 24 |
Aug 25 06:32:58 AM UTC 24 |
53965644996 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.853934004 |
|
|
Aug 25 06:27:17 AM UTC 24 |
Aug 25 06:33:07 AM UTC 24 |
18949382652 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.982827446 |
|
|
Aug 25 06:26:21 AM UTC 24 |
Aug 25 06:35:34 AM UTC 24 |
22504126379 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_perf.3493823634 |
|
|
Aug 25 06:09:34 AM UTC 24 |
Aug 25 06:36:22 AM UTC 24 |
31256820960 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3315574116 |
|
|
Aug 25 06:28:34 AM UTC 24 |
Aug 25 06:37:12 AM UTC 24 |
55162793760 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.1709298561 |
|
|
Aug 25 06:16:44 AM UTC 24 |
Aug 25 06:37:43 AM UTC 24 |
52492581077 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2325120635 |
|
|
Aug 25 06:18:21 AM UTC 24 |
Aug 25 06:38:21 AM UTC 24 |
48425417660 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.3401045645 |
|
|
Aug 25 06:27:28 AM UTC 24 |
Aug 25 06:39:09 AM UTC 24 |
41800498967 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.3513457606 |
|
|
Aug 25 06:15:47 AM UTC 24 |
Aug 25 06:40:24 AM UTC 24 |
58120045610 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.3183067761 |
|
|
Aug 25 06:22:00 AM UTC 24 |
Aug 25 06:40:30 AM UTC 24 |
23230969336 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.276961096 |
|
|
Aug 25 06:24:23 AM UTC 24 |
Aug 25 06:40:45 AM UTC 24 |
74214587710 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.2461219512 |
|
|
Aug 25 06:26:49 AM UTC 24 |
Aug 25 06:41:22 AM UTC 24 |
69922938440 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.2078004716 |
|
|
Aug 25 06:21:46 AM UTC 24 |
Aug 25 06:43:12 AM UTC 24 |
69601575575 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2125171681 |
|
|
Aug 25 06:24:48 AM UTC 24 |
Aug 25 06:43:26 AM UTC 24 |
50768946546 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.1810537383 |
|
|
Aug 25 06:03:16 AM UTC 24 |
Aug 25 06:43:28 AM UTC 24 |
69546094782 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2766709392 |
|
|
Aug 25 06:10:48 AM UTC 24 |
Aug 25 06:49:16 AM UTC 24 |
51263700701 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_stress_all.2210581976 |
|
|
Aug 25 06:28:02 AM UTC 24 |
Aug 25 06:50:25 AM UTC 24 |
76945824724 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.1187312980 |
|
|
Aug 25 06:08:49 AM UTC 24 |
Aug 25 06:52:04 AM UTC 24 |
24361868283 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_stress_all.1076933619 |
|
|
Aug 25 06:18:00 AM UTC 24 |
Aug 25 06:52:15 AM UTC 24 |
23617072336 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_perf.1042863521 |
|
|
Aug 25 06:20:41 AM UTC 24 |
Aug 25 06:55:45 AM UTC 24 |
50012316630 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.207591721 |
|
|
Aug 25 06:18:42 AM UTC 24 |
Aug 25 07:10:20 AM UTC 24 |
86308453554 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3124026415 |
|
|
Aug 25 06:28:50 AM UTC 24 |
Aug 25 06:28:52 AM UTC 24 |
42632554 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3219266542 |
|
|
Aug 25 06:28:48 AM UTC 24 |
Aug 25 06:28:52 AM UTC 24 |
478675216 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2510003464 |
|
|
Aug 25 06:28:51 AM UTC 24 |
Aug 25 06:28:53 AM UTC 24 |
17065001 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3027344864 |
|
|
Aug 25 06:28:51 AM UTC 24 |
Aug 25 06:28:53 AM UTC 24 |
62176410 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1424634470 |
|
|
Aug 25 06:28:50 AM UTC 24 |
Aug 25 06:28:54 AM UTC 24 |
532721531 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1025808197 |
|
|
Aug 25 06:28:52 AM UTC 24 |
Aug 25 06:28:54 AM UTC 24 |
51541982 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1425709400 |
|
|
Aug 25 06:28:51 AM UTC 24 |
Aug 25 06:28:55 AM UTC 24 |
66445886 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.863256384 |
|
|
Aug 25 06:28:53 AM UTC 24 |
Aug 25 06:28:56 AM UTC 24 |
26321193 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3870397089 |
|
|
Aug 25 06:28:52 AM UTC 24 |
Aug 25 06:28:56 AM UTC 24 |
69961161 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.227766546 |
|
|
Aug 25 06:28:54 AM UTC 24 |
Aug 25 06:28:56 AM UTC 24 |
18545457 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.275039009 |
|
|
Aug 25 06:28:53 AM UTC 24 |
Aug 25 06:28:57 AM UTC 24 |
108815068 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.987611780 |
|
|
Aug 25 06:28:56 AM UTC 24 |
Aug 25 06:28:58 AM UTC 24 |
20541287 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3226628629 |
|
|
Aug 25 06:28:56 AM UTC 24 |
Aug 25 06:28:58 AM UTC 24 |
17949464 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1578405521 |
|
|
Aug 25 06:28:54 AM UTC 24 |
Aug 25 06:28:59 AM UTC 24 |
1906023366 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1623466194 |
|
|
Aug 25 06:28:56 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
93297414 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.619995529 |
|
|
Aug 25 06:28:57 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
98415522 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.139384223 |
|
|
Aug 25 06:28:57 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
42305974 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2832481421 |
|
|
Aug 25 06:28:58 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
23373952 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1352900977 |
|
|
Aug 25 06:28:58 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
22649100 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.837399811 |
|
|
Aug 25 06:28:58 AM UTC 24 |
Aug 25 06:29:00 AM UTC 24 |
57082907 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.2025495916 |
|
|
Aug 25 06:28:57 AM UTC 24 |
Aug 25 06:29:01 AM UTC 24 |
795387476 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1432841700 |
|
|
Aug 25 06:29:00 AM UTC 24 |
Aug 25 06:29:02 AM UTC 24 |
61282493 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3164944858 |
|
|
Aug 25 06:28:57 AM UTC 24 |
Aug 25 06:29:02 AM UTC 24 |
114030168 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3870209227 |
|
|
Aug 25 06:28:56 AM UTC 24 |
Aug 25 06:29:03 AM UTC 24 |
429327842 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3385164906 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:03 AM UTC 24 |
23344286 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.339372369 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:03 AM UTC 24 |
52750556 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.958013704 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:03 AM UTC 24 |
48777489 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3522030607 |
|
|
Aug 25 06:28:59 AM UTC 24 |
Aug 25 06:29:03 AM UTC 24 |
1501599084 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4201823964 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:04 AM UTC 24 |
45911059 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3998568921 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:05 AM UTC 24 |
715661928 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.241473092 |
|
|
Aug 25 06:29:02 AM UTC 24 |
Aug 25 06:29:05 AM UTC 24 |
117137228 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.2500986351 |
|
|
Aug 25 06:29:02 AM UTC 24 |
Aug 25 06:29:05 AM UTC 24 |
150202026 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3406851853 |
|
|
Aug 25 06:28:58 AM UTC 24 |
Aug 25 06:29:05 AM UTC 24 |
1038861787 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3801178229 |
|
|
Aug 25 06:29:01 AM UTC 24 |
Aug 25 06:29:05 AM UTC 24 |
700181215 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3160590588 |
|
|
Aug 25 06:29:03 AM UTC 24 |
Aug 25 06:29:06 AM UTC 24 |
21138101 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3779348800 |
|
|
Aug 25 06:29:05 AM UTC 24 |
Aug 25 06:29:07 AM UTC 24 |
92910141 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3875354151 |
|
|
Aug 25 06:29:05 AM UTC 24 |
Aug 25 06:29:07 AM UTC 24 |
27067913 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.739019571 |
|
|
Aug 25 06:29:05 AM UTC 24 |
Aug 25 06:29:07 AM UTC 24 |
44520622 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.3776589196 |
|
|
Aug 25 06:29:17 AM UTC 24 |
Aug 25 06:29:19 AM UTC 24 |
28349130 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.937237658 |
|
|
Aug 25 06:29:03 AM UTC 24 |
Aug 25 06:29:08 AM UTC 24 |
90808192 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3087348153 |
|
|
Aug 25 06:29:04 AM UTC 24 |
Aug 25 06:29:08 AM UTC 24 |
249702940 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3201859852 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:09 AM UTC 24 |
76021232 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3054717544 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:09 AM UTC 24 |
80202869 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.416087112 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:09 AM UTC 24 |
42234761 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3765841450 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:09 AM UTC 24 |
114331713 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.316204400 |
|
|
Aug 25 06:29:08 AM UTC 24 |
Aug 25 06:29:10 AM UTC 24 |
38152692 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4096963068 |
|
|
Aug 25 06:29:08 AM UTC 24 |
Aug 25 06:29:10 AM UTC 24 |
135791556 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.4235312047 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:10 AM UTC 24 |
143710218 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.595176604 |
|
|
Aug 25 06:29:08 AM UTC 24 |
Aug 25 06:29:10 AM UTC 24 |
45415333 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.633858309 |
|
|
Aug 25 06:29:06 AM UTC 24 |
Aug 25 06:29:10 AM UTC 24 |
125368342 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1117446464 |
|
|
Aug 25 06:29:02 AM UTC 24 |
Aug 25 06:29:11 AM UTC 24 |
766965098 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3722173117 |
|
|
Aug 25 06:29:09 AM UTC 24 |
Aug 25 06:29:11 AM UTC 24 |
123859283 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2387398985 |
|
|
Aug 25 06:29:09 AM UTC 24 |
Aug 25 06:29:11 AM UTC 24 |
26194145 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.911891651 |
|
|
Aug 25 06:29:09 AM UTC 24 |
Aug 25 06:29:12 AM UTC 24 |
24889855 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1637730777 |
|
|
Aug 25 06:29:11 AM UTC 24 |
Aug 25 06:29:13 AM UTC 24 |
16665530 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1467230037 |
|
|
Aug 25 06:29:11 AM UTC 24 |
Aug 25 06:29:13 AM UTC 24 |
19444351 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1441214918 |
|
|
Aug 25 06:29:05 AM UTC 24 |
Aug 25 06:29:13 AM UTC 24 |
1297548985 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.496536285 |
|
|
Aug 25 06:29:09 AM UTC 24 |
Aug 25 06:29:13 AM UTC 24 |
266328032 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1280198787 |
|
|
Aug 25 06:29:09 AM UTC 24 |
Aug 25 06:29:14 AM UTC 24 |
615280431 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1669474996 |
|
|
Aug 25 06:29:10 AM UTC 24 |
Aug 25 06:29:14 AM UTC 24 |
44869385 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.692110188 |
|
|
Aug 25 06:29:12 AM UTC 24 |
Aug 25 06:29:14 AM UTC 24 |
141553258 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3714253886 |
|
|
Aug 25 06:29:12 AM UTC 24 |
Aug 25 06:29:14 AM UTC 24 |
23564936 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3236117642 |
|
|
Aug 25 06:29:12 AM UTC 24 |
Aug 25 06:29:15 AM UTC 24 |
76945481 ps |