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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.23 97.21 89.46 97.22 72.02 94.26 98.44 90.00


Total test records in report: 1852
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T220 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3510159789 Aug 25 06:29:11 AM UTC 24 Aug 25 06:29:15 AM UTC 24 1018160033 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.1758394117 Aug 25 06:29:10 AM UTC 24 Aug 25 06:29:15 AM UTC 24 195087121 ps
T1763 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1079467984 Aug 25 06:29:12 AM UTC 24 Aug 25 06:29:15 AM UTC 24 176150978 ps
T1764 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.277766614 Aug 25 06:29:12 AM UTC 24 Aug 25 06:29:15 AM UTC 24 75222924 ps
T1765 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2165051480 Aug 25 06:29:13 AM UTC 24 Aug 25 06:29:15 AM UTC 24 71552789 ps
T1766 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2899228252 Aug 25 06:29:13 AM UTC 24 Aug 25 06:29:16 AM UTC 24 45737493 ps
T1767 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1060090878 Aug 25 06:29:13 AM UTC 24 Aug 25 06:29:16 AM UTC 24 214308897 ps
T1768 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.4063034198 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:17 AM UTC 24 110117866 ps
T1769 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3109334107 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:17 AM UTC 24 19281833 ps
T1770 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1333007716 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:17 AM UTC 24 173483797 ps
T1771 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2606830761 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:18 AM UTC 24 144476240 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2024586236 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:19 AM UTC 24 336938553 ps
T1772 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.3022375298 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:19 AM UTC 24 73051618 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2493525176 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:19 AM UTC 24 28204168 ps
T1773 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.520211049 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:20 AM UTC 24 45069898 ps
T1774 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3910684320 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:20 AM UTC 24 194152628 ps
T1775 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.1903894025 Aug 25 06:29:15 AM UTC 24 Aug 25 06:29:20 AM UTC 24 142854026 ps
T1776 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.967969133 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:20 AM UTC 24 250339905 ps
T1777 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.222432792 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:20 AM UTC 24 200764374 ps
T1778 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3409701763 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:22 AM UTC 24 68344027 ps
T1779 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.4014271507 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:21 AM UTC 24 162965346 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1597018066 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:21 AM UTC 24 78932493 ps
T1780 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.820957688 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:21 AM UTC 24 16324438 ps
T1781 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2111400399 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:21 AM UTC 24 72348589 ps
T1782 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.457809506 Aug 25 06:29:17 AM UTC 24 Aug 25 06:29:22 AM UTC 24 49433051 ps
T1783 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.723372719 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:22 AM UTC 24 107842707 ps
T1784 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1564616146 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:23 AM UTC 24 53412186 ps
T1785 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.2246674180 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:23 AM UTC 24 43250417 ps
T1786 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.2393682480 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:23 AM UTC 24 25533600 ps
T1787 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2920621870 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:23 AM UTC 24 48240890 ps
T1788 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3155455735 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:24 AM UTC 24 390792539 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3314502113 Aug 25 06:29:19 AM UTC 24 Aug 25 06:29:24 AM UTC 24 530446663 ps
T1789 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2537081209 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:24 AM UTC 24 51304516 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.1025653086 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:25 AM UTC 24 78979998 ps
T1790 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2859617727 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:25 AM UTC 24 34132874 ps
T1791 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2282687552 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:25 AM UTC 24 108209882 ps
T1792 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.772501379 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:25 AM UTC 24 36287950 ps
T1793 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1371168090 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:25 AM UTC 24 111180816 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.2938349927 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:26 AM UTC 24 262997743 ps
T1794 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.3096800268 Aug 25 06:29:21 AM UTC 24 Aug 25 06:29:26 AM UTC 24 270856590 ps
T1795 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1406264987 Aug 25 06:29:23 AM UTC 24 Aug 25 06:29:27 AM UTC 24 71595662 ps
T1796 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2091041454 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:28 AM UTC 24 28124888 ps
T1797 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3451726904 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:28 AM UTC 24 28883941 ps
T1798 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3723882847 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:28 AM UTC 24 64583912 ps
T1799 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1362974404 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:28 AM UTC 24 18531011 ps
T1800 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.265786794 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:28 AM UTC 24 106107618 ps
T1801 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.1007557251 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:29 AM UTC 24 85377468 ps
T1802 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.4141548292 Aug 25 06:29:25 AM UTC 24 Aug 25 06:29:29 AM UTC 24 48562412 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.492964989 Aug 25 06:29:26 AM UTC 24 Aug 25 06:29:29 AM UTC 24 68768797 ps
T1803 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.4062905547 Aug 25 06:29:26 AM UTC 24 Aug 25 06:29:30 AM UTC 24 236731480 ps
T1804 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2432763292 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 49938645 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2328389275 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 77857467 ps
T1805 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.310035862 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 39630008 ps
T1806 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1228954846 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 20626644 ps
T1807 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4207643575 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 121572896 ps
T1808 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.2046549485 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:30 AM UTC 24 121335498 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3667502730 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:32 AM UTC 24 138901192 ps
T1809 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1658158926 Aug 25 06:29:28 AM UTC 24 Aug 25 06:29:33 AM UTC 24 46338749 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2352273142 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:33 AM UTC 24 34135896 ps
T1810 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.4256443990 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:34 AM UTC 24 18592080 ps
T1811 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.4091867583 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:34 AM UTC 24 41354780 ps
T1812 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.181871720 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:34 AM UTC 24 111987991 ps
T1813 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2141563802 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:34 AM UTC 24 34535073 ps
T1814 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2838027918 Aug 25 06:29:30 AM UTC 24 Aug 25 06:29:34 AM UTC 24 124281559 ps
T1815 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1158596748 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:35 AM UTC 24 128736302 ps
T1816 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.800004663 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:35 AM UTC 24 321838727 ps
T1817 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2894175398 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:35 AM UTC 24 39688841 ps
T1818 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1134296965 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:35 AM UTC 24 39712436 ps
T1819 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.2835012957 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:35 AM UTC 24 48476679 ps
T1820 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.3152338969 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:35 AM UTC 24 39479477 ps
T1821 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2112277076 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:35 AM UTC 24 17778511 ps
T1822 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.515251442 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:36 AM UTC 24 97029077 ps
T1823 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.2744565230 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:36 AM UTC 24 36308076 ps
T1824 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2859379086 Aug 25 06:29:33 AM UTC 24 Aug 25 06:29:36 AM UTC 24 86082620 ps
T1825 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1890776903 Aug 25 06:29:31 AM UTC 24 Aug 25 06:29:36 AM UTC 24 489748134 ps
T1826 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.267585349 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:37 AM UTC 24 25434431 ps
T1827 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.3266442955 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 18698019 ps
T1828 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.2814522739 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 44035188 ps
T1829 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.527153984 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 24857071 ps
T1830 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.2954712935 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 28999832 ps
T1831 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.4250474135 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 45015860 ps
T1832 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1578076471 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 19989547 ps
T1833 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2256902405 Aug 25 06:29:35 AM UTC 24 Aug 25 06:29:38 AM UTC 24 45387663 ps
T1834 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.826124088 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 40963912 ps
T1835 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.1625447041 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 60185282 ps
T1836 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2825136573 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 21676003 ps
T1837 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.286501379 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 42594838 ps
T1838 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.3065404765 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 20423592 ps
T1839 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3724700022 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:41 AM UTC 24 34653038 ps
T1840 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.230162725 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:42 AM UTC 24 18934100 ps
T1841 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.1147883292 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:42 AM UTC 24 40960476 ps
T1842 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.3054947704 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:42 AM UTC 24 19068154 ps
T1843 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.254699885 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:42 AM UTC 24 36735478 ps
T1844 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.3235397455 Aug 25 06:29:39 AM UTC 24 Aug 25 06:29:42 AM UTC 24 15739408 ps
T1845 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2300958141 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 47018424 ps
T1846 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.3460177123 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 29703301 ps
T1847 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.711209719 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 16934146 ps
T1848 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3889251583 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 25999295 ps
T1849 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.2331461017 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 28802080 ps
T1850 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2401693940 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 33684800 ps
T1851 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.2320255049 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 19513830 ps
T1852 /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.313605879 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:42 AM UTC 24 49324466 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.2488766535
Short name T7
Test name
Test status
Simulation time 611773652 ps
CPU time 2.32 seconds
Started Aug 25 05:55:32 AM UTC 24
Finished Aug 25 05:55:35 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488766
535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.2488766535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3870748257
Short name T19
Test name
Test status
Simulation time 738290884 ps
CPU time 8.66 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:55:00 AM UTC 24
Peak memory 230968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870748257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3870748257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.3581845678
Short name T49
Test name
Test status
Simulation time 9834870697 ps
CPU time 18.09 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:55:09 AM UTC 24
Peak memory 227464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581845678 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3581845678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_stress_all.4126415408
Short name T134
Test name
Test status
Simulation time 36484939379 ps
CPU time 185.44 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 06:01:11 AM UTC 24
Peak memory 710888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126415408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.4126415408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.275039009
Short name T109
Test name
Test status
Simulation time 108815068 ps
CPU time 2.89 seconds
Started Aug 25 06:28:53 AM UTC 24
Finished Aug 25 06:28:57 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275039009 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.275039009
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.1463653817
Short name T3
Test name
Test status
Simulation time 301131447 ps
CPU time 3.68 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:54:55 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463653817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1463653817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.220634831
Short name T58
Test name
Test status
Simulation time 589450029 ps
CPU time 2.51 seconds
Started Aug 25 05:54:56 AM UTC 24
Finished Aug 25 05:54:59 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206348
31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_txstretch.220634831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.3752487048
Short name T34
Test name
Test status
Simulation time 2770925620 ps
CPU time 177.06 seconds
Started Aug 25 05:54:48 AM UTC 24
Finished Aug 25 05:57:49 AM UTC 24
Peak memory 897256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752487048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3752487048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.4109762362
Short name T12
Test name
Test status
Simulation time 794707547 ps
CPU time 12.79 seconds
Started Aug 25 05:54:53 AM UTC 24
Finished Aug 25 05:55:07 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109762362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.4109762362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1606656427
Short name T74
Test name
Test status
Simulation time 5989118660 ps
CPU time 12.16 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:55:05 AM UTC 24
Peak memory 233672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606656
427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.1606656427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_override.2354330120
Short name T1
Test name
Test status
Simulation time 46842927 ps
CPU time 1.08 seconds
Started Aug 25 05:54:48 AM UTC 24
Finished Aug 25 05:54:50 AM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354330120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2354330120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1997184466
Short name T75
Test name
Test status
Simulation time 354945948 ps
CPU time 1.17 seconds
Started Aug 25 05:54:56 AM UTC 24
Finished Aug 25 05:54:58 AM UTC 24
Peak memory 246856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997184466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1997184466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.172943605
Short name T46
Test name
Test status
Simulation time 2134631038 ps
CPU time 3.65 seconds
Started Aug 25 05:58:30 AM UTC 24
Finished Aug 25 05:58:35 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729436
05 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.172943605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.3776589196
Short name T304
Test name
Test status
Simulation time 28349130 ps
CPU time 0.95 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:19 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776589196 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3776589196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.958013704
Short name T234
Test name
Test status
Simulation time 48777489 ps
CPU time 1.13 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:03 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958013704 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.958013704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.1605703443
Short name T226
Test name
Test status
Simulation time 14232729465 ps
CPU time 127.96 seconds
Started Aug 25 05:57:36 AM UTC 24
Finished Aug 25 05:59:46 AM UTC 24
Peak memory 1345752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160570
3443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.1605703443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.2852624027
Short name T64
Test name
Test status
Simulation time 2712526908 ps
CPU time 11.6 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:55:05 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2852624027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2852624027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.1478641486
Short name T61
Test name
Test status
Simulation time 6045630694 ps
CPU time 4.34 seconds
Started Aug 25 05:54:56 AM UTC 24
Finished Aug 25 05:55:01 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478641
486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.1478641486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1578405521
Short name T208
Test name
Test status
Simulation time 1906023366 ps
CPU time 3.35 seconds
Started Aug 25 06:28:54 AM UTC 24
Finished Aug 25 06:28:59 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578405521 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1578405521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_stress_all.4082198984
Short name T24
Test name
Test status
Simulation time 74944972929 ps
CPU time 402.36 seconds
Started Aug 25 05:55:52 AM UTC 24
Finished Aug 25 06:02:41 AM UTC 24
Peak memory 1213028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082198984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.4082198984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_stress_all.2634886559
Short name T306
Test name
Test status
Simulation time 8499810617 ps
CPU time 397.35 seconds
Started Aug 25 06:10:57 AM UTC 24
Finished Aug 25 06:17:40 AM UTC 24
Peak memory 2193620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634886559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2634886559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.3874720428
Short name T11
Test name
Test status
Simulation time 163549010 ps
CPU time 5.91 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:54:57 AM UTC 24
Peak memory 244004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874720428 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.3874720428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2535528635
Short name T52
Test name
Test status
Simulation time 919217669 ps
CPU time 4 seconds
Started Aug 25 06:02:15 AM UTC 24
Finished Aug 25 06:02:20 AM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535528
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.2535528635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.457226963
Short name T25
Test name
Test status
Simulation time 1205472754 ps
CPU time 9.19 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:55:00 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457226963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.457226963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.3795794319
Short name T257
Test name
Test status
Simulation time 83796770 ps
CPU time 1.54 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:55:54 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795794319 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.3795794319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.3096738218
Short name T121
Test name
Test status
Simulation time 26069263762 ps
CPU time 298.42 seconds
Started Aug 25 06:04:01 AM UTC 24
Finished Aug 25 06:09:05 AM UTC 24
Peak memory 1726748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096738218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.3096738218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_alert_test.1203407609
Short name T100
Test name
Test status
Simulation time 32540769 ps
CPU time 0.95 seconds
Started Aug 25 05:54:57 AM UTC 24
Finished Aug 25 05:54:59 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203407609 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1203407609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_override.1756023609
Short name T152
Test name
Test status
Simulation time 30923877 ps
CPU time 1.11 seconds
Started Aug 25 06:10:45 AM UTC 24
Finished Aug 25 06:10:48 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756023609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1756023609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.2384155361
Short name T45
Test name
Test status
Simulation time 936408072 ps
CPU time 2.26 seconds
Started Aug 25 05:54:53 AM UTC 24
Finished Aug 25 05:54:57 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384155
361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark
s_acq.2384155361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.710034023
Short name T267
Test name
Test status
Simulation time 1022386496 ps
CPU time 12.43 seconds
Started Aug 25 05:56:59 AM UTC 24
Finished Aug 25 05:57:13 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710034023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.710034023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.1046756070
Short name T21
Test name
Test status
Simulation time 152664154 ps
CPU time 5.59 seconds
Started Aug 25 05:55:23 AM UTC 24
Finished Aug 25 05:55:30 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046756070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1046756070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_stress_all.449932107
Short name T199
Test name
Test status
Simulation time 52680150020 ps
CPU time 413.38 seconds
Started Aug 25 05:59:13 AM UTC 24
Finished Aug 25 06:06:12 AM UTC 24
Peak memory 659816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449932107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.449932107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_mode_toggle.1718068602
Short name T289
Test name
Test status
Simulation time 139154090 ps
CPU time 5.9 seconds
Started Aug 25 06:03:41 AM UTC 24
Finished Aug 25 06:03:48 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718068602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1718068602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3870397089
Short name T230
Test name
Test status
Simulation time 69961161 ps
CPU time 2.69 seconds
Started Aug 25 06:28:52 AM UTC 24
Finished Aug 25 06:28:56 AM UTC 24
Peak memory 215156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870397089 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3870397089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1588679381
Short name T88
Test name
Test status
Simulation time 1717360031 ps
CPU time 34.35 seconds
Started Aug 25 06:00:20 AM UTC 24
Finished Aug 25 06:00:56 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588679381 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.1588679381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_perf.3721295300
Short name T39
Test name
Test status
Simulation time 630576309 ps
CPU time 32.72 seconds
Started Aug 25 06:06:10 AM UTC 24
Finished Aug 25 06:06:44 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721295300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3721295300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.716353856
Short name T287
Test name
Test status
Simulation time 5225435106 ps
CPU time 66.7 seconds
Started Aug 25 05:54:51 AM UTC 24
Finished Aug 25 05:56:00 AM UTC 24
Peak memory 231096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716353856 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.716353856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.3434826721
Short name T261
Test name
Test status
Simulation time 189343344 ps
CPU time 1.27 seconds
Started Aug 25 06:01:37 AM UTC 24
Finished Aug 25 06:01:39 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434826721 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.3434826721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.821938688
Short name T293
Test name
Test status
Simulation time 50414356742 ps
CPU time 100.08 seconds
Started Aug 25 06:02:01 AM UTC 24
Finished Aug 25 06:03:43 AM UTC 24
Peak memory 342292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821938
688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.821938688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.130116350
Short name T14
Test name
Test status
Simulation time 343981402 ps
CPU time 6.67 seconds
Started Aug 25 05:55:41 AM UTC 24
Finished Aug 25 05:55:49 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130116350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.130116350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.3111186234
Short name T252
Test name
Test status
Simulation time 288500059 ps
CPU time 1.99 seconds
Started Aug 25 06:07:47 AM UTC 24
Finished Aug 25 06:07:50 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111186
234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.3111186234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.126852600
Short name T262
Test name
Test status
Simulation time 235579496 ps
CPU time 1.67 seconds
Started Aug 25 06:16:17 AM UTC 24
Finished Aug 25 06:16:19 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126852600 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.126852600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3667502730
Short name T218
Test name
Test status
Simulation time 138901192 ps
CPU time 3.37 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:32 AM UTC 24
Peak memory 215064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667502730 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3667502730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3314502113
Short name T292
Test name
Test status
Simulation time 530446663 ps
CPU time 3.58 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:24 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314502113 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3314502113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.1758231780
Short name T298
Test name
Test status
Simulation time 47760242704 ps
CPU time 551.48 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 06:04:11 AM UTC 24
Peak memory 5196120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175823
1780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.1758231780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.970464201
Short name T70
Test name
Test status
Simulation time 71635952 ps
CPU time 2.16 seconds
Started Aug 25 05:54:55 AM UTC 24
Finished Aug 25 05:54:58 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9704642
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.970464201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.2377852394
Short name T314
Test name
Test status
Simulation time 422085081 ps
CPU time 21.91 seconds
Started Aug 25 06:00:16 AM UTC 24
Finished Aug 25 06:00:39 AM UTC 24
Peak memory 284740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377852394 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.2377852394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.3805306767
Short name T275
Test name
Test status
Simulation time 1533205826 ps
CPU time 17.63 seconds
Started Aug 25 06:01:24 AM UTC 24
Finished Aug 25 06:01:43 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805306767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3805306767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.2405919522
Short name T281
Test name
Test status
Simulation time 1333293306 ps
CPU time 12.43 seconds
Started Aug 25 06:04:26 AM UTC 24
Finished Aug 25 06:04:40 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405919522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2405919522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.2749695924
Short name T265
Test name
Test status
Simulation time 61455671894 ps
CPU time 1514.3 seconds
Started Aug 25 06:05:32 AM UTC 24
Finished Aug 25 06:31:07 AM UTC 24
Peak memory 2277540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749695924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2749695924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.4266036137
Short name T184
Test name
Test status
Simulation time 187839280 ps
CPU time 2.28 seconds
Started Aug 25 05:56:07 AM UTC 24
Finished Aug 25 05:56:10 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266036
137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.4266036137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.4119555816
Short name T272
Test name
Test status
Simulation time 3893578253 ps
CPU time 23.52 seconds
Started Aug 25 06:16:51 AM UTC 24
Finished Aug 25 06:17:15 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119555816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.4119555816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.2515066186
Short name T541
Test name
Test status
Simulation time 11516102236 ps
CPU time 77.43 seconds
Started Aug 25 06:01:13 AM UTC 24
Finished Aug 25 06:02:32 AM UTC 24
Peak memory 1157536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2515066186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres
s_wr.2515066186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3087348153
Short name T215
Test name
Test status
Simulation time 249702940 ps
CPU time 3.67 seconds
Started Aug 25 06:29:04 AM UTC 24
Finished Aug 25 06:29:08 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087348153 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3087348153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.317166281
Short name T18
Test name
Test status
Simulation time 227263365 ps
CPU time 3.11 seconds
Started Aug 25 05:55:01 AM UTC 24
Finished Aug 25 05:55:05 AM UTC 24
Peak memory 233728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317166281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.317166281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.139384223
Short name T212
Test name
Test status
Simulation time 42305974 ps
CPU time 1.76 seconds
Started Aug 25 06:28:57 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=139384223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.139384223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.2025495916
Short name T209
Test name
Test status
Simulation time 795387476 ps
CPU time 3.09 seconds
Started Aug 25 06:28:57 AM UTC 24
Finished Aug 25 06:29:01 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025495916 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2025495916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_mode_toggle.2016276336
Short name T10
Test name
Test status
Simulation time 62043214 ps
CPU time 1.97 seconds
Started Aug 25 05:54:53 AM UTC 24
Finished Aug 25 05:54:56 AM UTC 24
Peak memory 216452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016276336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2016276336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.1809196865
Short name T470
Test name
Test status
Simulation time 846943383 ps
CPU time 2.97 seconds
Started Aug 25 06:00:40 AM UTC 24
Finished Aug 25 06:00:45 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809196
865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.1809196865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.1162179
Short name T80
Test name
Test status
Simulation time 247185662 ps
CPU time 2.89 seconds
Started Aug 25 06:24:26 AM UTC 24
Finished Aug 25 06:24:29 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos
t_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1162179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1425709400
Short name T238
Test name
Test status
Simulation time 66445886 ps
CPU time 3.43 seconds
Started Aug 25 06:28:51 AM UTC 24
Finished Aug 25 06:28:55 AM UTC 24
Peak memory 215188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425709400 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1425709400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2510003464
Short name T223
Test name
Test status
Simulation time 17065001 ps
CPU time 1.15 seconds
Started Aug 25 06:28:51 AM UTC 24
Finished Aug 25 06:28:53 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510003464 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2510003464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.863256384
Short name T202
Test name
Test status
Simulation time 26321193 ps
CPU time 1.48 seconds
Started Aug 25 06:28:53 AM UTC 24
Finished Aug 25 06:28:56 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=863256384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.863256384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3027344864
Short name T224
Test name
Test status
Simulation time 62176410 ps
CPU time 1.15 seconds
Started Aug 25 06:28:51 AM UTC 24
Finished Aug 25 06:28:53 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027344864 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3027344864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3124026415
Short name T305
Test name
Test status
Simulation time 42632554 ps
CPU time 1.09 seconds
Started Aug 25 06:28:50 AM UTC 24
Finished Aug 25 06:28:52 AM UTC 24
Peak memory 214364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124026415 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3124026415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1025808197
Short name T245
Test name
Test status
Simulation time 51541982 ps
CPU time 1.16 seconds
Started Aug 25 06:28:52 AM UTC 24
Finished Aug 25 06:28:54 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025808197 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.1025808197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3219266542
Short name T107
Test name
Test status
Simulation time 478675216 ps
CPU time 3.39 seconds
Started Aug 25 06:28:48 AM UTC 24
Finished Aug 25 06:28:52 AM UTC 24
Peak memory 215424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219266542 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3219266542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1424634470
Short name T108
Test name
Test status
Simulation time 532721531 ps
CPU time 3.38 seconds
Started Aug 25 06:28:50 AM UTC 24
Finished Aug 25 06:28:54 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424634470 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1424634470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1623466194
Short name T231
Test name
Test status
Simulation time 93297414 ps
CPU time 2.69 seconds
Started Aug 25 06:28:56 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623466194 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1623466194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3870209227
Short name T1752
Test name
Test status
Simulation time 429327842 ps
CPU time 5.82 seconds
Started Aug 25 06:28:56 AM UTC 24
Finished Aug 25 06:29:03 AM UTC 24
Peak memory 215204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870209227 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3870209227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3226628629
Short name T283
Test name
Test status
Simulation time 17949464 ps
CPU time 1.18 seconds
Started Aug 25 06:28:56 AM UTC 24
Finished Aug 25 06:28:58 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226628629 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3226628629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.987611780
Short name T110
Test name
Test status
Simulation time 20541287 ps
CPU time 1.12 seconds
Started Aug 25 06:28:56 AM UTC 24
Finished Aug 25 06:28:58 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987611780 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.987611780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.227766546
Short name T307
Test name
Test status
Simulation time 18545457 ps
CPU time 0.98 seconds
Started Aug 25 06:28:54 AM UTC 24
Finished Aug 25 06:28:56 AM UTC 24
Peak memory 214508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227766546 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.227766546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.619995529
Short name T246
Test name
Test status
Simulation time 98415522 ps
CPU time 1.65 seconds
Started Aug 25 06:28:57 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619995529 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.619995529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.520211049
Short name T1773
Test name
Test status
Simulation time 45069898 ps
CPU time 1.44 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:20 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=520211049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.520211049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.3022375298
Short name T1772
Test name
Test status
Simulation time 73051618 ps
CPU time 1.11 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:19 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022375298 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3022375298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3910684320
Short name T1774
Test name
Test status
Simulation time 194152628 ps
CPU time 1.64 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:20 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910684320 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.3910684320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.457809506
Short name T1782
Test name
Test status
Simulation time 49433051 ps
CPU time 4.22 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:22 AM UTC 24
Peak memory 225376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457809506 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.457809506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.967969133
Short name T1776
Test name
Test status
Simulation time 250339905 ps
CPU time 2.17 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:20 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967969133 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.967969133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3409701763
Short name T1778
Test name
Test status
Simulation time 68344027 ps
CPU time 1.48 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:22 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3409701763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3409701763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1597018066
Short name T241
Test name
Test status
Simulation time 78932493 ps
CPU time 1.24 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:21 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597018066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1597018066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2493525176
Short name T312
Test name
Test status
Simulation time 28204168 ps
CPU time 1.01 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:19 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493525176 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2493525176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2111400399
Short name T1781
Test name
Test status
Simulation time 72348589 ps
CPU time 1.34 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:21 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111400399 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.2111400399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.222432792
Short name T1777
Test name
Test status
Simulation time 200764374 ps
CPU time 1.96 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:20 AM UTC 24
Peak memory 214420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222432792 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.222432792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.4014271507
Short name T1779
Test name
Test status
Simulation time 162965346 ps
CPU time 2.27 seconds
Started Aug 25 06:29:17 AM UTC 24
Finished Aug 25 06:29:21 AM UTC 24
Peak memory 215160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014271507 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4014271507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2537081209
Short name T1789
Test name
Test status
Simulation time 51304516 ps
CPU time 1.86 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:24 AM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2537081209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2537081209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1564616146
Short name T1784
Test name
Test status
Simulation time 53412186 ps
CPU time 1.08 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:23 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564616146 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1564616146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.820957688
Short name T1780
Test name
Test status
Simulation time 16324438 ps
CPU time 0.99 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:21 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820957688 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.820957688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2920621870
Short name T1787
Test name
Test status
Simulation time 48240890 ps
CPU time 1.39 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:23 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920621870 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.2920621870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.723372719
Short name T1783
Test name
Test status
Simulation time 107842707 ps
CPU time 2.34 seconds
Started Aug 25 06:29:19 AM UTC 24
Finished Aug 25 06:29:22 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723372719 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.723372719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.772501379
Short name T1792
Test name
Test status
Simulation time 36287950 ps
CPU time 1.45 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 214620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=772501379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.772501379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.2246674180
Short name T1785
Test name
Test status
Simulation time 43250417 ps
CPU time 0.97 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:23 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246674180 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2246674180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.2393682480
Short name T1786
Test name
Test status
Simulation time 25533600 ps
CPU time 1.06 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:23 AM UTC 24
Peak memory 214400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393682480 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2393682480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3155455735
Short name T1788
Test name
Test status
Simulation time 390792539 ps
CPU time 1.25 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:24 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155455735 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.3155455735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.3096800268
Short name T1794
Test name
Test status
Simulation time 270856590 ps
CPU time 3.94 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:26 AM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096800268 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3096800268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.1025653086
Short name T216
Test name
Test status
Simulation time 78979998 ps
CPU time 2.48 seconds
Started Aug 25 06:29:21 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025653086 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1025653086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3451726904
Short name T1797
Test name
Test status
Simulation time 28883941 ps
CPU time 1.34 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:28 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3451726904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3451726904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2859617727
Short name T1790
Test name
Test status
Simulation time 34132874 ps
CPU time 1.04 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859617727 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2859617727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2282687552
Short name T1791
Test name
Test status
Simulation time 108209882 ps
CPU time 1.22 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282687552 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2282687552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1371168090
Short name T1793
Test name
Test status
Simulation time 111180816 ps
CPU time 1.34 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371168090 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.1371168090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1406264987
Short name T1795
Test name
Test status
Simulation time 71595662 ps
CPU time 2.94 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:27 AM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406264987 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1406264987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.2938349927
Short name T217
Test name
Test status
Simulation time 262997743 ps
CPU time 1.83 seconds
Started Aug 25 06:29:23 AM UTC 24
Finished Aug 25 06:29:26 AM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938349927 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2938349927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3723882847
Short name T1798
Test name
Test status
Simulation time 64583912 ps
CPU time 1.15 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:28 AM UTC 24
Peak memory 214812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3723882847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3723882847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1362974404
Short name T1799
Test name
Test status
Simulation time 18531011 ps
CPU time 1.22 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:28 AM UTC 24
Peak memory 214472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362974404 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1362974404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2091041454
Short name T1796
Test name
Test status
Simulation time 28124888 ps
CPU time 1.05 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:28 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091041454 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2091041454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.265786794
Short name T1800
Test name
Test status
Simulation time 106107618 ps
CPU time 1.33 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:28 AM UTC 24
Peak memory 214416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265786794 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.265786794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.4141548292
Short name T1802
Test name
Test status
Simulation time 48562412 ps
CPU time 1.86 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:29 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141548292 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4141548292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.1007557251
Short name T1801
Test name
Test status
Simulation time 85377468 ps
CPU time 1.89 seconds
Started Aug 25 06:29:25 AM UTC 24
Finished Aug 25 06:29:29 AM UTC 24
Peak memory 214704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007557251 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1007557251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4207643575
Short name T1807
Test name
Test status
Simulation time 121572896 ps
CPU time 1.49 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4207643575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4207643575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2328389275
Short name T243
Test name
Test status
Simulation time 77857467 ps
CPU time 1.14 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328389275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2328389275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2432763292
Short name T1804
Test name
Test status
Simulation time 49938645 ps
CPU time 0.92 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432763292 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2432763292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.310035862
Short name T1805
Test name
Test status
Simulation time 39630008 ps
CPU time 1.26 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310035862 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.310035862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.4062905547
Short name T1803
Test name
Test status
Simulation time 236731480 ps
CPU time 2.39 seconds
Started Aug 25 06:29:26 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 215208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062905547 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.4062905547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.492964989
Short name T221
Test name
Test status
Simulation time 68768797 ps
CPU time 1.91 seconds
Started Aug 25 06:29:26 AM UTC 24
Finished Aug 25 06:29:29 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492964989 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.492964989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.181871720
Short name T1812
Test name
Test status
Simulation time 111987991 ps
CPU time 1.48 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:34 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=181871720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.181871720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.2046549485
Short name T1808
Test name
Test status
Simulation time 121335498 ps
CPU time 1.27 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046549485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2046549485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1228954846
Short name T1806
Test name
Test status
Simulation time 20626644 ps
CPU time 1.08 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:30 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228954846 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1228954846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2838027918
Short name T1814
Test name
Test status
Simulation time 124281559 ps
CPU time 1.77 seconds
Started Aug 25 06:29:30 AM UTC 24
Finished Aug 25 06:29:34 AM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838027918 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.2838027918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1658158926
Short name T1809
Test name
Test status
Simulation time 46338749 ps
CPU time 3.78 seconds
Started Aug 25 06:29:28 AM UTC 24
Finished Aug 25 06:29:33 AM UTC 24
Peak memory 215300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658158926 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1658158926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2894175398
Short name T1817
Test name
Test status
Simulation time 39688841 ps
CPU time 2.33 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2894175398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2894175398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2352273142
Short name T244
Test name
Test status
Simulation time 34135896 ps
CPU time 1 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:33 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352273142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2352273142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.4256443990
Short name T1810
Test name
Test status
Simulation time 18592080 ps
CPU time 1 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:34 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256443990 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.4256443990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2141563802
Short name T1813
Test name
Test status
Simulation time 34535073 ps
CPU time 1.18 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:34 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141563802 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.2141563802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1890776903
Short name T1825
Test name
Test status
Simulation time 489748134 ps
CPU time 3.86 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:36 AM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890776903 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1890776903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.800004663
Short name T1816
Test name
Test status
Simulation time 321838727 ps
CPU time 2.29 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800004663 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.800004663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.515251442
Short name T1822
Test name
Test status
Simulation time 97029077 ps
CPU time 1.35 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:36 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=515251442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.515251442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.3152338969
Short name T1820
Test name
Test status
Simulation time 39479477 ps
CPU time 1.18 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152338969 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3152338969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.4091867583
Short name T1811
Test name
Test status
Simulation time 41354780 ps
CPU time 1.02 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:34 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091867583 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4091867583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2859379086
Short name T1824
Test name
Test status
Simulation time 86082620 ps
CPU time 1.56 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:36 AM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859379086 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.2859379086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.2744565230
Short name T1823
Test name
Test status
Simulation time 36308076 ps
CPU time 2.92 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:36 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744565230 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2744565230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1158596748
Short name T1815
Test name
Test status
Simulation time 128736302 ps
CPU time 1.89 seconds
Started Aug 25 06:29:31 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158596748 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1158596748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3522030607
Short name T111
Test name
Test status
Simulation time 1501599084 ps
CPU time 2.8 seconds
Started Aug 25 06:28:59 AM UTC 24
Finished Aug 25 06:29:03 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522030607 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3522030607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3406851853
Short name T1755
Test name
Test status
Simulation time 1038861787 ps
CPU time 5.71 seconds
Started Aug 25 06:28:58 AM UTC 24
Finished Aug 25 06:29:05 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406851853 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3406851853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2832481421
Short name T232
Test name
Test status
Simulation time 23373952 ps
CPU time 1.01 seconds
Started Aug 25 06:28:58 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832481421 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2832481421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4201823964
Short name T227
Test name
Test status
Simulation time 45911059 ps
CPU time 1.72 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:04 AM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4201823964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4201823964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.837399811
Short name T233
Test name
Test status
Simulation time 57082907 ps
CPU time 0.97 seconds
Started Aug 25 06:28:58 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837399811 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.837399811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1352900977
Short name T302
Test name
Test status
Simulation time 22649100 ps
CPU time 1.04 seconds
Started Aug 25 06:28:58 AM UTC 24
Finished Aug 25 06:29:00 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352900977 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1352900977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1432841700
Short name T247
Test name
Test status
Simulation time 61282493 ps
CPU time 1.01 seconds
Started Aug 25 06:29:00 AM UTC 24
Finished Aug 25 06:29:02 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432841700 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.1432841700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3164944858
Short name T211
Test name
Test status
Simulation time 114030168 ps
CPU time 4.33 seconds
Started Aug 25 06:28:57 AM UTC 24
Finished Aug 25 06:29:02 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164944858 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3164944858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.2835012957
Short name T1819
Test name
Test status
Simulation time 48476679 ps
CPU time 1.02 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835012957 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2835012957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1134296965
Short name T1818
Test name
Test status
Simulation time 39712436 ps
CPU time 0.93 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 214808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134296965 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1134296965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2112277076
Short name T1821
Test name
Test status
Simulation time 17778511 ps
CPU time 1.04 seconds
Started Aug 25 06:29:33 AM UTC 24
Finished Aug 25 06:29:35 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112277076 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2112277076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.2954712935
Short name T1830
Test name
Test status
Simulation time 28999832 ps
CPU time 1.05 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954712935 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2954712935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.3266442955
Short name T1827
Test name
Test status
Simulation time 18698019 ps
CPU time 0.99 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266442955 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3266442955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.2814522739
Short name T1828
Test name
Test status
Simulation time 44035188 ps
CPU time 0.94 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 213528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814522739 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2814522739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1578076471
Short name T1832
Test name
Test status
Simulation time 19989547 ps
CPU time 1.02 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578076471 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1578076471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.527153984
Short name T1829
Test name
Test status
Simulation time 24857071 ps
CPU time 0.81 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527153984 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.527153984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.267585349
Short name T1826
Test name
Test status
Simulation time 25434431 ps
CPU time 0.95 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:37 AM UTC 24
Peak memory 213308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267585349 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.267585349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.4250474135
Short name T1831
Test name
Test status
Simulation time 45015860 ps
CPU time 0.94 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250474135 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4250474135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.2500986351
Short name T1754
Test name
Test status
Simulation time 150202026 ps
CPU time 1.65 seconds
Started Aug 25 06:29:02 AM UTC 24
Finished Aug 25 06:29:05 AM UTC 24
Peak memory 214704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500986351 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2500986351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1117446464
Short name T239
Test name
Test status
Simulation time 766965098 ps
CPU time 7.39 seconds
Started Aug 25 06:29:02 AM UTC 24
Finished Aug 25 06:29:11 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117446464 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1117446464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.339372369
Short name T1753
Test name
Test status
Simulation time 52750556 ps
CPU time 1.06 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:03 AM UTC 24
Peak memory 214592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339372369 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.339372369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3160590588
Short name T228
Test name
Test status
Simulation time 21138101 ps
CPU time 1.31 seconds
Started Aug 25 06:29:03 AM UTC 24
Finished Aug 25 06:29:06 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3160590588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3160590588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3385164906
Short name T309
Test name
Test status
Simulation time 23344286 ps
CPU time 0.99 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:03 AM UTC 24
Peak memory 214524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385164906 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3385164906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.241473092
Short name T113
Test name
Test status
Simulation time 117137228 ps
CPU time 1.52 seconds
Started Aug 25 06:29:02 AM UTC 24
Finished Aug 25 06:29:05 AM UTC 24
Peak memory 214764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241473092 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.241473092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3998568921
Short name T112
Test name
Test status
Simulation time 715661928 ps
CPU time 2.9 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:05 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998568921 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3998568921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3801178229
Short name T114
Test name
Test status
Simulation time 700181215 ps
CPU time 3.41 seconds
Started Aug 25 06:29:01 AM UTC 24
Finished Aug 25 06:29:05 AM UTC 24
Peak memory 215188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801178229 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3801178229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2256902405
Short name T1833
Test name
Test status
Simulation time 45387663 ps
CPU time 1.04 seconds
Started Aug 25 06:29:35 AM UTC 24
Finished Aug 25 06:29:38 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256902405 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2256902405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.286501379
Short name T1837
Test name
Test status
Simulation time 42594838 ps
CPU time 1.14 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286501379 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.286501379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.826124088
Short name T1834
Test name
Test status
Simulation time 40963912 ps
CPU time 1.05 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826124088 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.826124088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.1625447041
Short name T1835
Test name
Test status
Simulation time 60185282 ps
CPU time 0.95 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625447041 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1625447041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2825136573
Short name T1836
Test name
Test status
Simulation time 21676003 ps
CPU time 0.9 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825136573 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2825136573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.3054947704
Short name T1842
Test name
Test status
Simulation time 19068154 ps
CPU time 1.12 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054947704 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3054947704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.3065404765
Short name T1838
Test name
Test status
Simulation time 20423592 ps
CPU time 1.03 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065404765 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3065404765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3724700022
Short name T1839
Test name
Test status
Simulation time 34653038 ps
CPU time 0.93 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724700022 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3724700022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.254699885
Short name T1843
Test name
Test status
Simulation time 36735478 ps
CPU time 1.01 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254699885 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.254699885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.230162725
Short name T1840
Test name
Test status
Simulation time 18934100 ps
CPU time 1.04 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230162725 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.230162725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.4235312047
Short name T237
Test name
Test status
Simulation time 143710218 ps
CPU time 2.78 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:10 AM UTC 24
Peak memory 215212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235312047 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.4235312047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1441214918
Short name T1760
Test name
Test status
Simulation time 1297548985 ps
CPU time 7.04 seconds
Started Aug 25 06:29:05 AM UTC 24
Finished Aug 25 06:29:13 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441214918 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1441214918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3875354151
Short name T115
Test name
Test status
Simulation time 27067913 ps
CPU time 1.18 seconds
Started Aug 25 06:29:05 AM UTC 24
Finished Aug 25 06:29:07 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875354151 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3875354151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3054717544
Short name T1757
Test name
Test status
Simulation time 80202869 ps
CPU time 1.23 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:09 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3054717544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3054717544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.739019571
Short name T235
Test name
Test status
Simulation time 44520622 ps
CPU time 1.19 seconds
Started Aug 25 06:29:05 AM UTC 24
Finished Aug 25 06:29:07 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739019571 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.739019571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3779348800
Short name T308
Test name
Test status
Simulation time 92910141 ps
CPU time 1.06 seconds
Started Aug 25 06:29:05 AM UTC 24
Finished Aug 25 06:29:07 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779348800 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3779348800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.416087112
Short name T248
Test name
Test status
Simulation time 42234761 ps
CPU time 1.54 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:09 AM UTC 24
Peak memory 214704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416087112 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.416087112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.937237658
Short name T213
Test name
Test status
Simulation time 90808192 ps
CPU time 3.33 seconds
Started Aug 25 06:29:03 AM UTC 24
Finished Aug 25 06:29:08 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937237658 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.937237658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.1147883292
Short name T1841
Test name
Test status
Simulation time 40960476 ps
CPU time 0.93 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147883292 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1147883292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.3235397455
Short name T1844
Test name
Test status
Simulation time 15739408 ps
CPU time 0.99 seconds
Started Aug 25 06:29:39 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235397455 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3235397455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2300958141
Short name T1845
Test name
Test status
Simulation time 47018424 ps
CPU time 1.01 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300958141 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2300958141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3889251583
Short name T1848
Test name
Test status
Simulation time 25999295 ps
CPU time 1.19 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889251583 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3889251583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.3460177123
Short name T1846
Test name
Test status
Simulation time 29703301 ps
CPU time 0.99 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460177123 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3460177123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.711209719
Short name T1847
Test name
Test status
Simulation time 16934146 ps
CPU time 1.03 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711209719 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.711209719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.2320255049
Short name T1851
Test name
Test status
Simulation time 19513830 ps
CPU time 1.04 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320255049 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2320255049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.2331461017
Short name T1849
Test name
Test status
Simulation time 28802080 ps
CPU time 0.98 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331461017 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2331461017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.313605879
Short name T1852
Test name
Test status
Simulation time 49324466 ps
CPU time 0.93 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313605879 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.313605879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2401693940
Short name T1850
Test name
Test status
Simulation time 33684800 ps
CPU time 1.03 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:42 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401693940 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2401693940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.595176604
Short name T116
Test name
Test status
Simulation time 45415333 ps
CPU time 1.28 seconds
Started Aug 25 06:29:08 AM UTC 24
Finished Aug 25 06:29:10 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=595176604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.595176604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.316204400
Short name T236
Test name
Test status
Simulation time 38152692 ps
CPU time 1.06 seconds
Started Aug 25 06:29:08 AM UTC 24
Finished Aug 25 06:29:10 AM UTC 24
Peak memory 214732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316204400 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.316204400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3201859852
Short name T1756
Test name
Test status
Simulation time 76021232 ps
CPU time 1.02 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:09 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201859852 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3201859852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4096963068
Short name T249
Test name
Test status
Simulation time 135791556 ps
CPU time 1.27 seconds
Started Aug 25 06:29:08 AM UTC 24
Finished Aug 25 06:29:10 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096963068 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.4096963068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3765841450
Short name T214
Test name
Test status
Simulation time 114331713 ps
CPU time 1.51 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:09 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765841450 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3765841450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.633858309
Short name T210
Test name
Test status
Simulation time 125368342 ps
CPU time 2.82 seconds
Started Aug 25 06:29:06 AM UTC 24
Finished Aug 25 06:29:10 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633858309 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.633858309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1669474996
Short name T1762
Test name
Test status
Simulation time 44869385 ps
CPU time 2.27 seconds
Started Aug 25 06:29:10 AM UTC 24
Finished Aug 25 06:29:14 AM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1669474996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1669474996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3722173117
Short name T242
Test name
Test status
Simulation time 123859283 ps
CPU time 1.04 seconds
Started Aug 25 06:29:09 AM UTC 24
Finished Aug 25 06:29:11 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722173117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3722173117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2387398985
Short name T1758
Test name
Test status
Simulation time 26194145 ps
CPU time 1.04 seconds
Started Aug 25 06:29:09 AM UTC 24
Finished Aug 25 06:29:11 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387398985 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2387398985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.911891651
Short name T1759
Test name
Test status
Simulation time 24889855 ps
CPU time 1.34 seconds
Started Aug 25 06:29:09 AM UTC 24
Finished Aug 25 06:29:12 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911891651 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.911891651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1280198787
Short name T1761
Test name
Test status
Simulation time 615280431 ps
CPU time 3.5 seconds
Started Aug 25 06:29:09 AM UTC 24
Finished Aug 25 06:29:14 AM UTC 24
Peak memory 215132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280198787 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1280198787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.496536285
Short name T222
Test name
Test status
Simulation time 266328032 ps
CPU time 3.09 seconds
Started Aug 25 06:29:09 AM UTC 24
Finished Aug 25 06:29:13 AM UTC 24
Peak memory 215316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496536285 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.496536285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3236117642
Short name T161
Test name
Test status
Simulation time 76945481 ps
CPU time 1.62 seconds
Started Aug 25 06:29:12 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3236117642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3236117642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1467230037
Short name T240
Test name
Test status
Simulation time 19444351 ps
CPU time 1.08 seconds
Started Aug 25 06:29:11 AM UTC 24
Finished Aug 25 06:29:13 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467230037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1467230037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1637730777
Short name T310
Test name
Test status
Simulation time 16665530 ps
CPU time 1 seconds
Started Aug 25 06:29:11 AM UTC 24
Finished Aug 25 06:29:13 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637730777 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1637730777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.692110188
Short name T133
Test name
Test status
Simulation time 141553258 ps
CPU time 1.15 seconds
Started Aug 25 06:29:12 AM UTC 24
Finished Aug 25 06:29:14 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692110188 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.692110188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.1758394117
Short name T162
Test name
Test status
Simulation time 195087121 ps
CPU time 3.32 seconds
Started Aug 25 06:29:10 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758394117 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1758394117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3510159789
Short name T220
Test name
Test status
Simulation time 1018160033 ps
CPU time 3.05 seconds
Started Aug 25 06:29:11 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510159789 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3510159789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2899228252
Short name T1766
Test name
Test status
Simulation time 45737493 ps
CPU time 1.25 seconds
Started Aug 25 06:29:13 AM UTC 24
Finished Aug 25 06:29:16 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2899228252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2899228252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2165051480
Short name T1765
Test name
Test status
Simulation time 71552789 ps
CPU time 1.06 seconds
Started Aug 25 06:29:13 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165051480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2165051480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3714253886
Short name T311
Test name
Test status
Simulation time 23564936 ps
CPU time 1.09 seconds
Started Aug 25 06:29:12 AM UTC 24
Finished Aug 25 06:29:14 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714253886 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3714253886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1060090878
Short name T1767
Test name
Test status
Simulation time 214308897 ps
CPU time 1.44 seconds
Started Aug 25 06:29:13 AM UTC 24
Finished Aug 25 06:29:16 AM UTC 24
Peak memory 214604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060090878 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.1060090878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1079467984
Short name T1763
Test name
Test status
Simulation time 176150978 ps
CPU time 1.96 seconds
Started Aug 25 06:29:12 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 213196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079467984 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1079467984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.277766614
Short name T1764
Test name
Test status
Simulation time 75222924 ps
CPU time 2.04 seconds
Started Aug 25 06:29:12 AM UTC 24
Finished Aug 25 06:29:15 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277766614 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.277766614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2606830761
Short name T1771
Test name
Test status
Simulation time 144476240 ps
CPU time 1.44 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:18 AM UTC 24
Peak memory 224672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2606830761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2606830761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3109334107
Short name T1769
Test name
Test status
Simulation time 19281833 ps
CPU time 1.09 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:17 AM UTC 24
Peak memory 214676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109334107 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3109334107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.4063034198
Short name T1768
Test name
Test status
Simulation time 110117866 ps
CPU time 0.96 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:17 AM UTC 24
Peak memory 214496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063034198 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4063034198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1333007716
Short name T1770
Test name
Test status
Simulation time 173483797 ps
CPU time 1.3 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:17 AM UTC 24
Peak memory 214680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333007716 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.1333007716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.1903894025
Short name T1775
Test name
Test status
Simulation time 142854026 ps
CPU time 3.96 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:20 AM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903894025 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1903894025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2024586236
Short name T219
Test name
Test status
Simulation time 336938553 ps
CPU time 3.28 seconds
Started Aug 25 06:29:15 AM UTC 24
Finished Aug 25 06:29:19 AM UTC 24
Peak memory 215184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024586236 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2024586236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.3637913455
Short name T266
Test name
Test status
Simulation time 427192210 ps
CPU time 27.91 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:55:19 AM UTC 24
Peak memory 315344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637913455 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.3637913455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.4228262117
Short name T29
Test name
Test status
Simulation time 12274453499 ps
CPU time 143.03 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:57:16 AM UTC 24
Peak memory 768264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228262117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4228262117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.303220485
Short name T192
Test name
Test status
Simulation time 6100390861 ps
CPU time 218.26 seconds
Started Aug 25 05:54:48 AM UTC 24
Finished Aug 25 05:58:31 AM UTC 24
Peak memory 872740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303220485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.303220485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3725485880
Short name T2
Test name
Test status
Simulation time 104010455 ps
CPU time 1.75 seconds
Started Aug 25 05:54:48 AM UTC 24
Finished Aug 25 05:54:51 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725485880 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.3725485880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2686733239
Short name T33
Test name
Test status
Simulation time 1051671801 ps
CPU time 64.51 seconds
Started Aug 25 05:54:48 AM UTC 24
Finished Aug 25 05:55:55 AM UTC 24
Peak memory 307300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686733239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2686733239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.3522875099
Short name T32
Test name
Test status
Simulation time 4118309928 ps
CPU time 25.06 seconds
Started Aug 25 05:54:50 AM UTC 24
Finished Aug 25 05:55:16 AM UTC 24
Peak memory 243812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522875099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3522875099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.3621711090
Short name T4
Test name
Test status
Simulation time 457516185 ps
CPU time 1.72 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:54:55 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621711
090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.3621711090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.2677100884
Short name T8
Test name
Test status
Simulation time 469919000 ps
CPU time 1.95 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:54:55 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677100
884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.2677100884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.2657848247
Short name T72
Test name
Test status
Simulation time 1971333826 ps
CPU time 6.05 seconds
Started Aug 25 05:54:53 AM UTC 24
Finished Aug 25 05:55:00 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657848
247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.2657848247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.2911658333
Short name T69
Test name
Test status
Simulation time 689527562 ps
CPU time 7.37 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:55:00 AM UTC 24
Peak memory 226628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291165
8333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.2911658333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.2909696949
Short name T455
Test name
Test status
Simulation time 17613953831 ps
CPU time 316.03 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 06:00:12 AM UTC 24
Peak memory 4345996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2909696949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress
_wr.2909696949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2476131579
Short name T62
Test name
Test status
Simulation time 2312187756 ps
CPU time 5.22 seconds
Started Aug 25 05:54:56 AM UTC 24
Finished Aug 25 05:55:02 AM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476131
579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.2476131579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_perf.930567327
Short name T73
Test name
Test status
Simulation time 1331225873 ps
CPU time 8.71 seconds
Started Aug 25 05:54:52 AM UTC 24
Finished Aug 25 05:55:02 AM UTC 24
Peak memory 228808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9305673
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.930567327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.1098962064
Short name T173
Test name
Test status
Simulation time 1197289936 ps
CPU time 4.78 seconds
Started Aug 25 05:54:56 AM UTC 24
Finished Aug 25 05:55:02 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098962
064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.1098962064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3275356357
Short name T174
Test name
Test status
Simulation time 23142317267 ps
CPU time 23.61 seconds
Started Aug 25 05:54:51 AM UTC 24
Finished Aug 25 05:55:16 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275356357 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.3275356357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.3281805906
Short name T51
Test name
Test status
Simulation time 30319375020 ps
CPU time 109.29 seconds
Started Aug 25 05:54:51 AM UTC 24
Finished Aug 25 05:56:43 AM UTC 24
Peak memory 1376440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281805906 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.3281805906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.3692577391
Short name T324
Test name
Test status
Simulation time 3909473232 ps
CPU time 21.57 seconds
Started Aug 25 05:54:51 AM UTC 24
Finished Aug 25 05:55:14 AM UTC 24
Peak memory 283032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692577391 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.3692577391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_alert_test.3847698658
Short name T102
Test name
Test status
Simulation time 31186856 ps
CPU time 0.95 seconds
Started Aug 25 05:55:20 AM UTC 24
Finished Aug 25 05:55:22 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847698658 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3847698658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.1946249395
Short name T176
Test name
Test status
Simulation time 1567105356 ps
CPU time 17.82 seconds
Started Aug 25 05:54:59 AM UTC 24
Finished Aug 25 05:55:19 AM UTC 24
Peak memory 270672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946249395 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.1946249395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.2034709928
Short name T28
Test name
Test status
Simulation time 2661910431 ps
CPU time 143.49 seconds
Started Aug 25 05:55:01 AM UTC 24
Finished Aug 25 05:57:27 AM UTC 24
Peak memory 837908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034709928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2034709928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.1900873982
Short name T106
Test name
Test status
Simulation time 2361255401 ps
CPU time 161.85 seconds
Started Aug 25 05:54:58 AM UTC 24
Finished Aug 25 05:57:44 AM UTC 24
Peak memory 698532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900873982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1900873982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.369755930
Short name T36
Test name
Test status
Simulation time 100743743 ps
CPU time 1.71 seconds
Started Aug 25 05:54:58 AM UTC 24
Finished Aug 25 05:55:01 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369755930 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.369755930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2177264826
Short name T44
Test name
Test status
Simulation time 2401610068 ps
CPU time 15.22 seconds
Started Aug 25 05:54:59 AM UTC 24
Finished Aug 25 05:55:16 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177264826 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.2177264826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.2868000788
Short name T85
Test name
Test status
Simulation time 12938526341 ps
CPU time 100.2 seconds
Started Aug 25 05:54:57 AM UTC 24
Finished Aug 25 05:56:40 AM UTC 24
Peak memory 944344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868000788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2868000788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.2115953594
Short name T13
Test name
Test status
Simulation time 1371500904 ps
CPU time 13.79 seconds
Started Aug 25 05:55:16 AM UTC 24
Finished Aug 25 05:55:31 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115953594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2115953594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_override.938692170
Short name T82
Test name
Test status
Simulation time 110632080 ps
CPU time 0.95 seconds
Started Aug 25 05:54:57 AM UTC 24
Finished Aug 25 05:54:59 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938692170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.938692170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_perf.2889113353
Short name T15
Test name
Test status
Simulation time 3394730980 ps
CPU time 14.22 seconds
Started Aug 25 05:55:01 AM UTC 24
Finished Aug 25 05:55:16 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889113353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2889113353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.3875558463
Short name T1517
Test name
Test status
Simulation time 23257220522 ps
CPU time 1778.88 seconds
Started Aug 25 05:55:01 AM UTC 24
Finished Aug 25 06:25:04 AM UTC 24
Peak memory 2199752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875558463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3875558463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.2810038381
Short name T203
Test name
Test status
Simulation time 7885744727 ps
CPU time 50.84 seconds
Started Aug 25 05:54:57 AM UTC 24
Finished Aug 25 05:55:50 AM UTC 24
Peak memory 352488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810038381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2810038381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.1910094779
Short name T175
Test name
Test status
Simulation time 619161792 ps
CPU time 16.19 seconds
Started Aug 25 05:55:01 AM UTC 24
Finished Aug 25 05:55:18 AM UTC 24
Peak memory 228912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910094779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1910094779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3328558484
Short name T205
Test name
Test status
Simulation time 154521532 ps
CPU time 1.22 seconds
Started Aug 25 05:55:19 AM UTC 24
Finished Aug 25 05:55:22 AM UTC 24
Peak memory 246856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328558484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3328558484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.543154537
Short name T65
Test name
Test status
Simulation time 11287173916 ps
CPU time 7.55 seconds
Started Aug 25 05:55:12 AM UTC 24
Finished Aug 25 05:55:21 AM UTC 24
Peak memory 233940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=543154537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.543154537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.1095725283
Short name T316
Test name
Test status
Simulation time 243112286 ps
CPU time 3.11 seconds
Started Aug 25 05:55:06 AM UTC 24
Finished Aug 25 05:55:11 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095725
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.1095725283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.2129784101
Short name T322
Test name
Test status
Simulation time 287213186 ps
CPU time 1.37 seconds
Started Aug 25 05:55:09 AM UTC 24
Finished Aug 25 05:55:11 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129784
101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.2129784101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.3510207196
Short name T300
Test name
Test status
Simulation time 295547893 ps
CPU time 3.53 seconds
Started Aug 25 05:55:17 AM UTC 24
Finished Aug 25 05:55:22 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510207
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermark
s_acq.3510207196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.1156333584
Short name T325
Test name
Test status
Simulation time 288978207 ps
CPU time 2.11 seconds
Started Aug 25 05:55:17 AM UTC 24
Finished Aug 25 05:55:20 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156333
584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_tx.1156333584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.1929629776
Short name T50
Test name
Test status
Simulation time 8613259071 ps
CPU time 14.91 seconds
Started Aug 25 05:55:02 AM UTC 24
Finished Aug 25 05:55:18 AM UTC 24
Peak memory 227592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929629776 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1929629776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.680281209
Short name T323
Test name
Test status
Simulation time 922939251 ps
CPU time 7.3 seconds
Started Aug 25 05:55:03 AM UTC 24
Finished Aug 25 05:55:12 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680281
209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.680281209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.3842316042
Short name T194
Test name
Test status
Simulation time 9250408999 ps
CPU time 9.68 seconds
Started Aug 25 05:55:04 AM UTC 24
Finished Aug 25 05:55:15 AM UTC 24
Peak memory 216944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3842316042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress
_wr.3842316042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.3587053730
Short name T63
Test name
Test status
Simulation time 517368951 ps
CPU time 4.35 seconds
Started Aug 25 05:55:18 AM UTC 24
Finished Aug 25 05:55:24 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587053
730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.3587053730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.1322160204
Short name T67
Test name
Test status
Simulation time 541831796 ps
CPU time 4.11 seconds
Started Aug 25 05:55:19 AM UTC 24
Finished Aug 25 05:55:25 AM UTC 24
Peak memory 216792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322160
204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1322160204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.2483160258
Short name T59
Test name
Test status
Simulation time 538512287 ps
CPU time 2.04 seconds
Started Aug 25 05:55:19 AM UTC 24
Finished Aug 25 05:55:23 AM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483160
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_txstretch.2483160258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_perf.1887865171
Short name T177
Test name
Test status
Simulation time 3117208635 ps
CPU time 8.05 seconds
Started Aug 25 05:55:10 AM UTC 24
Finished Aug 25 05:55:19 AM UTC 24
Peak memory 227212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887865
171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.1887865171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.3785563529
Short name T326
Test name
Test status
Simulation time 3486329541 ps
CPU time 3.03 seconds
Started Aug 25 05:55:17 AM UTC 24
Finished Aug 25 05:55:21 AM UTC 24
Peak memory 216432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785563
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.3785563529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.2157947041
Short name T193
Test name
Test status
Simulation time 1082918286 ps
CPU time 18.23 seconds
Started Aug 25 05:55:02 AM UTC 24
Finished Aug 25 05:55:21 AM UTC 24
Peak memory 233672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157947041 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.2157947041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3539900976
Short name T255
Test name
Test status
Simulation time 17552997117 ps
CPU time 235.45 seconds
Started Aug 25 05:55:11 AM UTC 24
Finished Aug 25 05:59:10 AM UTC 24
Peak memory 1939876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353990
0976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.3539900976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.1745241061
Short name T285
Test name
Test status
Simulation time 2661708639 ps
CPU time 41.67 seconds
Started Aug 25 05:55:03 AM UTC 24
Finished Aug 25 05:55:46 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745241061 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.1745241061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.975389368
Short name T337
Test name
Test status
Simulation time 14471340668 ps
CPU time 61.77 seconds
Started Aug 25 05:55:03 AM UTC 24
Finished Aug 25 05:56:07 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975389368 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.975389368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.4222534837
Short name T178
Test name
Test status
Simulation time 3997680023 ps
CPU time 96.92 seconds
Started Aug 25 05:55:03 AM UTC 24
Finished Aug 25 05:56:42 AM UTC 24
Peak memory 1099856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222534837 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.4222534837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.1320964356
Short name T76
Test name
Test status
Simulation time 1990751771 ps
CPU time 11.78 seconds
Started Aug 25 05:55:05 AM UTC 24
Finished Aug 25 05:55:18 AM UTC 24
Peak memory 230964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320964
356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.1320964356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.3656319384
Short name T71
Test name
Test status
Simulation time 87374186 ps
CPU time 3.79 seconds
Started Aug 25 05:55:17 AM UTC 24
Finished Aug 25 05:55:22 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656319
384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.3656319384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_alert_test.2994559269
Short name T480
Test name
Test status
Simulation time 25981763 ps
CPU time 0.93 seconds
Started Aug 25 06:00:51 AM UTC 24
Finished Aug 25 06:00:53 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994559269 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2994559269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.1985059285
Short name T466
Test name
Test status
Simulation time 175042608 ps
CPU time 2.19 seconds
Started Aug 25 06:00:19 AM UTC 24
Finished Aug 25 06:00:23 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985059285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1985059285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.2637585069
Short name T492
Test name
Test status
Simulation time 38437209884 ps
CPU time 67.68 seconds
Started Aug 25 06:00:17 AM UTC 24
Finished Aug 25 06:01:26 AM UTC 24
Peak memory 501988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637585069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2637585069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2115204661
Short name T543
Test name
Test status
Simulation time 1758046846 ps
CPU time 139.7 seconds
Started Aug 25 06:00:15 AM UTC 24
Finished Aug 25 06:02:37 AM UTC 24
Peak memory 651284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115204661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2115204661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.3171284468
Short name T463
Test name
Test status
Simulation time 341157350 ps
CPU time 1.18 seconds
Started Aug 25 06:00:16 AM UTC 24
Finished Aug 25 06:00:18 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171284468 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.3171284468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.60939993
Short name T467
Test name
Test status
Simulation time 638424723 ps
CPU time 6.42 seconds
Started Aug 25 06:00:16 AM UTC 24
Finished Aug 25 06:00:23 AM UTC 24
Peak memory 247880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60939993 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.60939993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.4200697549
Short name T514
Test name
Test status
Simulation time 5846645084 ps
CPU time 96.31 seconds
Started Aug 25 06:00:15 AM UTC 24
Finished Aug 25 06:01:53 AM UTC 24
Peak memory 1003596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200697549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.4200697549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.171100393
Short name T268
Test name
Test status
Simulation time 446489899 ps
CPU time 7.02 seconds
Started Aug 25 06:00:45 AM UTC 24
Finished Aug 25 06:00:53 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171100393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.171100393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_override.1091966529
Short name T460
Test name
Test status
Simulation time 200210387 ps
CPU time 0.97 seconds
Started Aug 25 06:00:13 AM UTC 24
Finished Aug 25 06:00:15 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091966529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1091966529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_perf.19986914
Short name T483
Test name
Test status
Simulation time 8027383272 ps
CPU time 35.02 seconds
Started Aug 25 06:00:18 AM UTC 24
Finished Aug 25 06:00:55 AM UTC 24
Peak memory 237132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19986914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.19986914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.1248047937
Short name T251
Test name
Test status
Simulation time 604777173 ps
CPU time 31.57 seconds
Started Aug 25 06:00:18 AM UTC 24
Finished Aug 25 06:00:51 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248047937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1248047937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.879856509
Short name T407
Test name
Test status
Simulation time 2499075380 ps
CPU time 23.83 seconds
Started Aug 25 06:00:13 AM UTC 24
Finished Aug 25 06:00:39 AM UTC 24
Peak memory 282880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879856509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.879856509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_stress_all.2170317515
Short name T1259
Test name
Test status
Simulation time 20342802385 ps
CPU time 1148.78 seconds
Started Aug 25 06:00:19 AM UTC 24
Finished Aug 25 06:19:42 AM UTC 24
Peak memory 3328424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170317515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2170317515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.2985523350
Short name T469
Test name
Test status
Simulation time 2513691876 ps
CPU time 13.38 seconds
Started Aug 25 06:00:19 AM UTC 24
Finished Aug 25 06:00:34 AM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985523350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2985523350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.1089165433
Short name T477
Test name
Test status
Simulation time 702074606 ps
CPU time 8.29 seconds
Started Aug 25 06:00:40 AM UTC 24
Finished Aug 25 06:00:50 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1089165433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.1089165433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.37901135
Short name T471
Test name
Test status
Simulation time 362040429 ps
CPU time 1.58 seconds
Started Aug 25 06:00:36 AM UTC 24
Finished Aug 25 06:00:39 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790113
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.37901135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1613301376
Short name T472
Test name
Test status
Simulation time 225380590 ps
CPU time 2.1 seconds
Started Aug 25 06:00:39 AM UTC 24
Finished Aug 25 06:00:42 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613301
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.1613301376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.54820537
Short name T479
Test name
Test status
Simulation time 889730926 ps
CPU time 4.32 seconds
Started Aug 25 06:00:46 AM UTC 24
Finished Aug 25 06:00:51 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5482053
7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermarks
_acq.54820537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.3052416479
Short name T475
Test name
Test status
Simulation time 107737346 ps
CPU time 1.55 seconds
Started Aug 25 06:00:47 AM UTC 24
Finished Aug 25 06:00:49 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052416
479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_tx.3052416479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.3863688945
Short name T441
Test name
Test status
Simulation time 15257282340 ps
CPU time 12.19 seconds
Started Aug 25 06:00:31 AM UTC 24
Finished Aug 25 06:00:44 AM UTC 24
Peak memory 250152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386368
8945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.3863688945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.2095731579
Short name T565
Test name
Test status
Simulation time 10966082703 ps
CPU time 154.66 seconds
Started Aug 25 06:00:33 AM UTC 24
Finished Aug 25 06:03:11 AM UTC 24
Peak memory 2801884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2095731579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres
s_wr.2095731579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.218994057
Short name T296
Test name
Test status
Simulation time 2029820636 ps
CPU time 4.87 seconds
Started Aug 25 06:00:50 AM UTC 24
Finished Aug 25 06:00:56 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189940
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.218994057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.1995925208
Short name T486
Test name
Test status
Simulation time 1824385497 ps
CPU time 3.75 seconds
Started Aug 25 06:00:51 AM UTC 24
Finished Aug 25 06:00:56 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995925
208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad
dr.1995925208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.1458474130
Short name T484
Test name
Test status
Simulation time 150987818 ps
CPU time 2.54 seconds
Started Aug 25 06:00:51 AM UTC 24
Finished Aug 25 06:00:55 AM UTC 24
Peak memory 233456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458474
130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.1458474130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_perf.443557878
Short name T474
Test name
Test status
Simulation time 1646786500 ps
CPU time 4.89 seconds
Started Aug 25 06:00:40 AM UTC 24
Finished Aug 25 06:00:46 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4435578
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.443557878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.2962192420
Short name T481
Test name
Test status
Simulation time 1808168435 ps
CPU time 3.88 seconds
Started Aug 25 06:00:49 AM UTC 24
Finished Aug 25 06:00:54 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962192
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.2962192420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3773635460
Short name T631
Test name
Test status
Simulation time 21214548897 ps
CPU time 263.35 seconds
Started Aug 25 06:00:40 AM UTC 24
Finished Aug 25 06:05:08 AM UTC 24
Peak memory 3479760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377363
5460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.3773635460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.3875749109
Short name T478
Test name
Test status
Simulation time 2396890445 ps
CPU time 24.43 seconds
Started Aug 25 06:00:25 AM UTC 24
Finished Aug 25 06:00:50 AM UTC 24
Peak memory 233864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875749109 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.3875749109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.2828657356
Short name T947
Test name
Test status
Simulation time 43651880612 ps
CPU time 683.3 seconds
Started Aug 25 06:00:23 AM UTC 24
Finished Aug 25 06:11:56 AM UTC 24
Peak memory 6058200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828657356 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.2828657356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.3578845508
Short name T509
Test name
Test status
Simulation time 3081365938 ps
CPU time 80.02 seconds
Started Aug 25 06:00:25 AM UTC 24
Finished Aug 25 06:01:47 AM UTC 24
Peak memory 932356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578845508 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.3578845508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.1976978529
Short name T473
Test name
Test status
Simulation time 1255147448 ps
CPU time 9.96 seconds
Started Aug 25 06:00:35 AM UTC 24
Finished Aug 25 06:00:46 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976978
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.1976978529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.1383197052
Short name T476
Test name
Test status
Simulation time 51499522 ps
CPU time 1.99 seconds
Started Aug 25 06:00:47 AM UTC 24
Finished Aug 25 06:00:50 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383197
052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.1383197052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_alert_test.737151945
Short name T499
Test name
Test status
Simulation time 37175325 ps
CPU time 0.99 seconds
Started Aug 25 06:01:32 AM UTC 24
Finished Aug 25 06:01:34 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737151945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.737151945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.214191411
Short name T488
Test name
Test status
Simulation time 410060286 ps
CPU time 6.57 seconds
Started Aug 25 06:00:57 AM UTC 24
Finished Aug 25 06:01:05 AM UTC 24
Peak memory 226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214191411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.214191411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.3298364027
Short name T135
Test name
Test status
Simulation time 1132985685 ps
CPU time 14.11 seconds
Started Aug 25 06:00:56 AM UTC 24
Finished Aug 25 06:01:11 AM UTC 24
Peak memory 344352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298364027 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.3298364027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.2309765319
Short name T596
Test name
Test status
Simulation time 3133765145 ps
CPU time 181.7 seconds
Started Aug 25 06:00:56 AM UTC 24
Finished Aug 25 06:04:01 AM UTC 24
Peak memory 475364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309765319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2309765319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.3619716689
Short name T522
Test name
Test status
Simulation time 4601675235 ps
CPU time 74.34 seconds
Started Aug 25 06:00:55 AM UTC 24
Finished Aug 25 06:02:11 AM UTC 24
Peak memory 733652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619716689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3619716689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.1973869557
Short name T258
Test name
Test status
Simulation time 83214824 ps
CPU time 1.44 seconds
Started Aug 25 06:00:55 AM UTC 24
Finished Aug 25 06:00:57 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973869557 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.1973869557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.679972574
Short name T489
Test name
Test status
Simulation time 513634167 ps
CPU time 10.66 seconds
Started Aug 25 06:00:56 AM UTC 24
Finished Aug 25 06:01:08 AM UTC 24
Peak memory 239952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679972574 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.679972574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.804538600
Short name T118
Test name
Test status
Simulation time 15679126773 ps
CPU time 73.27 seconds
Started Aug 25 06:00:53 AM UTC 24
Finished Aug 25 06:02:09 AM UTC 24
Peak memory 897432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804538600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.804538600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_override.3200362365
Short name T482
Test name
Test status
Simulation time 30554641 ps
CPU time 1.02 seconds
Started Aug 25 06:00:52 AM UTC 24
Finished Aug 25 06:00:54 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200362365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3200362365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_perf.3749156370
Short name T548
Test name
Test status
Simulation time 5330151986 ps
CPU time 109.87 seconds
Started Aug 25 06:00:56 AM UTC 24
Finished Aug 25 06:02:48 AM UTC 24
Peak memory 647388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749156370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3749156370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.3177327015
Short name T137
Test name
Test status
Simulation time 2784253482 ps
CPU time 14.85 seconds
Started Aug 25 06:00:57 AM UTC 24
Finished Aug 25 06:01:13 AM UTC 24
Peak memory 239180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177327015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3177327015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.3323567288
Short name T501
Test name
Test status
Simulation time 1546446380 ps
CPU time 40.77 seconds
Started Aug 25 06:00:52 AM UTC 24
Finished Aug 25 06:01:35 AM UTC 24
Peak memory 352456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323567288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3323567288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.2664349906
Short name T507
Test name
Test status
Simulation time 4899964627 ps
CPU time 38.49 seconds
Started Aug 25 06:00:57 AM UTC 24
Finished Aug 25 06:01:37 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664349906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2664349906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.1893802583
Short name T500
Test name
Test status
Simulation time 5363425302 ps
CPU time 10.88 seconds
Started Aug 25 06:01:22 AM UTC 24
Finished Aug 25 06:01:35 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1893802583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_ad
dr.1893802583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.497685957
Short name T143
Test name
Test status
Simulation time 345836839 ps
CPU time 2.07 seconds
Started Aug 25 06:01:19 AM UTC 24
Finished Aug 25 06:01:22 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4976859
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.497685957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.2795419572
Short name T142
Test name
Test status
Simulation time 154563874 ps
CPU time 1.54 seconds
Started Aug 25 06:01:19 AM UTC 24
Finished Aug 25 06:01:22 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795419
572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.2795419572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.2180433443
Short name T494
Test name
Test status
Simulation time 515361309 ps
CPU time 4.56 seconds
Started Aug 25 06:01:24 AM UTC 24
Finished Aug 25 06:01:29 AM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180433
443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.2180433443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.1353210637
Short name T496
Test name
Test status
Simulation time 163126515 ps
CPU time 1.92 seconds
Started Aug 25 06:01:28 AM UTC 24
Finished Aug 25 06:01:31 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353210
637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermark
s_tx.1353210637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.3959811238
Short name T139
Test name
Test status
Simulation time 1179134080 ps
CPU time 5.45 seconds
Started Aug 25 06:01:12 AM UTC 24
Finished Aug 25 06:01:18 AM UTC 24
Peak memory 230920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395981
1238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.3959811238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.377384265
Short name T505
Test name
Test status
Simulation time 559613773 ps
CPU time 5.25 seconds
Started Aug 25 06:01:30 AM UTC 24
Finished Aug 25 06:01:37 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773842
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.377384265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.2644276672
Short name T506
Test name
Test status
Simulation time 1152293485 ps
CPU time 4.41 seconds
Started Aug 25 06:01:31 AM UTC 24
Finished Aug 25 06:01:37 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644276
672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.2644276672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_nack_txstretch.3064940092
Short name T503
Test name
Test status
Simulation time 443691139 ps
CPU time 2.02 seconds
Started Aug 25 06:01:32 AM UTC 24
Finished Aug 25 06:01:36 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064940
092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_txstretch.3064940092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_perf.2511204741
Short name T495
Test name
Test status
Simulation time 587823017 ps
CPU time 7.92 seconds
Started Aug 25 06:01:21 AM UTC 24
Finished Aug 25 06:01:30 AM UTC 24
Peak memory 228876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511204
741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.2511204741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.2473783643
Short name T504
Test name
Test status
Simulation time 3071375795 ps
CPU time 4.7 seconds
Started Aug 25 06:01:30 AM UTC 24
Finished Aug 25 06:01:36 AM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473783
643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.2473783643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.3218889930
Short name T491
Test name
Test status
Simulation time 1258906110 ps
CPU time 22.37 seconds
Started Aug 25 06:00:59 AM UTC 24
Finished Aug 25 06:01:23 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218889930 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.3218889930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.3551945301
Short name T539
Test name
Test status
Simulation time 6466437321 ps
CPU time 68.53 seconds
Started Aug 25 06:01:21 AM UTC 24
Finished Aug 25 06:02:32 AM UTC 24
Peak memory 284828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355194
5301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.3551945301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.3735806390
Short name T141
Test name
Test status
Simulation time 1816022984 ps
CPU time 11.23 seconds
Started Aug 25 06:01:08 AM UTC 24
Finished Aug 25 06:01:21 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735806390 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.3735806390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.3605714236
Short name T138
Test name
Test status
Simulation time 8455590377 ps
CPU time 10.72 seconds
Started Aug 25 06:01:05 AM UTC 24
Finished Aug 25 06:01:17 AM UTC 24
Peak memory 216740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605714236 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.3605714236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.1132711424
Short name T297
Test name
Test status
Simulation time 3152585695 ps
CPU time 26.68 seconds
Started Aug 25 06:01:12 AM UTC 24
Finished Aug 25 06:01:40 AM UTC 24
Peak memory 790748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132711424 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.1132711424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.2804401040
Short name T493
Test name
Test status
Simulation time 1404946858 ps
CPU time 13.24 seconds
Started Aug 25 06:01:14 AM UTC 24
Finished Aug 25 06:01:29 AM UTC 24
Peak memory 231164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804401
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.2804401040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.2940055455
Short name T502
Test name
Test status
Simulation time 224841932 ps
CPU time 6.1 seconds
Started Aug 25 06:01:28 AM UTC 24
Finished Aug 25 06:01:35 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940055
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.2940055455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_alert_test.736461333
Short name T490
Test name
Test status
Simulation time 18139837 ps
CPU time 1.01 seconds
Started Aug 25 06:02:19 AM UTC 24
Finished Aug 25 06:02:21 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736461333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.736461333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.3141606063
Short name T510
Test name
Test status
Simulation time 1049945906 ps
CPU time 6.18 seconds
Started Aug 25 06:01:40 AM UTC 24
Finished Aug 25 06:01:47 AM UTC 24
Peak memory 256200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141606063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3141606063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.386328352
Short name T512
Test name
Test status
Simulation time 395772821 ps
CPU time 10.71 seconds
Started Aug 25 06:01:37 AM UTC 24
Finished Aug 25 06:01:49 AM UTC 24
Peak memory 303400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386328352 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.386328352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.3184597720
Short name T566
Test name
Test status
Simulation time 2555658194 ps
CPU time 146.78 seconds
Started Aug 25 06:01:38 AM UTC 24
Finished Aug 25 06:04:08 AM UTC 24
Peak memory 344260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184597720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3184597720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.2331595498
Short name T635
Test name
Test status
Simulation time 10121615164 ps
CPU time 214.18 seconds
Started Aug 25 06:01:35 AM UTC 24
Finished Aug 25 06:05:14 AM UTC 24
Peak memory 862372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331595498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2331595498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.415961593
Short name T508
Test name
Test status
Simulation time 275514588 ps
CPU time 8.05 seconds
Started Aug 25 06:01:37 AM UTC 24
Finished Aug 25 06:01:46 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415961593 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.415961593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.2964015601
Short name T119
Test name
Test status
Simulation time 18456503521 ps
CPU time 125.53 seconds
Started Aug 25 06:01:35 AM UTC 24
Finished Aug 25 06:03:44 AM UTC 24
Peak memory 1396800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964015601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2964015601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.1018016564
Short name T527
Test name
Test status
Simulation time 553464879 ps
CPU time 7.04 seconds
Started Aug 25 06:02:09 AM UTC 24
Finished Aug 25 06:02:17 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018016564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1018016564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_override.1728620252
Short name T146
Test name
Test status
Simulation time 178723709 ps
CPU time 1.03 seconds
Started Aug 25 06:01:35 AM UTC 24
Finished Aug 25 06:01:38 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728620252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1728620252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_perf.1153980819
Short name T696
Test name
Test status
Simulation time 7621220444 ps
CPU time 282.75 seconds
Started Aug 25 06:01:38 AM UTC 24
Finished Aug 25 06:06:25 AM UTC 24
Peak memory 1878240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153980819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1153980819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.519653215
Short name T699
Test name
Test status
Simulation time 5785576945 ps
CPU time 285.54 seconds
Started Aug 25 06:01:38 AM UTC 24
Finished Aug 25 06:06:28 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519653215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.519653215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.2186183420
Short name T563
Test name
Test status
Simulation time 6079924269 ps
CPU time 91.64 seconds
Started Aug 25 06:01:33 AM UTC 24
Finished Aug 25 06:03:07 AM UTC 24
Peak memory 373196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186183420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2186183420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.2687208644
Short name T515
Test name
Test status
Simulation time 665507725 ps
CPU time 18.51 seconds
Started Aug 25 06:01:39 AM UTC 24
Finished Aug 25 06:01:59 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687208644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2687208644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.2456740949
Short name T524
Test name
Test status
Simulation time 1517349600 ps
CPU time 6.89 seconds
Started Aug 25 06:02:04 AM UTC 24
Finished Aug 25 06:02:12 AM UTC 24
Peak memory 228924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2456740949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.2456740949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.132436337
Short name T516
Test name
Test status
Simulation time 128315886 ps
CPU time 1.36 seconds
Started Aug 25 06:01:58 AM UTC 24
Finished Aug 25 06:02:00 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324363
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.132436337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1387046977
Short name T518
Test name
Test status
Simulation time 610083998 ps
CPU time 2.38 seconds
Started Aug 25 06:02:00 AM UTC 24
Finished Aug 25 06:02:03 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387046
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.1387046977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.17724689
Short name T528
Test name
Test status
Simulation time 8058766885 ps
CPU time 5.35 seconds
Started Aug 25 06:02:11 AM UTC 24
Finished Aug 25 06:02:18 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772468
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermarks
_acq.17724689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.693779648
Short name T525
Test name
Test status
Simulation time 277077988 ps
CPU time 1.72 seconds
Started Aug 25 06:02:11 AM UTC 24
Finished Aug 25 06:02:14 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6937796
48 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermarks
_tx.693779648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.2750762653
Short name T521
Test name
Test status
Simulation time 379457738 ps
CPU time 3.72 seconds
Started Aug 25 06:02:06 AM UTC 24
Finished Aug 25 06:02:11 AM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750762
653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.2750762653
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.969782718
Short name T517
Test name
Test status
Simulation time 1887350958 ps
CPU time 9.84 seconds
Started Aug 25 06:01:49 AM UTC 24
Finished Aug 25 06:02:00 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969782
718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.969782718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.1711356524
Short name T544
Test name
Test status
Simulation time 4152167925 ps
CPU time 46.84 seconds
Started Aug 25 06:01:50 AM UTC 24
Finished Aug 25 06:02:38 AM UTC 24
Peak memory 1181920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1711356524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.1711356524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.2546666365
Short name T532
Test name
Test status
Simulation time 2079193433 ps
CPU time 5.02 seconds
Started Aug 25 06:02:18 AM UTC 24
Finished Aug 25 06:02:24 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546666
365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad
dr.2546666365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_perf.251329782
Short name T523
Test name
Test status
Simulation time 3987954191 ps
CPU time 9.54 seconds
Started Aug 25 06:02:01 AM UTC 24
Finished Aug 25 06:02:12 AM UTC 24
Peak memory 229180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513297
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.251329782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.2178292946
Short name T526
Test name
Test status
Simulation time 1189507877 ps
CPU time 3.78 seconds
Started Aug 25 06:02:13 AM UTC 24
Finished Aug 25 06:02:17 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178292
946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.2178292946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.160549813
Short name T520
Test name
Test status
Simulation time 2531125684 ps
CPU time 22.97 seconds
Started Aug 25 06:01:43 AM UTC 24
Finished Aug 25 06:02:07 AM UTC 24
Peak memory 231092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160549813 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.160549813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.1189731794
Short name T530
Test name
Test status
Simulation time 619589150 ps
CPU time 32.57 seconds
Started Aug 25 06:01:47 AM UTC 24
Finished Aug 25 06:02:21 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189731794 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.1189731794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.1442124034
Short name T568
Test name
Test status
Simulation time 36792573784 ps
CPU time 86.82 seconds
Started Aug 25 06:01:46 AM UTC 24
Finished Aug 25 06:03:15 AM UTC 24
Peak memory 1302676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442124034 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.1442124034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.2808807163
Short name T535
Test name
Test status
Simulation time 1437595142 ps
CPU time 36.3 seconds
Started Aug 25 06:01:48 AM UTC 24
Finished Aug 25 06:02:26 AM UTC 24
Peak memory 383052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808807163 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.2808807163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3928060898
Short name T519
Test name
Test status
Simulation time 1227072555 ps
CPU time 12.27 seconds
Started Aug 25 06:01:52 AM UTC 24
Finished Aug 25 06:02:05 AM UTC 24
Peak memory 243732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928060
898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.3928060898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.3394301378
Short name T529
Test name
Test status
Simulation time 163443555 ps
CPU time 5.3 seconds
Started Aug 25 06:02:13 AM UTC 24
Finished Aug 25 06:02:19 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394301
378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3394301378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_alert_test.2923130364
Short name T561
Test name
Test status
Simulation time 15183683 ps
CPU time 1 seconds
Started Aug 25 06:03:03 AM UTC 24
Finished Aug 25 06:03:05 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923130364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2923130364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3312514150
Short name T542
Test name
Test status
Simulation time 480067525 ps
CPU time 4 seconds
Started Aug 25 06:02:31 AM UTC 24
Finished Aug 25 06:02:36 AM UTC 24
Peak memory 227204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312514150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3312514150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.1817209429
Short name T537
Test name
Test status
Simulation time 321878019 ps
CPU time 5.71 seconds
Started Aug 25 06:02:23 AM UTC 24
Finished Aug 25 06:02:30 AM UTC 24
Peak memory 264268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817209429 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.1817209429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.1583161159
Short name T663
Test name
Test status
Simulation time 47208906560 ps
CPU time 203.79 seconds
Started Aug 25 06:02:24 AM UTC 24
Finished Aug 25 06:05:52 AM UTC 24
Peak memory 571612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583161159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1583161159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.2570095919
Short name T584
Test name
Test status
Simulation time 15151193696 ps
CPU time 99.69 seconds
Started Aug 25 06:02:22 AM UTC 24
Finished Aug 25 06:04:04 AM UTC 24
Peak memory 794896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570095919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2570095919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.4136750603
Short name T534
Test name
Test status
Simulation time 112456288 ps
CPU time 1.8 seconds
Started Aug 25 06:02:22 AM UTC 24
Finished Aug 25 06:02:25 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136750603 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.4136750603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.2143946517
Short name T538
Test name
Test status
Simulation time 419514633 ps
CPU time 5.87 seconds
Started Aug 25 06:02:23 AM UTC 24
Finished Aug 25 06:02:30 AM UTC 24
Peak memory 237648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143946517 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.2143946517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.3733742051
Short name T120
Test name
Test status
Simulation time 22472298547 ps
CPU time 154.2 seconds
Started Aug 25 06:02:21 AM UTC 24
Finished Aug 25 06:04:58 AM UTC 24
Peak memory 1624200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733742051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3733742051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.1959112242
Short name T269
Test name
Test status
Simulation time 2657938623 ps
CPU time 10.2 seconds
Started Aug 25 06:02:54 AM UTC 24
Finished Aug 25 06:03:06 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959112242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1959112242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_mode_toggle.3428247423
Short name T81
Test name
Test status
Simulation time 219197317 ps
CPU time 3.36 seconds
Started Aug 25 06:02:51 AM UTC 24
Finished Aug 25 06:02:55 AM UTC 24
Peak memory 243908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428247423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3428247423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_override.1782663395
Short name T531
Test name
Test status
Simulation time 87121966 ps
CPU time 1.03 seconds
Started Aug 25 06:02:20 AM UTC 24
Finished Aug 25 06:02:22 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782663395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1782663395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_perf.4013816782
Short name T1226
Test name
Test status
Simulation time 27039062898 ps
CPU time 970.4 seconds
Started Aug 25 06:02:26 AM UTC 24
Finished Aug 25 06:18:49 AM UTC 24
Peak memory 3025000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013816782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.4013816782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.1195830953
Short name T540
Test name
Test status
Simulation time 105410497 ps
CPU time 5.55 seconds
Started Aug 25 06:02:26 AM UTC 24
Finished Aug 25 06:02:32 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195830953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1195830953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3572624767
Short name T558
Test name
Test status
Simulation time 3142897760 ps
CPU time 39.98 seconds
Started Aug 25 06:02:20 AM UTC 24
Finished Aug 25 06:03:02 AM UTC 24
Peak memory 348472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572624767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3572624767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_stress_all.2131533494
Short name T200
Test name
Test status
Simulation time 20515122855 ps
CPU time 334.37 seconds
Started Aug 25 06:02:31 AM UTC 24
Finished Aug 25 06:08:11 AM UTC 24
Peak memory 490140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131533494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2131533494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1658050262
Short name T545
Test name
Test status
Simulation time 655965312 ps
CPU time 15.98 seconds
Started Aug 25 06:02:27 AM UTC 24
Finished Aug 25 06:02:44 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658050262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1658050262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.1021541310
Short name T554
Test name
Test status
Simulation time 827124778 ps
CPU time 6.95 seconds
Started Aug 25 06:02:49 AM UTC 24
Finished Aug 25 06:02:57 AM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1021541310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_ad
dr.1021541310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.2956416375
Short name T547
Test name
Test status
Simulation time 610822940 ps
CPU time 2.13 seconds
Started Aug 25 06:02:44 AM UTC 24
Finished Aug 25 06:02:48 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956416
375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.2956416375
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.1984980227
Short name T549
Test name
Test status
Simulation time 345897521 ps
CPU time 1.87 seconds
Started Aug 25 06:02:46 AM UTC 24
Finished Aug 25 06:02:48 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984980
227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.1984980227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.2489940158
Short name T557
Test name
Test status
Simulation time 441229438 ps
CPU time 3.85 seconds
Started Aug 25 06:02:55 AM UTC 24
Finished Aug 25 06:03:00 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489940
158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermar
ks_acq.2489940158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.3011977466
Short name T556
Test name
Test status
Simulation time 865910107 ps
CPU time 2.35 seconds
Started Aug 25 06:02:56 AM UTC 24
Finished Aug 25 06:03:00 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011977
466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_tx.3011977466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.4211255898
Short name T550
Test name
Test status
Simulation time 944056008 ps
CPU time 11.22 seconds
Started Aug 25 06:02:37 AM UTC 24
Finished Aug 25 06:02:50 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421125
5898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.4211255898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.4290779029
Short name T770
Test name
Test status
Simulation time 17649446551 ps
CPU time 327.17 seconds
Started Aug 25 06:02:38 AM UTC 24
Finished Aug 25 06:08:10 AM UTC 24
Peak memory 4299232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4290779029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stres
s_wr.4290779029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.826301077
Short name T560
Test name
Test status
Simulation time 2306600345 ps
CPU time 4.49 seconds
Started Aug 25 06:02:58 AM UTC 24
Finished Aug 25 06:03:04 AM UTC 24
Peak memory 227048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8263010
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.826301077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.1451581554
Short name T47
Test name
Test status
Simulation time 1180894149 ps
CPU time 4.08 seconds
Started Aug 25 06:03:00 AM UTC 24
Finished Aug 25 06:03:05 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451581
554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.1451581554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.3958758901
Short name T562
Test name
Test status
Simulation time 703560535 ps
CPU time 2.59 seconds
Started Aug 25 06:03:02 AM UTC 24
Finished Aug 25 06:03:05 AM UTC 24
Peak memory 233428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958758
901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.3958758901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_perf.2104862034
Short name T553
Test name
Test status
Simulation time 1434126071 ps
CPU time 8.42 seconds
Started Aug 25 06:02:47 AM UTC 24
Finished Aug 25 06:02:56 AM UTC 24
Peak memory 233064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104862
034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.2104862034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.949190971
Short name T559
Test name
Test status
Simulation time 926284455 ps
CPU time 3.44 seconds
Started Aug 25 06:02:58 AM UTC 24
Finished Aug 25 06:03:03 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9491909
71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.949190971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.1803974716
Short name T89
Test name
Test status
Simulation time 7843778410 ps
CPU time 38.69 seconds
Started Aug 25 06:02:31 AM UTC 24
Finished Aug 25 06:03:11 AM UTC 24
Peak memory 227248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803974716 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.1803974716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.3643712485
Short name T607
Test name
Test status
Simulation time 63428539869 ps
CPU time 96.31 seconds
Started Aug 25 06:02:49 AM UTC 24
Finished Aug 25 06:04:28 AM UTC 24
Peak memory 676120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364371
2485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.3643712485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.1564660225
Short name T546
Test name
Test status
Simulation time 545818808 ps
CPU time 11.33 seconds
Started Aug 25 06:02:33 AM UTC 24
Finished Aug 25 06:02:45 AM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564660225 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.1564660225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.3184829951
Short name T773
Test name
Test status
Simulation time 46539791969 ps
CPU time 336.63 seconds
Started Aug 25 06:02:33 AM UTC 24
Finished Aug 25 06:08:14 AM UTC 24
Peak memory 3529112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184829951 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.3184829951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.1102588040
Short name T551
Test name
Test status
Simulation time 2790076924 ps
CPU time 12.37 seconds
Started Aug 25 06:02:39 AM UTC 24
Finished Aug 25 06:02:53 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102588
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.1102588040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.147276558
Short name T569
Test name
Test status
Simulation time 671618726 ps
CPU time 16.72 seconds
Started Aug 25 06:02:57 AM UTC 24
Finished Aug 25 06:03:15 AM UTC 24
Peak memory 226692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472765
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.147276558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_alert_test.1527900163
Short name T590
Test name
Test status
Simulation time 30672509 ps
CPU time 0.87 seconds
Started Aug 25 06:03:49 AM UTC 24
Finished Aug 25 06:03:51 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527900163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1527900163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.3322977176
Short name T567
Test name
Test status
Simulation time 118403967 ps
CPU time 2.34 seconds
Started Aug 25 06:03:12 AM UTC 24
Finished Aug 25 06:03:15 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322977176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3322977176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.3039005467
Short name T572
Test name
Test status
Simulation time 189612155 ps
CPU time 11.1 seconds
Started Aug 25 06:03:07 AM UTC 24
Finished Aug 25 06:03:19 AM UTC 24
Peak memory 250012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039005467 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.3039005467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.3206866245
Short name T632
Test name
Test status
Simulation time 13744191225 ps
CPU time 118.52 seconds
Started Aug 25 06:03:08 AM UTC 24
Finished Aug 25 06:05:09 AM UTC 24
Peak memory 538772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206866245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3206866245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.3791927492
Short name T599
Test name
Test status
Simulation time 7011041842 ps
CPU time 66.54 seconds
Started Aug 25 06:03:06 AM UTC 24
Finished Aug 25 06:04:14 AM UTC 24
Peak memory 621036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791927492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3791927492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.4123557470
Short name T564
Test name
Test status
Simulation time 108317741 ps
CPU time 2.16 seconds
Started Aug 25 06:03:07 AM UTC 24
Finished Aug 25 06:03:10 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123557470 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.4123557470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.3966464999
Short name T571
Test name
Test status
Simulation time 460897133 ps
CPU time 8.58 seconds
Started Aug 25 06:03:08 AM UTC 24
Finished Aug 25 06:03:18 AM UTC 24
Peak memory 260232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966464999 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.3966464999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.4184176128
Short name T793
Test name
Test status
Simulation time 4558998057 ps
CPU time 329.5 seconds
Started Aug 25 06:03:06 AM UTC 24
Finished Aug 25 06:08:40 AM UTC 24
Peak memory 1360328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184176128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.4184176128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.2476879104
Short name T277
Test name
Test status
Simulation time 728796221 ps
CPU time 16.25 seconds
Started Aug 25 06:03:41 AM UTC 24
Finished Aug 25 06:03:58 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476879104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2476879104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_override.3585277160
Short name T147
Test name
Test status
Simulation time 20866526 ps
CPU time 1.1 seconds
Started Aug 25 06:03:05 AM UTC 24
Finished Aug 25 06:03:07 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585277160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3585277160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_perf.1373203300
Short name T646
Test name
Test status
Simulation time 7174580436 ps
CPU time 130.08 seconds
Started Aug 25 06:03:10 AM UTC 24
Finished Aug 25 06:05:23 AM UTC 24
Peak memory 237388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373203300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1373203300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.3738451044
Short name T570
Test name
Test status
Simulation time 176212001 ps
CPU time 3.62 seconds
Started Aug 25 06:03:11 AM UTC 24
Finished Aug 25 06:03:16 AM UTC 24
Peak memory 229008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738451044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3738451044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.3673502446
Short name T586
Test name
Test status
Simulation time 3649515931 ps
CPU time 43.53 seconds
Started Aug 25 06:03:04 AM UTC 24
Finished Aug 25 06:03:49 AM UTC 24
Peak memory 381152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673502446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3673502446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.263833663
Short name T574
Test name
Test status
Simulation time 953969954 ps
CPU time 21.33 seconds
Started Aug 25 06:03:11 AM UTC 24
Finished Aug 25 06:03:34 AM UTC 24
Peak memory 233740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263833663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.263833663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.2229294873
Short name T587
Test name
Test status
Simulation time 1696247455 ps
CPU time 7.29 seconds
Started Aug 25 06:03:41 AM UTC 24
Finished Aug 25 06:03:49 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2229294873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad
dr.2229294873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.2878190911
Short name T577
Test name
Test status
Simulation time 467394105 ps
CPU time 2.96 seconds
Started Aug 25 06:03:35 AM UTC 24
Finished Aug 25 06:03:39 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878190
911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.2878190911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.3420692289
Short name T576
Test name
Test status
Simulation time 652486310 ps
CPU time 1.59 seconds
Started Aug 25 06:03:36 AM UTC 24
Finished Aug 25 06:03:39 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420692
289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.3420692289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.4137426476
Short name T588
Test name
Test status
Simulation time 1097680331 ps
CPU time 4.54 seconds
Started Aug 25 06:03:44 AM UTC 24
Finished Aug 25 06:03:50 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137426
476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.4137426476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.914059654
Short name T585
Test name
Test status
Simulation time 157408161 ps
CPU time 2.12 seconds
Started Aug 25 06:03:45 AM UTC 24
Finished Aug 25 06:03:48 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9140596
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks
_tx.914059654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_hrst.2523743271
Short name T582
Test name
Test status
Simulation time 272192918 ps
CPU time 3.64 seconds
Started Aug 25 06:03:41 AM UTC 24
Finished Aug 25 06:03:45 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523743
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.2523743271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.1653779822
Short name T573
Test name
Test status
Simulation time 13537355025 ps
CPU time 11.33 seconds
Started Aug 25 06:03:19 AM UTC 24
Finished Aug 25 06:03:31 AM UTC 24
Peak memory 243924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165377
9822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.1653779822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.1096610175
Short name T608
Test name
Test status
Simulation time 5909297189 ps
CPU time 65.7 seconds
Started Aug 25 06:03:20 AM UTC 24
Finished Aug 25 06:04:28 AM UTC 24
Peak memory 1612180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1096610175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.1096610175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.2788948527
Short name T592
Test name
Test status
Simulation time 7392363675 ps
CPU time 4.3 seconds
Started Aug 25 06:03:47 AM UTC 24
Finished Aug 25 06:03:52 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788948
527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.2788948527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.2378068853
Short name T594
Test name
Test status
Simulation time 3531130713 ps
CPU time 4.93 seconds
Started Aug 25 06:03:48 AM UTC 24
Finished Aug 25 06:03:54 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378068
853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_ad
dr.2378068853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_perf.3450690031
Short name T583
Test name
Test status
Simulation time 2584296260 ps
CPU time 7.67 seconds
Started Aug 25 06:03:38 AM UTC 24
Finished Aug 25 06:03:46 AM UTC 24
Peak memory 229300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450690
031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.3450690031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.57075758
Short name T589
Test name
Test status
Simulation time 465706793 ps
CPU time 3.47 seconds
Started Aug 25 06:03:46 AM UTC 24
Finished Aug 25 06:03:51 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5707575
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.57075758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.3249749810
Short name T579
Test name
Test status
Simulation time 4867204544 ps
CPU time 22.72 seconds
Started Aug 25 06:03:16 AM UTC 24
Finished Aug 25 06:03:40 AM UTC 24
Peak memory 231148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249749810 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.3249749810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.368145519
Short name T637
Test name
Test status
Simulation time 74920401111 ps
CPU time 93.48 seconds
Started Aug 25 06:03:40 AM UTC 24
Finished Aug 25 06:05:15 AM UTC 24
Peak memory 538836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368145
519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.368145519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.2360115275
Short name T581
Test name
Test status
Simulation time 1350727962 ps
CPU time 26.23 seconds
Started Aug 25 06:03:17 AM UTC 24
Finished Aug 25 06:03:44 AM UTC 24
Peak memory 243836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360115275 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.2360115275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.1810537383
Short name T1747
Test name
Test status
Simulation time 69546094782 ps
CPU time 2386.44 seconds
Started Aug 25 06:03:16 AM UTC 24
Finished Aug 25 06:43:28 AM UTC 24
Peak memory 12533976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810537383 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.1810537383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.1769942801
Short name T580
Test name
Test status
Simulation time 2763378811 ps
CPU time 22.1 seconds
Started Aug 25 06:03:17 AM UTC 24
Finished Aug 25 06:03:40 AM UTC 24
Peak memory 467168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769942801 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.1769942801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.3487675728
Short name T578
Test name
Test status
Simulation time 2993115763 ps
CPU time 13.17 seconds
Started Aug 25 06:03:25 AM UTC 24
Finished Aug 25 06:03:40 AM UTC 24
Peak memory 233028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487675
728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.3487675728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_alert_test.1279651267
Short name T616
Test name
Test status
Simulation time 37171287 ps
CPU time 0.95 seconds
Started Aug 25 06:04:32 AM UTC 24
Finished Aug 25 06:04:34 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279651267 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1279651267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.4066904225
Short name T591
Test name
Test status
Simulation time 660739504 ps
CPU time 4 seconds
Started Aug 25 06:03:59 AM UTC 24
Finished Aug 25 06:04:04 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066904225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4066904225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.312511778
Short name T600
Test name
Test status
Simulation time 858806666 ps
CPU time 25.13 seconds
Started Aug 25 06:03:53 AM UTC 24
Finished Aug 25 06:04:19 AM UTC 24
Peak memory 305184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312511778 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.312511778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.1863882293
Short name T651
Test name
Test status
Simulation time 44184873861 ps
CPU time 126.55 seconds
Started Aug 25 06:03:53 AM UTC 24
Finished Aug 25 06:06:02 AM UTC 24
Peak memory 616900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863882293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1863882293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.2168745471
Short name T612
Test name
Test status
Simulation time 1772218858 ps
CPU time 128.99 seconds
Started Aug 25 06:03:52 AM UTC 24
Finished Aug 25 06:06:03 AM UTC 24
Peak memory 647244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168745471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2168745471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.916878196
Short name T593
Test name
Test status
Simulation time 449296954 ps
CPU time 1.37 seconds
Started Aug 25 06:03:52 AM UTC 24
Finished Aug 25 06:03:54 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916878196 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.916878196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.238068596
Short name T533
Test name
Test status
Simulation time 214315118 ps
CPU time 15.06 seconds
Started Aug 25 06:03:53 AM UTC 24
Finished Aug 25 06:04:09 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238068596 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.238068596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.1954209799
Short name T742
Test name
Test status
Simulation time 6142945061 ps
CPU time 200.5 seconds
Started Aug 25 06:03:51 AM UTC 24
Finished Aug 25 06:07:15 AM UTC 24
Peak memory 938188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954209799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1954209799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_override.356990923
Short name T148
Test name
Test status
Simulation time 56735324 ps
CPU time 1.13 seconds
Started Aug 25 06:03:50 AM UTC 24
Finished Aug 25 06:03:52 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356990923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.356990923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_perf.782471404
Short name T38
Test name
Test status
Simulation time 27787662268 ps
CPU time 92.98 seconds
Started Aug 25 06:03:55 AM UTC 24
Finished Aug 25 06:05:31 AM UTC 24
Peak memory 283040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782471404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.782471404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.3893715296
Short name T595
Test name
Test status
Simulation time 145354959 ps
CPU time 2.25 seconds
Started Aug 25 06:03:55 AM UTC 24
Finished Aug 25 06:03:58 AM UTC 24
Peak memory 237244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893715296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3893715296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.245502998
Short name T598
Test name
Test status
Simulation time 13677918372 ps
CPU time 29.53 seconds
Started Aug 25 06:03:49 AM UTC 24
Finished Aug 25 06:04:20 AM UTC 24
Peak memory 327904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245502998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.245502998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.3380439816
Short name T624
Test name
Test status
Simulation time 2915516777 ps
CPU time 42.74 seconds
Started Aug 25 06:03:59 AM UTC 24
Finished Aug 25 06:04:44 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380439816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3380439816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.4161467803
Short name T615
Test name
Test status
Simulation time 847528482 ps
CPU time 9.04 seconds
Started Aug 25 06:04:23 AM UTC 24
Finished Aug 25 06:04:33 AM UTC 24
Peak memory 232976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4161467803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.4161467803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.2221547160
Short name T602
Test name
Test status
Simulation time 222239844 ps
CPU time 2.58 seconds
Started Aug 25 06:04:18 AM UTC 24
Finished Aug 25 06:04:22 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221547
160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.2221547160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.2838802792
Short name T603
Test name
Test status
Simulation time 325772887 ps
CPU time 1.4 seconds
Started Aug 25 06:04:20 AM UTC 24
Finished Aug 25 06:04:23 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838802
792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.2838802792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.839882324
Short name T614
Test name
Test status
Simulation time 1775840858 ps
CPU time 4.32 seconds
Started Aug 25 06:04:27 AM UTC 24
Finished Aug 25 06:04:33 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8398823
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_acq.839882324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.3310959754
Short name T613
Test name
Test status
Simulation time 128164246 ps
CPU time 2.08 seconds
Started Aug 25 06:04:28 AM UTC 24
Finished Aug 25 06:04:31 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310959
754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_tx.3310959754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_hrst.1270442314
Short name T610
Test name
Test status
Simulation time 455475852 ps
CPU time 3.46 seconds
Started Aug 25 06:04:24 AM UTC 24
Finished Aug 25 06:04:28 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270442
314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_hrst.1270442314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.3218835887
Short name T601
Test name
Test status
Simulation time 817768096 ps
CPU time 8.95 seconds
Started Aug 25 06:04:10 AM UTC 24
Finished Aug 25 06:04:20 AM UTC 24
Peak memory 229104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321883
5887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.3218835887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.311432963
Short name T609
Test name
Test status
Simulation time 12296711493 ps
CPU time 16.53 seconds
Started Aug 25 06:04:10 AM UTC 24
Finished Aug 25 06:04:28 AM UTC 24
Peak memory 274944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=311432963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stress
_wr.311432963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.2630647941
Short name T619
Test name
Test status
Simulation time 598616692 ps
CPU time 4.84 seconds
Started Aug 25 06:04:29 AM UTC 24
Finished Aug 25 06:04:35 AM UTC 24
Peak memory 226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630647
941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.2630647941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.2023592062
Short name T618
Test name
Test status
Simulation time 958427612 ps
CPU time 4.32 seconds
Started Aug 25 06:04:29 AM UTC 24
Finished Aug 25 06:04:35 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023592
062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad
dr.2023592062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.1977853051
Short name T621
Test name
Test status
Simulation time 961100767 ps
CPU time 2.36 seconds
Started Aug 25 06:04:32 AM UTC 24
Finished Aug 25 06:04:36 AM UTC 24
Peak memory 233428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977853
051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.1977853051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_perf.2849790432
Short name T611
Test name
Test status
Simulation time 1043556275 ps
CPU time 5.94 seconds
Started Aug 25 06:04:21 AM UTC 24
Finished Aug 25 06:04:29 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849790
432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.2849790432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.2981733938
Short name T617
Test name
Test status
Simulation time 415088183 ps
CPU time 3.97 seconds
Started Aug 25 06:04:29 AM UTC 24
Finished Aug 25 06:04:34 AM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981733
938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.2981733938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.4201866730
Short name T606
Test name
Test status
Simulation time 3701528347 ps
CPU time 19.44 seconds
Started Aug 25 06:04:04 AM UTC 24
Finished Aug 25 06:04:25 AM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201866730 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.4201866730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.4211096950
Short name T804
Test name
Test status
Simulation time 37353131976 ps
CPU time 268.29 seconds
Started Aug 25 06:04:21 AM UTC 24
Finished Aug 25 06:08:54 AM UTC 24
Peak memory 2453728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421109
6950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.4211096950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.4131898659
Short name T627
Test name
Test status
Simulation time 15179978244 ps
CPU time 49.26 seconds
Started Aug 25 06:04:06 AM UTC 24
Finished Aug 25 06:04:57 AM UTC 24
Peak memory 250308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131898659 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.4131898659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.2067900927
Short name T716
Test name
Test status
Simulation time 49204748809 ps
CPU time 155.57 seconds
Started Aug 25 06:04:05 AM UTC 24
Finished Aug 25 06:06:44 AM UTC 24
Peak memory 1904848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067900927 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.2067900927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.3878652067
Short name T605
Test name
Test status
Simulation time 3432507901 ps
CPU time 14.66 seconds
Started Aug 25 06:04:09 AM UTC 24
Finished Aug 25 06:04:25 AM UTC 24
Peak memory 324092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878652067 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.3878652067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.3876039477
Short name T604
Test name
Test status
Simulation time 4603980735 ps
CPU time 11.55 seconds
Started Aug 25 06:04:12 AM UTC 24
Finished Aug 25 06:04:25 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876039
477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.3876039477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.891103245
Short name T294
Test name
Test status
Simulation time 151692523 ps
CPU time 5.24 seconds
Started Aug 25 06:04:28 AM UTC 24
Finished Aug 25 06:04:35 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8911032
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.891103245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_alert_test.1544416307
Short name T649
Test name
Test status
Simulation time 46955859 ps
CPU time 1.02 seconds
Started Aug 25 06:05:23 AM UTC 24
Finished Aug 25 06:05:25 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544416307 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1544416307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.2218850025
Short name T625
Test name
Test status
Simulation time 1056491785 ps
CPU time 2.93 seconds
Started Aug 25 06:04:42 AM UTC 24
Finished Aug 25 06:04:46 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218850025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2218850025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.64863647
Short name T628
Test name
Test status
Simulation time 427731701 ps
CPU time 26.03 seconds
Started Aug 25 06:04:36 AM UTC 24
Finished Aug 25 06:05:03 AM UTC 24
Peak memory 313296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64863647 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.64863647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.3462753922
Short name T788
Test name
Test status
Simulation time 3469976230 ps
CPU time 233.94 seconds
Started Aug 25 06:04:37 AM UTC 24
Finished Aug 25 06:08:35 AM UTC 24
Peak memory 739792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462753922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3462753922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.969975854
Short name T689
Test name
Test status
Simulation time 2440933017 ps
CPU time 100.74 seconds
Started Aug 25 06:04:36 AM UTC 24
Finished Aug 25 06:06:19 AM UTC 24
Peak memory 792848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969975854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.969975854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.736983023
Short name T622
Test name
Test status
Simulation time 103789668 ps
CPU time 1.86 seconds
Started Aug 25 06:04:36 AM UTC 24
Finished Aug 25 06:04:39 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736983023 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.736983023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.504439615
Short name T626
Test name
Test status
Simulation time 233485578 ps
CPU time 13.68 seconds
Started Aug 25 06:04:36 AM UTC 24
Finished Aug 25 06:04:51 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504439615 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.504439615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.3774646511
Short name T752
Test name
Test status
Simulation time 5626449171 ps
CPU time 187.49 seconds
Started Aug 25 06:04:36 AM UTC 24
Finished Aug 25 06:07:47 AM UTC 24
Peak memory 1628564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774646511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3774646511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.3168516351
Short name T654
Test name
Test status
Simulation time 617263896 ps
CPU time 11.82 seconds
Started Aug 25 06:05:16 AM UTC 24
Finished Aug 25 06:05:29 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168516351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3168516351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_mode_toggle.1216829398
Short name T643
Test name
Test status
Simulation time 184191374 ps
CPU time 4.51 seconds
Started Aug 25 06:05:16 AM UTC 24
Finished Aug 25 06:05:22 AM UTC 24
Peak memory 248208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216829398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1216829398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_override.643240168
Short name T620
Test name
Test status
Simulation time 86908478 ps
CPU time 1.06 seconds
Started Aug 25 06:04:33 AM UTC 24
Finished Aug 25 06:04:36 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643240168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.643240168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_perf.3361996995
Short name T1622
Test name
Test status
Simulation time 73253991699 ps
CPU time 1320.42 seconds
Started Aug 25 06:04:37 AM UTC 24
Finished Aug 25 06:26:54 AM UTC 24
Peak memory 3609036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361996995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3361996995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.233894088
Short name T623
Test name
Test status
Simulation time 43086601 ps
CPU time 1.67 seconds
Started Aug 25 06:04:39 AM UTC 24
Finished Aug 25 06:04:42 AM UTC 24
Peak memory 236488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233894088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.233894088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.2822531169
Short name T694
Test name
Test status
Simulation time 12969067919 ps
CPU time 107.13 seconds
Started Aug 25 06:04:33 AM UTC 24
Finished Aug 25 06:06:23 AM UTC 24
Peak memory 368824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822531169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2822531169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.2002258308
Short name T629
Test name
Test status
Simulation time 1525841831 ps
CPU time 22.91 seconds
Started Aug 25 06:04:40 AM UTC 24
Finished Aug 25 06:05:04 AM UTC 24
Peak memory 227068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002258308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2002258308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.2888427318
Short name T642
Test name
Test status
Simulation time 1108814397 ps
CPU time 6.07 seconds
Started Aug 25 06:05:14 AM UTC 24
Finished Aug 25 06:05:21 AM UTC 24
Peak memory 227116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2888427318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_ad
dr.2888427318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.2965414848
Short name T633
Test name
Test status
Simulation time 381365578 ps
CPU time 1.32 seconds
Started Aug 25 06:05:10 AM UTC 24
Finished Aug 25 06:05:12 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965414
848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.2965414848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.1181318982
Short name T295
Test name
Test status
Simulation time 585028281 ps
CPU time 1.77 seconds
Started Aug 25 06:05:13 AM UTC 24
Finished Aug 25 06:05:16 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181318
982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.1181318982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.3982918977
Short name T645
Test name
Test status
Simulation time 505538063 ps
CPU time 4.26 seconds
Started Aug 25 06:05:17 AM UTC 24
Finished Aug 25 06:05:23 AM UTC 24
Peak memory 216552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982918
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.3982918977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.3948753785
Short name T644
Test name
Test status
Simulation time 103835174 ps
CPU time 1.74 seconds
Started Aug 25 06:05:20 AM UTC 24
Finished Aug 25 06:05:22 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948753
785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermark
s_tx.3948753785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_hrst.3773076897
Short name T639
Test name
Test status
Simulation time 170989455 ps
CPU time 2.27 seconds
Started Aug 25 06:05:16 AM UTC 24
Finished Aug 25 06:05:20 AM UTC 24
Peak memory 227124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773076
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.3773076897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.4104572384
Short name T638
Test name
Test status
Simulation time 2580421245 ps
CPU time 14.06 seconds
Started Aug 25 06:05:04 AM UTC 24
Finished Aug 25 06:05:19 AM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410457
2384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.4104572384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.1310541307
Short name T1294
Test name
Test status
Simulation time 34565820204 ps
CPU time 908.8 seconds
Started Aug 25 06:05:05 AM UTC 24
Finished Aug 25 06:20:24 AM UTC 24
Peak memory 8536220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1310541307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stres
s_wr.1310541307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.1906561977
Short name T653
Test name
Test status
Simulation time 583268732 ps
CPU time 5.51 seconds
Started Aug 25 06:05:22 AM UTC 24
Finished Aug 25 06:05:28 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906561
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.1906561977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.3789617563
Short name T652
Test name
Test status
Simulation time 1048855440 ps
CPU time 4.82 seconds
Started Aug 25 06:05:22 AM UTC 24
Finished Aug 25 06:05:28 AM UTC 24
Peak memory 216400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789617
563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.3789617563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_perf.1769396127
Short name T640
Test name
Test status
Simulation time 607186957 ps
CPU time 6.04 seconds
Started Aug 25 06:05:13 AM UTC 24
Finished Aug 25 06:05:20 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769396
127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.1769396127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.38406740
Short name T648
Test name
Test status
Simulation time 1595130326 ps
CPU time 3.24 seconds
Started Aug 25 06:05:21 AM UTC 24
Finished Aug 25 06:05:25 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840674
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.38406740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.122058943
Short name T636
Test name
Test status
Simulation time 620423366 ps
CPU time 26.22 seconds
Started Aug 25 06:04:47 AM UTC 24
Finished Aug 25 06:05:15 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122058943 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.122058943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.2998329949
Short name T1567
Test name
Test status
Simulation time 58442338838 ps
CPU time 1734.85 seconds
Started Aug 25 06:05:14 AM UTC 24
Finished Aug 25 06:34:29 AM UTC 24
Peak memory 10903980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299832
9949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.2998329949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.663134931
Short name T630
Test name
Test status
Simulation time 1359919896 ps
CPU time 8.53 seconds
Started Aug 25 06:04:57 AM UTC 24
Finished Aug 25 06:05:07 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663134931 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.663134931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.1783371562
Short name T634
Test name
Test status
Simulation time 10548609464 ps
CPU time 20.3 seconds
Started Aug 25 06:04:51 AM UTC 24
Finished Aug 25 06:05:13 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783371562 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.1783371562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.543193046
Short name T666
Test name
Test status
Simulation time 5093980993 ps
CPU time 52.2 seconds
Started Aug 25 06:05:00 AM UTC 24
Finished Aug 25 06:05:54 AM UTC 24
Peak memory 450812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543193046 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.543193046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.361072068
Short name T641
Test name
Test status
Simulation time 23919807710 ps
CPU time 11.94 seconds
Started Aug 25 06:05:08 AM UTC 24
Finished Aug 25 06:05:21 AM UTC 24
Peak memory 233784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610720
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.361072068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.2461383997
Short name T647
Test name
Test status
Simulation time 71182736 ps
CPU time 2.36 seconds
Started Aug 25 06:05:21 AM UTC 24
Finished Aug 25 06:05:24 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461383
997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2461383997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_alert_test.2782193719
Short name T677
Test name
Test status
Simulation time 18747972 ps
CPU time 0.95 seconds
Started Aug 25 06:06:06 AM UTC 24
Finished Aug 25 06:06:08 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782193719 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2782193719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.3958776922
Short name T657
Test name
Test status
Simulation time 1390052031 ps
CPU time 3.36 seconds
Started Aug 25 06:05:31 AM UTC 24
Finished Aug 25 06:05:35 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958776922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3958776922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.3238412563
Short name T664
Test name
Test status
Simulation time 1423436205 ps
CPU time 23.61 seconds
Started Aug 25 06:05:27 AM UTC 24
Finished Aug 25 06:05:53 AM UTC 24
Peak memory 299332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238412563 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.3238412563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.3588557976
Short name T729
Test name
Test status
Simulation time 11573372203 ps
CPU time 97.41 seconds
Started Aug 25 06:05:28 AM UTC 24
Finished Aug 25 06:07:08 AM UTC 24
Peak memory 528592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588557976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3588557976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.704819817
Short name T810
Test name
Test status
Simulation time 11861240335 ps
CPU time 210.89 seconds
Started Aug 25 06:05:25 AM UTC 24
Finished Aug 25 06:09:00 AM UTC 24
Peak memory 854212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704819817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.704819817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.3667724715
Short name T655
Test name
Test status
Simulation time 520001358 ps
CPU time 2.08 seconds
Started Aug 25 06:05:26 AM UTC 24
Finished Aug 25 06:05:29 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667724715 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.3667724715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.3166488924
Short name T659
Test name
Test status
Simulation time 521064074 ps
CPU time 9.79 seconds
Started Aug 25 06:05:27 AM UTC 24
Finished Aug 25 06:05:39 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166488924 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.3166488924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.1480562564
Short name T782
Test name
Test status
Simulation time 2654337824 ps
CPU time 181.63 seconds
Started Aug 25 06:05:25 AM UTC 24
Finished Aug 25 06:08:30 AM UTC 24
Peak memory 864768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480562564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1480562564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.2598057697
Short name T270
Test name
Test status
Simulation time 2948564804 ps
CPU time 7.6 seconds
Started Aug 25 06:05:59 AM UTC 24
Finished Aug 25 06:06:08 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598057697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.2598057697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_override.1477295397
Short name T650
Test name
Test status
Simulation time 39183320 ps
CPU time 1.06 seconds
Started Aug 25 06:05:24 AM UTC 24
Finished Aug 25 06:05:26 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477295397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1477295397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_perf.288961367
Short name T1019
Test name
Test status
Simulation time 32730491881 ps
CPU time 477.07 seconds
Started Aug 25 06:05:29 AM UTC 24
Finished Aug 25 06:13:34 AM UTC 24
Peak memory 790852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288961367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.288961367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.2247114501
Short name T656
Test name
Test status
Simulation time 295879018 ps
CPU time 4.22 seconds
Started Aug 25 06:05:30 AM UTC 24
Finished Aug 25 06:05:35 AM UTC 24
Peak memory 232892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247114501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2247114501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.2833795012
Short name T669
Test name
Test status
Simulation time 5624108049 ps
CPU time 32.35 seconds
Started Aug 25 06:05:24 AM UTC 24
Finished Aug 25 06:05:58 AM UTC 24
Peak memory 362700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833795012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2833795012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.3688131884
Short name T660
Test name
Test status
Simulation time 755065465 ps
CPU time 9.27 seconds
Started Aug 25 06:05:31 AM UTC 24
Finished Aug 25 06:05:41 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688131884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3688131884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.1002758119
Short name T673
Test name
Test status
Simulation time 1176962805 ps
CPU time 8.54 seconds
Started Aug 25 06:05:55 AM UTC 24
Finished Aug 25 06:06:05 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1002758119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.1002758119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.207294987
Short name T668
Test name
Test status
Simulation time 391296336 ps
CPU time 1.59 seconds
Started Aug 25 06:05:53 AM UTC 24
Finished Aug 25 06:05:55 AM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072949
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.207294987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.1324800722
Short name T667
Test name
Test status
Simulation time 162159393 ps
CPU time 1.53 seconds
Started Aug 25 06:05:53 AM UTC 24
Finished Aug 25 06:05:55 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324800
722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.1324800722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.2804765853
Short name T674
Test name
Test status
Simulation time 2235071318 ps
CPU time 4.73 seconds
Started Aug 25 06:05:59 AM UTC 24
Finished Aug 25 06:06:05 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804765
853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermar
ks_acq.2804765853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.1731932064
Short name T676
Test name
Test status
Simulation time 141354505 ps
CPU time 2.21 seconds
Started Aug 25 06:06:02 AM UTC 24
Finished Aug 25 06:06:05 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731932
064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_tx.1731932064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_hrst.2608154303
Short name T671
Test name
Test status
Simulation time 971206959 ps
CPU time 5.06 seconds
Started Aug 25 06:05:56 AM UTC 24
Finished Aug 25 06:06:02 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608154
303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.2608154303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.3984061557
Short name T665
Test name
Test status
Simulation time 1241395754 ps
CPU time 9.65 seconds
Started Aug 25 06:05:42 AM UTC 24
Finished Aug 25 06:05:53 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398406
1557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.3984061557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.2223531620
Short name T675
Test name
Test status
Simulation time 7923793710 ps
CPU time 18.53 seconds
Started Aug 25 06:05:45 AM UTC 24
Finished Aug 25 06:06:05 AM UTC 24
Peak memory 260504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2223531620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.2223531620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.972868647
Short name T685
Test name
Test status
Simulation time 4072157509 ps
CPU time 5.24 seconds
Started Aug 25 06:06:04 AM UTC 24
Finished Aug 25 06:06:11 AM UTC 24
Peak memory 227180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9728686
47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.972868647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.2767231938
Short name T683
Test name
Test status
Simulation time 1198588576 ps
CPU time 4.58 seconds
Started Aug 25 06:06:04 AM UTC 24
Finished Aug 25 06:06:10 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767231
938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.2767231938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_perf.54617597
Short name T670
Test name
Test status
Simulation time 658060158 ps
CPU time 6.65 seconds
Started Aug 25 06:05:54 AM UTC 24
Finished Aug 25 06:06:02 AM UTC 24
Peak memory 228796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5461759
7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.54617597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.181942334
Short name T678
Test name
Test status
Simulation time 4602638072 ps
CPU time 3.97 seconds
Started Aug 25 06:06:03 AM UTC 24
Finished Aug 25 06:06:08 AM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819423
34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.181942334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.2348498043
Short name T679
Test name
Test status
Simulation time 1420041063 ps
CPU time 31.02 seconds
Started Aug 25 06:05:36 AM UTC 24
Finished Aug 25 06:06:09 AM UTC 24
Peak memory 231104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348498043 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.2348498043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.274306633
Short name T979
Test name
Test status
Simulation time 48136501850 ps
CPU time 395.96 seconds
Started Aug 25 06:05:54 AM UTC 24
Finished Aug 25 06:12:35 AM UTC 24
Peak memory 4405356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274306
633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.274306633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.3299466075
Short name T682
Test name
Test status
Simulation time 1684986277 ps
CPU time 29.28 seconds
Started Aug 25 06:05:39 AM UTC 24
Finished Aug 25 06:06:10 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299466075 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.3299466075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.344029135
Short name T1604
Test name
Test status
Simulation time 54828077459 ps
CPU time 1296.62 seconds
Started Aug 25 06:05:36 AM UTC 24
Finished Aug 25 06:27:29 AM UTC 24
Peak memory 9029788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344029135 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.344029135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.1244157278
Short name T662
Test name
Test status
Simulation time 1924438105 ps
CPU time 7.31 seconds
Started Aug 25 06:05:40 AM UTC 24
Finished Aug 25 06:05:49 AM UTC 24
Peak memory 301144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244157278 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.1244157278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.2547093984
Short name T672
Test name
Test status
Simulation time 6182820154 ps
CPU time 12.34 seconds
Started Aug 25 06:05:49 AM UTC 24
Finished Aug 25 06:06:04 AM UTC 24
Peak memory 245932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547093
984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.2547093984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.2322985638
Short name T681
Test name
Test status
Simulation time 122850099 ps
CPU time 4.52 seconds
Started Aug 25 06:06:03 AM UTC 24
Finished Aug 25 06:06:09 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322985
638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2322985638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_alert_test.1490943108
Short name T706
Test name
Test status
Simulation time 16181670 ps
CPU time 1 seconds
Started Aug 25 06:06:36 AM UTC 24
Finished Aug 25 06:06:38 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490943108 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1490943108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.2016826891
Short name T693
Test name
Test status
Simulation time 202620319 ps
CPU time 9.18 seconds
Started Aug 25 06:06:11 AM UTC 24
Finished Aug 25 06:06:22 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016826891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2016826891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.3505256706
Short name T692
Test name
Test status
Simulation time 696812868 ps
CPU time 10.37 seconds
Started Aug 25 06:06:10 AM UTC 24
Finished Aug 25 06:06:22 AM UTC 24
Peak memory 250188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505256706 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.3505256706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.1068788379
Short name T777
Test name
Test status
Simulation time 27576183236 ps
CPU time 128.09 seconds
Started Aug 25 06:06:10 AM UTC 24
Finished Aug 25 06:08:21 AM UTC 24
Peak memory 401632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068788379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1068788379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.811646200
Short name T727
Test name
Test status
Simulation time 1646680484 ps
CPU time 51.71 seconds
Started Aug 25 06:06:09 AM UTC 24
Finished Aug 25 06:07:02 AM UTC 24
Peak memory 487556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811646200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.811646200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.4016838918
Short name T686
Test name
Test status
Simulation time 111675892 ps
CPU time 1.48 seconds
Started Aug 25 06:06:09 AM UTC 24
Finished Aug 25 06:06:12 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016838918 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.4016838918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.590096148
Short name T687
Test name
Test status
Simulation time 214351140 ps
CPU time 4.81 seconds
Started Aug 25 06:06:10 AM UTC 24
Finished Aug 25 06:06:16 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590096148 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.590096148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.3960591351
Short name T820
Test name
Test status
Simulation time 5621702319 ps
CPU time 190.71 seconds
Started Aug 25 06:06:09 AM UTC 24
Finished Aug 25 06:09:24 AM UTC 24
Peak memory 1626312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960591351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3960591351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.1038655692
Short name T276
Test name
Test status
Simulation time 4971945810 ps
CPU time 13.49 seconds
Started Aug 25 06:06:28 AM UTC 24
Finished Aug 25 06:06:42 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038655692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1038655692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_override.665501692
Short name T149
Test name
Test status
Simulation time 29477674 ps
CPU time 1.03 seconds
Started Aug 25 06:06:07 AM UTC 24
Finished Aug 25 06:06:09 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665501692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.665501692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.350501443
Short name T688
Test name
Test status
Simulation time 240024600 ps
CPU time 4.2 seconds
Started Aug 25 06:06:11 AM UTC 24
Finished Aug 25 06:06:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350501443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.350501443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.1500015287
Short name T726
Test name
Test status
Simulation time 908622686 ps
CPU time 53.74 seconds
Started Aug 25 06:06:06 AM UTC 24
Finished Aug 25 06:07:01 AM UTC 24
Peak memory 262280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500015287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1500015287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.627151314
Short name T720
Test name
Test status
Simulation time 773755867 ps
CPU time 41.74 seconds
Started Aug 25 06:06:11 AM UTC 24
Finished Aug 25 06:06:55 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627151314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.627151314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.568713842
Short name T713
Test name
Test status
Simulation time 1760359250 ps
CPU time 14.77 seconds
Started Aug 25 06:06:25 AM UTC 24
Finished Aug 25 06:06:41 AM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=568713842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.568713842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.1276106445
Short name T698
Test name
Test status
Simulation time 191323159 ps
CPU time 2.31 seconds
Started Aug 25 06:06:23 AM UTC 24
Finished Aug 25 06:06:27 AM UTC 24
Peak memory 226616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276106
445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.1276106445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.2826964085
Short name T697
Test name
Test status
Simulation time 253239454 ps
CPU time 2.22 seconds
Started Aug 25 06:06:23 AM UTC 24
Finished Aug 25 06:06:26 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826964
085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.2826964085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.1262685058
Short name T705
Test name
Test status
Simulation time 2213385109 ps
CPU time 4.92 seconds
Started Aug 25 06:06:30 AM UTC 24
Finished Aug 25 06:06:36 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262685
058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar
ks_acq.1262685058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.1494593238
Short name T704
Test name
Test status
Simulation time 171615961 ps
CPU time 2.48 seconds
Started Aug 25 06:06:31 AM UTC 24
Finished Aug 25 06:06:34 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494593
238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark
s_tx.1494593238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.936832222
Short name T702
Test name
Test status
Simulation time 1426742619 ps
CPU time 5.53 seconds
Started Aug 25 06:06:27 AM UTC 24
Finished Aug 25 06:06:33 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9368322
22 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.936832222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.2280254132
Short name T701
Test name
Test status
Simulation time 2320805657 ps
CPU time 11.93 seconds
Started Aug 25 06:06:20 AM UTC 24
Finished Aug 25 06:06:33 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228025
4132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.2280254132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.772730220
Short name T931
Test name
Test status
Simulation time 16378090761 ps
CPU time 301.75 seconds
Started Aug 25 06:06:21 AM UTC 24
Finished Aug 25 06:11:28 AM UTC 24
Peak memory 3985556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=772730220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress
_wr.772730220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.551260993
Short name T711
Test name
Test status
Simulation time 994931611 ps
CPU time 5.17 seconds
Started Aug 25 06:06:34 AM UTC 24
Finished Aug 25 06:06:40 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5512609
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.551260993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.4242958002
Short name T710
Test name
Test status
Simulation time 1690193243 ps
CPU time 4.18 seconds
Started Aug 25 06:06:35 AM UTC 24
Finished Aug 25 06:06:40 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242958
002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.4242958002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.2520333547
Short name T707
Test name
Test status
Simulation time 607167891 ps
CPU time 2.12 seconds
Started Aug 25 06:06:35 AM UTC 24
Finished Aug 25 06:06:38 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520333
547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_txstretch.2520333547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_perf.374449183
Short name T703
Test name
Test status
Simulation time 729467764 ps
CPU time 8.7 seconds
Started Aug 25 06:06:24 AM UTC 24
Finished Aug 25 06:06:34 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744491
83 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.374449183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.428711138
Short name T709
Test name
Test status
Simulation time 414294863 ps
CPU time 4.09 seconds
Started Aug 25 06:06:34 AM UTC 24
Finished Aug 25 06:06:39 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287111
38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.428711138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.2658044261
Short name T724
Test name
Test status
Simulation time 2386255618 ps
CPU time 43.58 seconds
Started Aug 25 06:06:14 AM UTC 24
Finished Aug 25 06:06:59 AM UTC 24
Peak memory 227212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658044261 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.2658044261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.2342456054
Short name T1304
Test name
Test status
Simulation time 37085786282 ps
CPU time 837.25 seconds
Started Aug 25 06:06:25 AM UTC 24
Finished Aug 25 06:20:33 AM UTC 24
Peak memory 7299500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234245
6054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.2342456054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.1842834394
Short name T751
Test name
Test status
Simulation time 1574435817 ps
CPU time 85.66 seconds
Started Aug 25 06:06:17 AM UTC 24
Finished Aug 25 06:07:45 AM UTC 24
Peak memory 229100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842834394 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.1842834394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.4125966393
Short name T695
Test name
Test status
Simulation time 29239028337 ps
CPU time 8.89 seconds
Started Aug 25 06:06:15 AM UTC 24
Finished Aug 25 06:06:25 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125966393 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.4125966393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.2291049523
Short name T700
Test name
Test status
Simulation time 854643379 ps
CPU time 10.7 seconds
Started Aug 25 06:06:18 AM UTC 24
Finished Aug 25 06:06:30 AM UTC 24
Peak memory 233920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291049523 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.2291049523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.2243566138
Short name T708
Test name
Test status
Simulation time 1916892011 ps
CPU time 15.72 seconds
Started Aug 25 06:06:22 AM UTC 24
Finished Aug 25 06:06:39 AM UTC 24
Peak memory 232956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243566
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.2243566138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.757482818
Short name T714
Test name
Test status
Simulation time 259034806 ps
CPU time 7.9 seconds
Started Aug 25 06:06:33 AM UTC 24
Finished Aug 25 06:06:42 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7574828
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.757482818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_alert_test.961085256
Short name T741
Test name
Test status
Simulation time 38842233 ps
CPU time 0.79 seconds
Started Aug 25 06:07:13 AM UTC 24
Finished Aug 25 06:07:15 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961085256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.961085256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.3377147246
Short name T722
Test name
Test status
Simulation time 970279561 ps
CPU time 10.87 seconds
Started Aug 25 06:06:44 AM UTC 24
Finished Aug 25 06:06:56 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377147246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3377147246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.1173969540
Short name T719
Test name
Test status
Simulation time 279889602 ps
CPU time 7.74 seconds
Started Aug 25 06:06:42 AM UTC 24
Finished Aug 25 06:06:51 AM UTC 24
Peak memory 254044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173969540 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.1173969540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.1041185879
Short name T855
Test name
Test status
Simulation time 3216139670 ps
CPU time 203.71 seconds
Started Aug 25 06:06:42 AM UTC 24
Finished Aug 25 06:10:09 AM UTC 24
Peak memory 499872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041185879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1041185879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.3871129759
Short name T850
Test name
Test status
Simulation time 10387397798 ps
CPU time 200.05 seconds
Started Aug 25 06:06:40 AM UTC 24
Finished Aug 25 06:10:03 AM UTC 24
Peak memory 827852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871129759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3871129759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.2272596311
Short name T715
Test name
Test status
Simulation time 187171795 ps
CPU time 1.47 seconds
Started Aug 25 06:06:41 AM UTC 24
Finished Aug 25 06:06:43 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272596311 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.2272596311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.3515211498
Short name T718
Test name
Test status
Simulation time 337123996 ps
CPU time 6.49 seconds
Started Aug 25 06:06:42 AM UTC 24
Finished Aug 25 06:06:49 AM UTC 24
Peak memory 245844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515211498 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.3515211498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.861191348
Short name T968
Test name
Test status
Simulation time 16082619707 ps
CPU time 330.01 seconds
Started Aug 25 06:06:39 AM UTC 24
Finished Aug 25 06:12:15 AM UTC 24
Peak memory 1331420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861191348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.861191348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.3328606189
Short name T739
Test name
Test status
Simulation time 552689894 ps
CPU time 10.52 seconds
Started Aug 25 06:07:06 AM UTC 24
Finished Aug 25 06:07:18 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328606189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3328606189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_override.3097475332
Short name T712
Test name
Test status
Simulation time 17859668 ps
CPU time 0.96 seconds
Started Aug 25 06:06:39 AM UTC 24
Finished Aug 25 06:06:41 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097475332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3097475332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.879526474
Short name T717
Test name
Test status
Simulation time 98995974 ps
CPU time 1.55 seconds
Started Aug 25 06:06:43 AM UTC 24
Finished Aug 25 06:06:46 AM UTC 24
Peak memory 234548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879526474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.879526474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.2926596843
Short name T733
Test name
Test status
Simulation time 4255846858 ps
CPU time 29.08 seconds
Started Aug 25 06:06:39 AM UTC 24
Finished Aug 25 06:07:10 AM UTC 24
Peak memory 276948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926596843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2926596843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.3683215805
Short name T723
Test name
Test status
Simulation time 1309498456 ps
CPU time 12.91 seconds
Started Aug 25 06:06:43 AM UTC 24
Finished Aug 25 06:06:57 AM UTC 24
Peak memory 232972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683215805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3683215805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.1475722464
Short name T736
Test name
Test status
Simulation time 1812743074 ps
CPU time 7.54 seconds
Started Aug 25 06:07:03 AM UTC 24
Finished Aug 25 06:07:12 AM UTC 24
Peak memory 220660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1475722464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad
dr.1475722464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.3622225709
Short name T728
Test name
Test status
Simulation time 350947240 ps
CPU time 2.21 seconds
Started Aug 25 06:07:00 AM UTC 24
Finished Aug 25 06:07:03 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622225
709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.3622225709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.3628014396
Short name T164
Test name
Test status
Simulation time 608674219 ps
CPU time 2.49 seconds
Started Aug 25 06:07:02 AM UTC 24
Finished Aug 25 06:07:06 AM UTC 24
Peak memory 232968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628014
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.3628014396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.1506500024
Short name T738
Test name
Test status
Simulation time 367547227 ps
CPU time 4.14 seconds
Started Aug 25 06:07:07 AM UTC 24
Finished Aug 25 06:07:13 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506500
024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermar
ks_acq.1506500024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.1836582229
Short name T735
Test name
Test status
Simulation time 139844711 ps
CPU time 1.8 seconds
Started Aug 25 06:07:08 AM UTC 24
Finished Aug 25 06:07:12 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836582
229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark
s_tx.1836582229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.728060278
Short name T731
Test name
Test status
Simulation time 204981846 ps
CPU time 2.29 seconds
Started Aug 25 06:07:04 AM UTC 24
Finished Aug 25 06:07:08 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7280602
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.728060278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.212006875
Short name T730
Test name
Test status
Simulation time 2232373158 ps
CPU time 11.15 seconds
Started Aug 25 06:06:56 AM UTC 24
Finished Aug 25 06:07:08 AM UTC 24
Peak memory 233092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212006
875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.212006875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.3728892261
Short name T757
Test name
Test status
Simulation time 13858426369 ps
CPU time 57.93 seconds
Started Aug 25 06:06:57 AM UTC 24
Finished Aug 25 06:07:56 AM UTC 24
Peak memory 807132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3728892261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.3728892261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.3050187297
Short name T743
Test name
Test status
Simulation time 493436676 ps
CPU time 5.26 seconds
Started Aug 25 06:07:10 AM UTC 24
Finished Aug 25 06:07:16 AM UTC 24
Peak memory 227116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050187
297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.3050187297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.502471585
Short name T680
Test name
Test status
Simulation time 416841170 ps
CPU time 4.19 seconds
Started Aug 25 06:07:11 AM UTC 24
Finished Aug 25 06:07:16 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5024715
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.502471585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_perf.2181884767
Short name T732
Test name
Test status
Simulation time 4719078100 ps
CPU time 5.27 seconds
Started Aug 25 06:07:02 AM UTC 24
Finished Aug 25 06:07:08 AM UTC 24
Peak memory 226576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181884
767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.2181884767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.2029861775
Short name T740
Test name
Test status
Simulation time 1979803859 ps
CPU time 4.51 seconds
Started Aug 25 06:07:09 AM UTC 24
Finished Aug 25 06:07:15 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029861
775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.2029861775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.540463042
Short name T90
Test name
Test status
Simulation time 2047405020 ps
CPU time 16.51 seconds
Started Aug 25 06:06:45 AM UTC 24
Finished Aug 25 06:07:03 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540463042 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.540463042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.156668782
Short name T786
Test name
Test status
Simulation time 41765954396 ps
CPU time 90.08 seconds
Started Aug 25 06:07:02 AM UTC 24
Finished Aug 25 06:08:34 AM UTC 24
Peak memory 659340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156668
782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.156668782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.2906244502
Short name T691
Test name
Test status
Simulation time 1146250452 ps
CPU time 29.45 seconds
Started Aug 25 06:06:50 AM UTC 24
Finished Aug 25 06:07:21 AM UTC 24
Peak memory 249932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906244502 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.2906244502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.1629845019
Short name T767
Test name
Test status
Simulation time 36408443561 ps
CPU time 81.04 seconds
Started Aug 25 06:06:46 AM UTC 24
Finished Aug 25 06:08:09 AM UTC 24
Peak memory 1198232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629845019 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.1629845019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.1172292359
Short name T721
Test name
Test status
Simulation time 213849079 ps
CPU time 3.31 seconds
Started Aug 25 06:06:51 AM UTC 24
Finished Aug 25 06:06:56 AM UTC 24
Peak memory 225240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172292359 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.1172292359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.1907836864
Short name T734
Test name
Test status
Simulation time 2676152475 ps
CPU time 12.4 seconds
Started Aug 25 06:06:57 AM UTC 24
Finished Aug 25 06:07:10 AM UTC 24
Peak memory 243960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907836
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.1907836864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.2505432787
Short name T737
Test name
Test status
Simulation time 47150859 ps
CPU time 2.22 seconds
Started Aug 25 06:07:08 AM UTC 24
Finished Aug 25 06:07:12 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505432
787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2505432787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_alert_test.3108784552
Short name T101
Test name
Test status
Simulation time 34873292 ps
CPU time 0.89 seconds
Started Aug 25 05:55:48 AM UTC 24
Finished Aug 25 05:55:50 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108784552 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3108784552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.226164731
Short name T328
Test name
Test status
Simulation time 288788007 ps
CPU time 7.46 seconds
Started Aug 25 05:55:22 AM UTC 24
Finished Aug 25 05:55:31 AM UTC 24
Peak memory 276508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226164731 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.226164731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.3138250770
Short name T172
Test name
Test status
Simulation time 15011099488 ps
CPU time 185.56 seconds
Started Aug 25 05:55:23 AM UTC 24
Finished Aug 25 05:58:32 AM UTC 24
Peak memory 1046748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138250770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3138250770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.2662011886
Short name T191
Test name
Test status
Simulation time 2192960510 ps
CPU time 174.78 seconds
Started Aug 25 05:55:21 AM UTC 24
Finished Aug 25 05:58:20 AM UTC 24
Peak memory 762076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662011886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2662011886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.257318501
Short name T37
Test name
Test status
Simulation time 845829303 ps
CPU time 1.25 seconds
Started Aug 25 05:55:22 AM UTC 24
Finished Aug 25 05:55:24 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257318501 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.257318501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.3404674554
Short name T165
Test name
Test status
Simulation time 291675481 ps
CPU time 7.19 seconds
Started Aug 25 05:55:22 AM UTC 24
Finished Aug 25 05:55:30 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404674554 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.3404674554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.3317524790
Short name T413
Test name
Test status
Simulation time 6911506656 ps
CPU time 241.73 seconds
Started Aug 25 05:55:21 AM UTC 24
Finished Aug 25 05:59:27 AM UTC 24
Peak memory 1042592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317524790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3317524790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_mode_toggle.3281063863
Short name T26
Test name
Test status
Simulation time 430388529 ps
CPU time 4.81 seconds
Started Aug 25 05:55:38 AM UTC 24
Finished Aug 25 05:55:44 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281063863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3281063863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_override.2226131070
Short name T103
Test name
Test status
Simulation time 42636375 ps
CPU time 1.01 seconds
Started Aug 25 05:55:20 AM UTC 24
Finished Aug 25 05:55:22 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226131070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2226131070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2093491820
Short name T20
Test name
Test status
Simulation time 436310879 ps
CPU time 13.06 seconds
Started Aug 25 05:55:23 AM UTC 24
Finished Aug 25 05:55:37 AM UTC 24
Peak memory 311592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093491820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2093491820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.1209001016
Short name T327
Test name
Test status
Simulation time 64234921 ps
CPU time 2.34 seconds
Started Aug 25 05:55:23 AM UTC 24
Finished Aug 25 05:55:27 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209001016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.1209001016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.1457325872
Short name T342
Test name
Test status
Simulation time 2023984085 ps
CPU time 58.88 seconds
Started Aug 25 05:55:20 AM UTC 24
Finished Aug 25 05:56:21 AM UTC 24
Peak memory 313372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457325872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1457325872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.3993492734
Short name T229
Test name
Test status
Simulation time 698488771 ps
CPU time 10.86 seconds
Started Aug 25 05:55:23 AM UTC 24
Finished Aug 25 05:55:35 AM UTC 24
Peak memory 228752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993492734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3993492734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.2694230330
Short name T204
Test name
Test status
Simulation time 77050136 ps
CPU time 1.34 seconds
Started Aug 25 05:55:48 AM UTC 24
Finished Aug 25 05:55:50 AM UTC 24
Peak memory 246796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694230330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2694230330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3878564985
Short name T66
Test name
Test status
Simulation time 1332091046 ps
CPU time 10.05 seconds
Started Aug 25 05:55:36 AM UTC 24
Finished Aug 25 05:55:47 AM UTC 24
Peak memory 233160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3878564985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3878564985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.2354175770
Short name T9
Test name
Test status
Simulation time 184939097 ps
CPU time 1.79 seconds
Started Aug 25 05:55:35 AM UTC 24
Finished Aug 25 05:55:38 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354175
770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.2354175770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.2745638711
Short name T291
Test name
Test status
Simulation time 1799204199 ps
CPU time 4.58 seconds
Started Aug 25 05:55:41 AM UTC 24
Finished Aug 25 05:55:47 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745638
711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermark
s_acq.2745638711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.701418486
Short name T332
Test name
Test status
Simulation time 182926198 ps
CPU time 2.13 seconds
Started Aug 25 05:55:43 AM UTC 24
Finished Aug 25 05:55:47 AM UTC 24
Peak memory 216324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7014184
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.701418486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.342840830
Short name T330
Test name
Test status
Simulation time 21591805862 ps
CPU time 10.69 seconds
Started Aug 25 05:55:31 AM UTC 24
Finished Aug 25 05:55:43 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342840
830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.342840830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.1196216262
Short name T336
Test name
Test status
Simulation time 42528787777 ps
CPU time 31.27 seconds
Started Aug 25 05:55:32 AM UTC 24
Finished Aug 25 05:56:05 AM UTC 24
Peak memory 565352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1196216262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress
_wr.1196216262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2606886214
Short name T166
Test name
Test status
Simulation time 2110016723 ps
CPU time 3.99 seconds
Started Aug 25 05:55:46 AM UTC 24
Finished Aug 25 05:55:51 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606886
214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.2606886214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.301390037
Short name T68
Test name
Test status
Simulation time 1146837169 ps
CPU time 4.95 seconds
Started Aug 25 05:55:47 AM UTC 24
Finished Aug 25 05:55:53 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013900
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.301390037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.2436794919
Short name T60
Test name
Test status
Simulation time 264461442 ps
CPU time 2.42 seconds
Started Aug 25 05:55:47 AM UTC 24
Finished Aug 25 05:55:50 AM UTC 24
Peak memory 233480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436794
919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.2436794919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_perf.4127792269
Short name T331
Test name
Test status
Simulation time 1736981190 ps
CPU time 9.29 seconds
Started Aug 25 05:55:36 AM UTC 24
Finished Aug 25 05:55:47 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127792
269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.4127792269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.2420526290
Short name T334
Test name
Test status
Simulation time 1046550792 ps
CPU time 4.95 seconds
Started Aug 25 05:55:46 AM UTC 24
Finished Aug 25 05:55:52 AM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420526
290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.2420526290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.2911481088
Short name T5
Test name
Test status
Simulation time 2377484744 ps
CPU time 9.74 seconds
Started Aug 25 05:55:24 AM UTC 24
Finished Aug 25 05:55:35 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911481088 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.2911481088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.2806869054
Short name T254
Test name
Test status
Simulation time 5513710782 ps
CPU time 46.79 seconds
Started Aug 25 05:55:36 AM UTC 24
Finished Aug 25 05:56:25 AM UTC 24
Peak memory 266408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280686
9054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.2806869054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.804183675
Short name T286
Test name
Test status
Simulation time 1133084960 ps
CPU time 24.73 seconds
Started Aug 25 05:55:25 AM UTC 24
Finished Aug 25 05:55:52 AM UTC 24
Peak memory 243856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804183675 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.804183675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.4284150385
Short name T329
Test name
Test status
Simulation time 11624250045 ps
CPU time 13.43 seconds
Started Aug 25 05:55:25 AM UTC 24
Finished Aug 25 05:55:40 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284150385 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.4284150385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2684280776
Short name T6
Test name
Test status
Simulation time 1156395932 ps
CPU time 6.7 seconds
Started Aug 25 05:55:27 AM UTC 24
Finished Aug 25 05:55:36 AM UTC 24
Peak memory 297104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684280776 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.2684280776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.4017294606
Short name T77
Test name
Test status
Simulation time 1271620618 ps
CPU time 11.25 seconds
Started Aug 25 05:55:32 AM UTC 24
Finished Aug 25 05:55:44 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017294
606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.4017294606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3706136745
Short name T318
Test name
Test status
Simulation time 253324089 ps
CPU time 6.04 seconds
Started Aug 25 05:55:44 AM UTC 24
Finished Aug 25 05:55:52 AM UTC 24
Peak memory 233516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706136
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3706136745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_alert_test.826386476
Short name T766
Test name
Test status
Simulation time 22084406 ps
CPU time 0.93 seconds
Started Aug 25 06:08:06 AM UTC 24
Finished Aug 25 06:08:08 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826386476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.826386476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.2775059045
Short name T744
Test name
Test status
Simulation time 121149352 ps
CPU time 2.75 seconds
Started Aug 25 06:07:20 AM UTC 24
Finished Aug 25 06:07:23 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775059045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2775059045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.259579425
Short name T747
Test name
Test status
Simulation time 5216197875 ps
CPU time 12.63 seconds
Started Aug 25 06:07:15 AM UTC 24
Finished Aug 25 06:07:29 AM UTC 24
Peak memory 325712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259579425 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.259579425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.662035102
Short name T833
Test name
Test status
Simulation time 33189785971 ps
CPU time 137.5 seconds
Started Aug 25 06:07:16 AM UTC 24
Finished Aug 25 06:09:37 AM UTC 24
Peak memory 587936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662035102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.662035102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.1148479238
Short name T809
Test name
Test status
Simulation time 8722664088 ps
CPU time 101.52 seconds
Started Aug 25 06:07:15 AM UTC 24
Finished Aug 25 06:08:59 AM UTC 24
Peak memory 528856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148479238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1148479238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.135447698
Short name T684
Test name
Test status
Simulation time 171829458 ps
CPU time 1.18 seconds
Started Aug 25 06:07:15 AM UTC 24
Finished Aug 25 06:07:17 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135447698 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.135447698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.4286774492
Short name T725
Test name
Test status
Simulation time 108715031 ps
CPU time 3.59 seconds
Started Aug 25 06:07:16 AM UTC 24
Finished Aug 25 06:07:21 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286774492 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.4286774492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.3182147271
Short name T122
Test name
Test status
Simulation time 4903244598 ps
CPU time 141.74 seconds
Started Aug 25 06:07:14 AM UTC 24
Finished Aug 25 06:09:39 AM UTC 24
Peak memory 1421536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182147271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3182147271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.1132157916
Short name T280
Test name
Test status
Simulation time 932922701 ps
CPU time 9.27 seconds
Started Aug 25 06:07:56 AM UTC 24
Finished Aug 25 06:08:06 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132157916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1132157916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_override.1172481613
Short name T150
Test name
Test status
Simulation time 44748212 ps
CPU time 0.9 seconds
Started Aug 25 06:07:13 AM UTC 24
Finished Aug 25 06:07:15 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172481613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1172481613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_perf.2401322038
Short name T848
Test name
Test status
Simulation time 19437207850 ps
CPU time 161.82 seconds
Started Aug 25 06:07:17 AM UTC 24
Finished Aug 25 06:10:03 AM UTC 24
Peak memory 479652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401322038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2401322038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.3185353065
Short name T745
Test name
Test status
Simulation time 882246643 ps
CPU time 5.56 seconds
Started Aug 25 06:07:17 AM UTC 24
Finished Aug 25 06:07:24 AM UTC 24
Peak memory 258076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185353065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3185353065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.852925275
Short name T817
Test name
Test status
Simulation time 5500018226 ps
CPU time 124.74 seconds
Started Aug 25 06:07:13 AM UTC 24
Finished Aug 25 06:09:20 AM UTC 24
Peak memory 428164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852925275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.852925275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_stress_all.2971627312
Short name T1359
Test name
Test status
Simulation time 17623412041 ps
CPU time 853.23 seconds
Started Aug 25 06:07:22 AM UTC 24
Finished Aug 25 06:21:47 AM UTC 24
Peak memory 4337880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971627312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.2971627312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.1416736567
Short name T749
Test name
Test status
Simulation time 2953732941 ps
CPU time 17.46 seconds
Started Aug 25 06:07:18 AM UTC 24
Finished Aug 25 06:07:37 AM UTC 24
Peak memory 229004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416736567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1416736567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.2555291674
Short name T756
Test name
Test status
Simulation time 3317791115 ps
CPU time 5.79 seconds
Started Aug 25 06:07:49 AM UTC 24
Finished Aug 25 06:07:55 AM UTC 24
Peak memory 233196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2555291674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.2555291674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.3926895105
Short name T754
Test name
Test status
Simulation time 148921992 ps
CPU time 1.56 seconds
Started Aug 25 06:07:45 AM UTC 24
Finished Aug 25 06:07:48 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926895
105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.3926895105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.4249855581
Short name T761
Test name
Test status
Simulation time 2389517668 ps
CPU time 3.43 seconds
Started Aug 25 06:07:57 AM UTC 24
Finished Aug 25 06:08:01 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249855
581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermar
ks_acq.4249855581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.1977194230
Short name T760
Test name
Test status
Simulation time 265496385 ps
CPU time 1.66 seconds
Started Aug 25 06:07:57 AM UTC 24
Finished Aug 25 06:08:00 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977194
230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_tx.1977194230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.3840073499
Short name T750
Test name
Test status
Simulation time 993930652 ps
CPU time 10.38 seconds
Started Aug 25 06:07:30 AM UTC 24
Finished Aug 25 06:07:42 AM UTC 24
Peak memory 243792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384007
3499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.3840073499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.1204470290
Short name T980
Test name
Test status
Simulation time 18517923970 ps
CPU time 299.06 seconds
Started Aug 25 06:07:33 AM UTC 24
Finished Aug 25 06:12:37 AM UTC 24
Peak memory 3074200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1204470290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres
s_wr.1204470290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.363061186
Short name T763
Test name
Test status
Simulation time 1069872974 ps
CPU time 4.72 seconds
Started Aug 25 06:08:00 AM UTC 24
Finished Aug 25 06:08:06 AM UTC 24
Peak memory 226852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630611
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.363061186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.657473045
Short name T765
Test name
Test status
Simulation time 529984276 ps
CPU time 4.92 seconds
Started Aug 25 06:08:02 AM UTC 24
Finished Aug 25 06:08:08 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6574730
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.657473045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.1115074273
Short name T769
Test name
Test status
Simulation time 143228486 ps
CPU time 2.44 seconds
Started Aug 25 06:08:06 AM UTC 24
Finished Aug 25 06:08:10 AM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115074
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.1115074273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_perf.3459055923
Short name T758
Test name
Test status
Simulation time 3294893325 ps
CPU time 8.03 seconds
Started Aug 25 06:07:47 AM UTC 24
Finished Aug 25 06:07:57 AM UTC 24
Peak memory 233772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459055
923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.3459055923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.4254882579
Short name T762
Test name
Test status
Simulation time 484518725 ps
CPU time 4.42 seconds
Started Aug 25 06:08:00 AM UTC 24
Finished Aug 25 06:08:06 AM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254882
579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.4254882579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.4109771956
Short name T753
Test name
Test status
Simulation time 5315406732 ps
CPU time 22.63 seconds
Started Aug 25 06:07:23 AM UTC 24
Finished Aug 25 06:07:47 AM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109771956 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.4109771956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.1112250761
Short name T1229
Test name
Test status
Simulation time 43521810275 ps
CPU time 658.52 seconds
Started Aug 25 06:07:49 AM UTC 24
Finished Aug 25 06:18:56 AM UTC 24
Peak memory 4325600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111225
0761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.1112250761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.117229502
Short name T811
Test name
Test status
Simulation time 3322144331 ps
CPU time 95.86 seconds
Started Aug 25 06:07:25 AM UTC 24
Finished Aug 25 06:09:03 AM UTC 24
Peak memory 228916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117229502 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.117229502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2804169328
Short name T759
Test name
Test status
Simulation time 13868562529 ps
CPU time 32.94 seconds
Started Aug 25 06:07:25 AM UTC 24
Finished Aug 25 06:07:59 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804169328 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.2804169328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.3135247055
Short name T748
Test name
Test status
Simulation time 606536680 ps
CPU time 1.72 seconds
Started Aug 25 06:07:29 AM UTC 24
Finished Aug 25 06:07:32 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135247055 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.3135247055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.3666991847
Short name T755
Test name
Test status
Simulation time 2379475012 ps
CPU time 10.86 seconds
Started Aug 25 06:07:38 AM UTC 24
Finished Aug 25 06:07:50 AM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666991
847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.3666991847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.1035299087
Short name T315
Test name
Test status
Simulation time 1013950659 ps
CPU time 19.2 seconds
Started Aug 25 06:07:59 AM UTC 24
Finished Aug 25 06:08:20 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035299
087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1035299087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_alert_test.3322969750
Short name T799
Test name
Test status
Simulation time 73088463 ps
CPU time 0.92 seconds
Started Aug 25 06:08:42 AM UTC 24
Finished Aug 25 06:08:44 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322969750 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3322969750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.1073996749
Short name T775
Test name
Test status
Simulation time 93473730 ps
CPU time 4.74 seconds
Started Aug 25 06:08:13 AM UTC 24
Finished Aug 25 06:08:19 AM UTC 24
Peak memory 233776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073996749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1073996749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.1200487064
Short name T778
Test name
Test status
Simulation time 207149180 ps
CPU time 13.31 seconds
Started Aug 25 06:08:11 AM UTC 24
Finished Aug 25 06:08:25 AM UTC 24
Peak memory 254048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200487064 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.1200487064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.2838037735
Short name T919
Test name
Test status
Simulation time 6055667023 ps
CPU time 186.99 seconds
Started Aug 25 06:08:11 AM UTC 24
Finished Aug 25 06:11:22 AM UTC 24
Peak memory 399624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838037735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2838037735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.3232815101
Short name T905
Test name
Test status
Simulation time 7580112674 ps
CPU time 174.57 seconds
Started Aug 25 06:08:10 AM UTC 24
Finished Aug 25 06:11:08 AM UTC 24
Peak memory 698608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232815101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3232815101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.2157010377
Short name T772
Test name
Test status
Simulation time 184126902 ps
CPU time 1.45 seconds
Started Aug 25 06:08:10 AM UTC 24
Finished Aug 25 06:08:12 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157010377 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.2157010377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.2729736990
Short name T780
Test name
Test status
Simulation time 206262200 ps
CPU time 14.54 seconds
Started Aug 25 06:08:11 AM UTC 24
Finished Aug 25 06:08:27 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729736990 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.2729736990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.335457869
Short name T877
Test name
Test status
Simulation time 17003250306 ps
CPU time 137.6 seconds
Started Aug 25 06:08:10 AM UTC 24
Finished Aug 25 06:10:30 AM UTC 24
Peak memory 1306836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335457869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.335457869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.1045761564
Short name T806
Test name
Test status
Simulation time 5238207239 ps
CPU time 18.66 seconds
Started Aug 25 06:08:35 AM UTC 24
Finished Aug 25 06:08:56 AM UTC 24
Peak memory 217012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045761564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1045761564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_override.577481993
Short name T771
Test name
Test status
Simulation time 25406698 ps
CPU time 1.07 seconds
Started Aug 25 06:08:09 AM UTC 24
Finished Aug 25 06:08:11 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577481993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.577481993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_perf.2199924690
Short name T969
Test name
Test status
Simulation time 77514980269 ps
CPU time 246.18 seconds
Started Aug 25 06:08:11 AM UTC 24
Finished Aug 25 06:12:22 AM UTC 24
Peak memory 846024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199924690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2199924690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.2819378912
Short name T774
Test name
Test status
Simulation time 189087968 ps
CPU time 5.17 seconds
Started Aug 25 06:08:12 AM UTC 24
Finished Aug 25 06:08:18 AM UTC 24
Peak memory 247904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819378912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.2819378912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.1026670219
Short name T842
Test name
Test status
Simulation time 11607739421 ps
CPU time 106.05 seconds
Started Aug 25 06:08:07 AM UTC 24
Finished Aug 25 06:09:56 AM UTC 24
Peak memory 403716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026670219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1026670219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.59256606
Short name T779
Test name
Test status
Simulation time 1935658832 ps
CPU time 12.09 seconds
Started Aug 25 06:08:12 AM UTC 24
Finished Aug 25 06:08:26 AM UTC 24
Peak memory 230896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59256606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.59256606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.4201050679
Short name T794
Test name
Test status
Simulation time 2639462215 ps
CPU time 5.59 seconds
Started Aug 25 06:08:34 AM UTC 24
Finished Aug 25 06:08:41 AM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4201050679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_ad
dr.4201050679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.3361799739
Short name T789
Test name
Test status
Simulation time 852261502 ps
CPU time 3.1 seconds
Started Aug 25 06:08:31 AM UTC 24
Finished Aug 25 06:08:35 AM UTC 24
Peak memory 230988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361799
739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.3361799739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.3084261228
Short name T787
Test name
Test status
Simulation time 223809880 ps
CPU time 2.42 seconds
Started Aug 25 06:08:31 AM UTC 24
Finished Aug 25 06:08:35 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084261
228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.3084261228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.2608065738
Short name T797
Test name
Test status
Simulation time 502273378 ps
CPU time 5.14 seconds
Started Aug 25 06:08:36 AM UTC 24
Finished Aug 25 06:08:42 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608065
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermar
ks_acq.2608065738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.3746333453
Short name T792
Test name
Test status
Simulation time 299492190 ps
CPU time 2.52 seconds
Started Aug 25 06:08:37 AM UTC 24
Finished Aug 25 06:08:40 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746333
453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.3746333453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.3306084068
Short name T791
Test name
Test status
Simulation time 720760969 ps
CPU time 2.22 seconds
Started Aug 25 06:08:34 AM UTC 24
Finished Aug 25 06:08:38 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306084
068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.3306084068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.638352992
Short name T783
Test name
Test status
Simulation time 941947530 ps
CPU time 7.74 seconds
Started Aug 25 06:08:22 AM UTC 24
Finished Aug 25 06:08:31 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638352
992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.638352992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.3077574275
Short name T784
Test name
Test status
Simulation time 5005697671 ps
CPU time 6.79 seconds
Started Aug 25 06:08:26 AM UTC 24
Finished Aug 25 06:08:34 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3077574275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.3077574275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.1391390616
Short name T801
Test name
Test status
Simulation time 7640809818 ps
CPU time 3.65 seconds
Started Aug 25 06:08:41 AM UTC 24
Finished Aug 25 06:08:46 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391390
616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.1391390616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.1678014932
Short name T802
Test name
Test status
Simulation time 637338793 ps
CPU time 5.3 seconds
Started Aug 25 06:08:41 AM UTC 24
Finished Aug 25 06:08:47 AM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678014
932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_ad
dr.1678014932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.3376346606
Short name T800
Test name
Test status
Simulation time 330179737 ps
CPU time 2.31 seconds
Started Aug 25 06:08:42 AM UTC 24
Finished Aug 25 06:08:45 AM UTC 24
Peak memory 233272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376346
606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.3376346606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_perf.3641859236
Short name T795
Test name
Test status
Simulation time 1630450467 ps
CPU time 7.89 seconds
Started Aug 25 06:08:32 AM UTC 24
Finished Aug 25 06:08:42 AM UTC 24
Peak memory 228796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641859
236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.3641859236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.3236049255
Short name T798
Test name
Test status
Simulation time 503462473 ps
CPU time 3.67 seconds
Started Aug 25 06:08:39 AM UTC 24
Finished Aug 25 06:08:44 AM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236049
255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.3236049255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.3562152911
Short name T790
Test name
Test status
Simulation time 3148133308 ps
CPU time 16.52 seconds
Started Aug 25 06:08:19 AM UTC 24
Finished Aug 25 06:08:37 AM UTC 24
Peak memory 227048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562152911 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.3562152911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.2714356587
Short name T913
Test name
Test status
Simulation time 36958422809 ps
CPU time 159.18 seconds
Started Aug 25 06:08:32 AM UTC 24
Finished Aug 25 06:11:15 AM UTC 24
Peak memory 2033868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271435
6587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.2714356587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.1052849041
Short name T837
Test name
Test status
Simulation time 2882398574 ps
CPU time 80.68 seconds
Started Aug 25 06:08:21 AM UTC 24
Finished Aug 25 06:09:43 AM UTC 24
Peak memory 228868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052849041 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.1052849041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.480720514
Short name T785
Test name
Test status
Simulation time 12045279669 ps
CPU time 13.16 seconds
Started Aug 25 06:08:20 AM UTC 24
Finished Aug 25 06:08:34 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480720514 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.480720514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.1029973916
Short name T840
Test name
Test status
Simulation time 3523152806 ps
CPU time 85.8 seconds
Started Aug 25 06:08:21 AM UTC 24
Finished Aug 25 06:09:48 AM UTC 24
Peak memory 598348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029973916 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.1029973916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.1197508463
Short name T796
Test name
Test status
Simulation time 6051476686 ps
CPU time 13.66 seconds
Started Aug 25 06:08:27 AM UTC 24
Finished Aug 25 06:08:42 AM UTC 24
Peak memory 243944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197508
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.1197508463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2951866496
Short name T805
Test name
Test status
Simulation time 995663958 ps
CPU time 16 seconds
Started Aug 25 06:08:38 AM UTC 24
Finished Aug 25 06:08:55 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951866
496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2951866496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_alert_test.2584429038
Short name T824
Test name
Test status
Simulation time 51155654 ps
CPU time 1.02 seconds
Started Aug 25 06:09:25 AM UTC 24
Finished Aug 25 06:09:27 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584429038 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2584429038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.4064225016
Short name T812
Test name
Test status
Simulation time 762475067 ps
CPU time 7.31 seconds
Started Aug 25 06:08:56 AM UTC 24
Finished Aug 25 06:09:04 AM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064225016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.4064225016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.2790021876
Short name T808
Test name
Test status
Simulation time 998412181 ps
CPU time 11.22 seconds
Started Aug 25 06:08:47 AM UTC 24
Finished Aug 25 06:08:59 AM UTC 24
Peak memory 299296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790021876 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.2790021876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.1187502710
Short name T881
Test name
Test status
Simulation time 6048335014 ps
CPU time 105.22 seconds
Started Aug 25 06:08:47 AM UTC 24
Finished Aug 25 06:10:34 AM UTC 24
Peak memory 530836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187502710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1187502710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.1953207505
Short name T949
Test name
Test status
Simulation time 9873242994 ps
CPU time 189.7 seconds
Started Aug 25 06:08:44 AM UTC 24
Finished Aug 25 06:11:58 AM UTC 24
Peak memory 811472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953207505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1953207505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.2996830203
Short name T803
Test name
Test status
Simulation time 419601823 ps
CPU time 1.65 seconds
Started Aug 25 06:08:44 AM UTC 24
Finished Aug 25 06:08:48 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996830203 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.2996830203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.1015690145
Short name T807
Test name
Test status
Simulation time 198570518 ps
CPU time 8.81 seconds
Started Aug 25 06:08:47 AM UTC 24
Finished Aug 25 06:08:57 AM UTC 24
Peak memory 237704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015690145 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.1015690145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.3046511945
Short name T123
Test name
Test status
Simulation time 11578825317 ps
CPU time 76.11 seconds
Started Aug 25 06:08:43 AM UTC 24
Finished Aug 25 06:10:02 AM UTC 24
Peak memory 909524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046511945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3046511945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.921034967
Short name T835
Test name
Test status
Simulation time 4141986972 ps
CPU time 21.54 seconds
Started Aug 25 06:09:19 AM UTC 24
Finished Aug 25 06:09:42 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921034967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.921034967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_override.2073705362
Short name T151
Test name
Test status
Simulation time 28579197 ps
CPU time 1.1 seconds
Started Aug 25 06:08:43 AM UTC 24
Finished Aug 25 06:08:46 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073705362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2073705362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_perf.2918902028
Short name T1197
Test name
Test status
Simulation time 7551868596 ps
CPU time 565.08 seconds
Started Aug 25 06:08:49 AM UTC 24
Finished Aug 25 06:18:22 AM UTC 24
Peak memory 1636512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918902028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2918902028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.1187312980
Short name T1749
Test name
Test status
Simulation time 24361868283 ps
CPU time 2565.61 seconds
Started Aug 25 06:08:49 AM UTC 24
Finished Aug 25 06:52:04 AM UTC 24
Peak memory 4055500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187312980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1187312980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.3490442306
Short name T868
Test name
Test status
Simulation time 7226980707 ps
CPU time 89.47 seconds
Started Aug 25 06:08:43 AM UTC 24
Finished Aug 25 06:10:15 AM UTC 24
Peak memory 364928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490442306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3490442306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_stress_all.2957390243
Short name T264
Test name
Test status
Simulation time 53518571235 ps
CPU time 589.34 seconds
Started Aug 25 06:08:56 AM UTC 24
Finished Aug 25 06:18:53 AM UTC 24
Peak memory 3027236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957390243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2957390243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.736168964
Short name T832
Test name
Test status
Simulation time 596700399 ps
CPU time 39.09 seconds
Started Aug 25 06:08:55 AM UTC 24
Finished Aug 25 06:09:36 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736168964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.736168964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.1608577958
Short name T819
Test name
Test status
Simulation time 3501794647 ps
CPU time 9.11 seconds
Started Aug 25 06:09:13 AM UTC 24
Finished Aug 25 06:09:23 AM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1608577958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_ad
dr.1608577958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.3677225783
Short name T813
Test name
Test status
Simulation time 152298552 ps
CPU time 1.43 seconds
Started Aug 25 06:09:06 AM UTC 24
Finished Aug 25 06:09:08 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677225
783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.3677225783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.392545326
Short name T815
Test name
Test status
Simulation time 772638133 ps
CPU time 2.41 seconds
Started Aug 25 06:09:09 AM UTC 24
Finished Aug 25 06:09:12 AM UTC 24
Peak memory 218640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925453
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.392545326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.2260456391
Short name T823
Test name
Test status
Simulation time 1630163821 ps
CPU time 3.32 seconds
Started Aug 25 06:09:21 AM UTC 24
Finished Aug 25 06:09:26 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260456
391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermar
ks_acq.2260456391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.2063252233
Short name T821
Test name
Test status
Simulation time 101971836 ps
CPU time 1.7 seconds
Started Aug 25 06:09:21 AM UTC 24
Finished Aug 25 06:09:24 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063252
233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_tx.2063252233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.2057806109
Short name T814
Test name
Test status
Simulation time 1020223123 ps
CPU time 10.09 seconds
Started Aug 25 06:09:00 AM UTC 24
Finished Aug 25 06:09:12 AM UTC 24
Peak memory 233364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205780
6109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.2057806109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.3615990875
Short name T818
Test name
Test status
Simulation time 3242975108 ps
CPU time 17.14 seconds
Started Aug 25 06:09:05 AM UTC 24
Finished Aug 25 06:09:23 AM UTC 24
Peak memory 561368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3615990875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.3615990875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.2977508529
Short name T830
Test name
Test status
Simulation time 542681188 ps
CPU time 4.62 seconds
Started Aug 25 06:09:25 AM UTC 24
Finished Aug 25 06:09:30 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977508
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.2977508529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.378894424
Short name T828
Test name
Test status
Simulation time 883038139 ps
CPU time 4.15 seconds
Started Aug 25 06:09:25 AM UTC 24
Finished Aug 25 06:09:30 AM UTC 24
Peak memory 216096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788944
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.378894424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.2515674770
Short name T826
Test name
Test status
Simulation time 507281783 ps
CPU time 2.65 seconds
Started Aug 25 06:09:25 AM UTC 24
Finished Aug 25 06:09:28 AM UTC 24
Peak memory 232880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515674
770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.2515674770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_perf.4024491620
Short name T768
Test name
Test status
Simulation time 3211839165 ps
CPU time 9.04 seconds
Started Aug 25 06:09:10 AM UTC 24
Finished Aug 25 06:09:20 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024491
620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.4024491620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.2407915927
Short name T827
Test name
Test status
Simulation time 489861571 ps
CPU time 4.67 seconds
Started Aug 25 06:09:24 AM UTC 24
Finished Aug 25 06:09:29 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407915
927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.2407915927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.4199904522
Short name T764
Test name
Test status
Simulation time 2358275039 ps
CPU time 18.68 seconds
Started Aug 25 06:08:57 AM UTC 24
Finished Aug 25 06:09:17 AM UTC 24
Peak memory 227188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199904522 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.4199904522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.1210477522
Short name T1156
Test name
Test status
Simulation time 57779402171 ps
CPU time 464.2 seconds
Started Aug 25 06:09:13 AM UTC 24
Finished Aug 25 06:17:04 AM UTC 24
Peak memory 3002668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121047
7522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.1210477522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.923632726
Short name T825
Test name
Test status
Simulation time 1988502679 ps
CPU time 26.78 seconds
Started Aug 25 06:08:59 AM UTC 24
Finished Aug 25 06:09:27 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923632726 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.923632726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.2857304550
Short name T816
Test name
Test status
Simulation time 27223387220 ps
CPU time 16.07 seconds
Started Aug 25 06:08:58 AM UTC 24
Finished Aug 25 06:09:16 AM UTC 24
Peak memory 274644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857304550 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.2857304550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.3106440722
Short name T822
Test name
Test status
Simulation time 2260208842 ps
CPU time 22.41 seconds
Started Aug 25 06:09:00 AM UTC 24
Finished Aug 25 06:09:24 AM UTC 24
Peak memory 436436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106440722 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.3106440722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.637135120
Short name T781
Test name
Test status
Simulation time 1547042871 ps
CPU time 12.71 seconds
Started Aug 25 06:09:05 AM UTC 24
Finished Aug 25 06:09:19 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6371351
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.637135120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.4202853503
Short name T836
Test name
Test status
Simulation time 1140286518 ps
CPU time 19.56 seconds
Started Aug 25 06:09:22 AM UTC 24
Finished Aug 25 06:09:43 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202853
503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.4202853503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_alert_test.2644119921
Short name T861
Test name
Test status
Simulation time 26927891 ps
CPU time 1.03 seconds
Started Aug 25 06:10:11 AM UTC 24
Finished Aug 25 06:10:13 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644119921 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2644119921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.2731993205
Short name T838
Test name
Test status
Simulation time 185613730 ps
CPU time 2.93 seconds
Started Aug 25 06:09:40 AM UTC 24
Finished Aug 25 06:09:44 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731993205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2731993205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.3971597265
Short name T846
Test name
Test status
Simulation time 2212072162 ps
CPU time 27.62 seconds
Started Aug 25 06:09:31 AM UTC 24
Finished Aug 25 06:10:00 AM UTC 24
Peak memory 307612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971597265 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.3971597265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.992769633
Short name T1016
Test name
Test status
Simulation time 7179150886 ps
CPU time 235.44 seconds
Started Aug 25 06:09:31 AM UTC 24
Finished Aug 25 06:13:31 AM UTC 24
Peak memory 629004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992769633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.992769633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.38749383
Short name T903
Test name
Test status
Simulation time 9487154432 ps
CPU time 91.01 seconds
Started Aug 25 06:09:29 AM UTC 24
Finished Aug 25 06:11:02 AM UTC 24
Peak memory 772432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38749383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.38749383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.2628673447
Short name T831
Test name
Test status
Simulation time 126377983 ps
CPU time 1.51 seconds
Started Aug 25 06:09:30 AM UTC 24
Finished Aug 25 06:09:33 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628673447 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.2628673447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.2980578906
Short name T839
Test name
Test status
Simulation time 471692402 ps
CPU time 11.45 seconds
Started Aug 25 06:09:31 AM UTC 24
Finished Aug 25 06:09:44 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980578906 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.2980578906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.52832759
Short name T1087
Test name
Test status
Simulation time 19726793988 ps
CPU time 361.42 seconds
Started Aug 25 06:09:28 AM UTC 24
Finished Aug 25 06:15:35 AM UTC 24
Peak memory 1427600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52832759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.52832759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.3023235671
Short name T859
Test name
Test status
Simulation time 1278090980 ps
CPU time 6.46 seconds
Started Aug 25 06:10:04 AM UTC 24
Finished Aug 25 06:10:12 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023235671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3023235671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_override.4213955577
Short name T829
Test name
Test status
Simulation time 74289809 ps
CPU time 1.08 seconds
Started Aug 25 06:09:28 AM UTC 24
Finished Aug 25 06:09:30 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213955577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4213955577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_perf.3493823634
Short name T1736
Test name
Test status
Simulation time 31256820960 ps
CPU time 1588.92 seconds
Started Aug 25 06:09:34 AM UTC 24
Finished Aug 25 06:36:22 AM UTC 24
Peak memory 4227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493823634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3493823634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.226656693
Short name T834
Test name
Test status
Simulation time 101019390 ps
CPU time 1.37 seconds
Started Aug 25 06:09:37 AM UTC 24
Finished Aug 25 06:09:39 AM UTC 24
Peak memory 236532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226656693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.226656693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.2666015741
Short name T841
Test name
Test status
Simulation time 2787872836 ps
CPU time 22.4 seconds
Started Aug 25 06:09:27 AM UTC 24
Finished Aug 25 06:09:51 AM UTC 24
Peak memory 293104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666015741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2666015741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.4000273449
Short name T263
Test name
Test status
Simulation time 71643312152 ps
CPU time 426.71 seconds
Started Aug 25 06:09:40 AM UTC 24
Finished Aug 25 06:16:53 AM UTC 24
Peak memory 1919160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000273449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.4000273449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.688803735
Short name T874
Test name
Test status
Simulation time 855929033 ps
CPU time 47.52 seconds
Started Aug 25 06:09:38 AM UTC 24
Finished Aug 25 06:10:27 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688803735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.688803735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.3952284412
Short name T860
Test name
Test status
Simulation time 1243815154 ps
CPU time 9.49 seconds
Started Aug 25 06:10:02 AM UTC 24
Finished Aug 25 06:10:12 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3952284412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_ad
dr.3952284412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.2923616153
Short name T849
Test name
Test status
Simulation time 241590889 ps
CPU time 1.11 seconds
Started Aug 25 06:10:01 AM UTC 24
Finished Aug 25 06:10:03 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923616
153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.2923616153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.1545992718
Short name T851
Test name
Test status
Simulation time 199650293 ps
CPU time 2.15 seconds
Started Aug 25 06:10:01 AM UTC 24
Finished Aug 25 06:10:04 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545992
718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.1545992718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.95851460
Short name T857
Test name
Test status
Simulation time 2209824910 ps
CPU time 5.19 seconds
Started Aug 25 06:10:04 AM UTC 24
Finished Aug 25 06:10:10 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9585146
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermarks
_acq.95851460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.2669895343
Short name T854
Test name
Test status
Simulation time 266272122 ps
CPU time 1.94 seconds
Started Aug 25 06:10:05 AM UTC 24
Finished Aug 25 06:10:08 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669895
343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.2669895343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.133578060
Short name T853
Test name
Test status
Simulation time 796429386 ps
CPU time 3.67 seconds
Started Aug 25 06:10:03 AM UTC 24
Finished Aug 25 06:10:08 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335780
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.133578060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.3748947614
Short name T847
Test name
Test status
Simulation time 6050207346 ps
CPU time 14.8 seconds
Started Aug 25 06:09:45 AM UTC 24
Finished Aug 25 06:10:01 AM UTC 24
Peak memory 233204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374894
7614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.3748947614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.1450939550
Short name T886
Test name
Test status
Simulation time 4228254501 ps
CPU time 48.08 seconds
Started Aug 25 06:09:49 AM UTC 24
Finished Aug 25 06:10:39 AM UTC 24
Peak memory 1188312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1450939550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stres
s_wr.1450939550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.1149077106
Short name T863
Test name
Test status
Simulation time 2068672288 ps
CPU time 4.4 seconds
Started Aug 25 06:10:08 AM UTC 24
Finished Aug 25 06:10:14 AM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149077
106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.1149077106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.2093758717
Short name T869
Test name
Test status
Simulation time 2416586839 ps
CPU time 4.45 seconds
Started Aug 25 06:10:09 AM UTC 24
Finished Aug 25 06:10:15 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093758
717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_ad
dr.2093758717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_perf.4076905881
Short name T856
Test name
Test status
Simulation time 1130118436 ps
CPU time 7.67 seconds
Started Aug 25 06:10:01 AM UTC 24
Finished Aug 25 06:10:10 AM UTC 24
Peak memory 229120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076905
881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.4076905881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.1605619440
Short name T862
Test name
Test status
Simulation time 2133498116 ps
CPU time 4.37 seconds
Started Aug 25 06:10:08 AM UTC 24
Finished Aug 25 06:10:14 AM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605619
440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.1605619440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.654307440
Short name T845
Test name
Test status
Simulation time 1810583827 ps
CPU time 15.11 seconds
Started Aug 25 06:09:43 AM UTC 24
Finished Aug 25 06:09:59 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654307440 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.654307440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.3573442194
Short name T1004
Test name
Test status
Simulation time 26412099352 ps
CPU time 178.44 seconds
Started Aug 25 06:10:02 AM UTC 24
Finished Aug 25 06:13:03 AM UTC 24
Peak memory 1796308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357344
2194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.3573442194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.1414471357
Short name T858
Test name
Test status
Simulation time 478161329 ps
CPU time 25.41 seconds
Started Aug 25 06:09:44 AM UTC 24
Finished Aug 25 06:10:11 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414471357 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.1414471357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.3984552478
Short name T1549
Test name
Test status
Simulation time 59250281676 ps
CPU time 1398.99 seconds
Started Aug 25 06:09:44 AM UTC 24
Finished Aug 25 06:33:20 AM UTC 24
Peak memory 8958164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984552478 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.3984552478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.4162221979
Short name T985
Test name
Test status
Simulation time 3703468085 ps
CPU time 173.78 seconds
Started Aug 25 06:09:45 AM UTC 24
Finished Aug 25 06:12:43 AM UTC 24
Peak memory 1096012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162221979 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.4162221979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.3190347744
Short name T852
Test name
Test status
Simulation time 1513172694 ps
CPU time 12.23 seconds
Started Aug 25 06:09:51 AM UTC 24
Finished Aug 25 06:10:05 AM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190347
744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.3190347744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.4133554914
Short name T864
Test name
Test status
Simulation time 243334497 ps
CPU time 6.72 seconds
Started Aug 25 06:10:06 AM UTC 24
Finished Aug 25 06:10:14 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133554
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.4133554914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_alert_test.543798364
Short name T867
Test name
Test status
Simulation time 98778657 ps
CPU time 0.94 seconds
Started Aug 25 06:10:43 AM UTC 24
Finished Aug 25 06:10:45 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543798364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.543798364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.4219906465
Short name T871
Test name
Test status
Simulation time 157175447 ps
CPU time 1.81 seconds
Started Aug 25 06:10:16 AM UTC 24
Finished Aug 25 06:10:19 AM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219906465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.4219906465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.251579018
Short name T875
Test name
Test status
Simulation time 864265670 ps
CPU time 13.46 seconds
Started Aug 25 06:10:14 AM UTC 24
Finished Aug 25 06:10:29 AM UTC 24
Peak memory 313628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251579018 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.251579018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.285928897
Short name T930
Test name
Test status
Simulation time 1936413200 ps
CPU time 117.53 seconds
Started Aug 25 06:10:15 AM UTC 24
Finished Aug 25 06:12:16 AM UTC 24
Peak memory 288844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285928897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.285928897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.2136722418
Short name T907
Test name
Test status
Simulation time 2594939989 ps
CPU time 55 seconds
Started Aug 25 06:10:13 AM UTC 24
Finished Aug 25 06:11:10 AM UTC 24
Peak memory 561312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136722418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2136722418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.1323047798
Short name T870
Test name
Test status
Simulation time 511104293 ps
CPU time 2.01 seconds
Started Aug 25 06:10:14 AM UTC 24
Finished Aug 25 06:10:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323047798 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.1323047798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.2961942637
Short name T873
Test name
Test status
Simulation time 161347256 ps
CPU time 8.9 seconds
Started Aug 25 06:10:15 AM UTC 24
Finished Aug 25 06:10:25 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961942637 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.2961942637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3389283326
Short name T961
Test name
Test status
Simulation time 28079424990 ps
CPU time 112.03 seconds
Started Aug 25 06:10:12 AM UTC 24
Finished Aug 25 06:12:07 AM UTC 24
Peak memory 1151180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389283326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3389283326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3437771920
Short name T904
Test name
Test status
Simulation time 1000720353 ps
CPU time 27.27 seconds
Started Aug 25 06:10:36 AM UTC 24
Finished Aug 25 06:11:04 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437771920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3437771920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_mode_toggle.1983090739
Short name T885
Test name
Test status
Simulation time 595498497 ps
CPU time 2.35 seconds
Started Aug 25 06:10:36 AM UTC 24
Finished Aug 25 06:10:39 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983090739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1983090739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_override.293903094
Short name T865
Test name
Test status
Simulation time 30018804 ps
CPU time 1.11 seconds
Started Aug 25 06:10:12 AM UTC 24
Finished Aug 25 06:10:14 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293903094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.293903094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_perf.170313959
Short name T1176
Test name
Test status
Simulation time 50294043716 ps
CPU time 440.3 seconds
Started Aug 25 06:10:15 AM UTC 24
Finished Aug 25 06:17:43 AM UTC 24
Peak memory 1407180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170313959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.170313959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.4003997716
Short name T872
Test name
Test status
Simulation time 259216081 ps
CPU time 3.31 seconds
Started Aug 25 06:10:15 AM UTC 24
Finished Aug 25 06:10:20 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003997716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.4003997716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.943108642
Short name T953
Test name
Test status
Simulation time 1750240863 ps
CPU time 104.99 seconds
Started Aug 25 06:10:12 AM UTC 24
Finished Aug 25 06:12:00 AM UTC 24
Peak memory 403468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943108642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.943108642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.3336077481
Short name T902
Test name
Test status
Simulation time 1518747681 ps
CPU time 42.01 seconds
Started Aug 25 06:10:15 AM UTC 24
Finished Aug 25 06:10:59 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336077481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3336077481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.1489212525
Short name T890
Test name
Test status
Simulation time 2929742124 ps
CPU time 5.3 seconds
Started Aug 25 06:10:36 AM UTC 24
Finished Aug 25 06:10:42 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1489212525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.1489212525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.485526176
Short name T878
Test name
Test status
Simulation time 143161811 ps
CPU time 1.77 seconds
Started Aug 25 06:10:30 AM UTC 24
Finished Aug 25 06:10:33 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4855261
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.485526176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.1134661720
Short name T882
Test name
Test status
Simulation time 256488149 ps
CPU time 2.46 seconds
Started Aug 25 06:10:31 AM UTC 24
Finished Aug 25 06:10:35 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134661
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.1134661720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.2539058888
Short name T892
Test name
Test status
Simulation time 1526092541 ps
CPU time 6.3 seconds
Started Aug 25 06:10:37 AM UTC 24
Finished Aug 25 06:10:44 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539058
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar
ks_acq.2539058888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.3993724736
Short name T888
Test name
Test status
Simulation time 113052971 ps
CPU time 2.18 seconds
Started Aug 25 06:10:38 AM UTC 24
Finished Aug 25 06:10:41 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993724
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.3993724736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_hrst.2585863601
Short name T887
Test name
Test status
Simulation time 1183459552 ps
CPU time 3.69 seconds
Started Aug 25 06:10:36 AM UTC 24
Finished Aug 25 06:10:40 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585863
601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_hrst.2585863601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.3066431110
Short name T880
Test name
Test status
Simulation time 642204255 ps
CPU time 6.96 seconds
Started Aug 25 06:10:26 AM UTC 24
Finished Aug 25 06:10:34 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306643
1110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.3066431110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.1032165381
Short name T891
Test name
Test status
Simulation time 9170548246 ps
CPU time 14.85 seconds
Started Aug 25 06:10:28 AM UTC 24
Finished Aug 25 06:10:44 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1032165381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.1032165381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.2633519642
Short name T895
Test name
Test status
Simulation time 582087568 ps
CPU time 4.53 seconds
Started Aug 25 06:10:41 AM UTC 24
Finished Aug 25 06:10:47 AM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633519
642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.2633519642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.2404218043
Short name T897
Test name
Test status
Simulation time 1200153362 ps
CPU time 5.72 seconds
Started Aug 25 06:10:42 AM UTC 24
Finished Aug 25 06:10:49 AM UTC 24
Peak memory 216400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404218
043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_ad
dr.2404218043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.1166873444
Short name T893
Test name
Test status
Simulation time 424002068 ps
CPU time 2.31 seconds
Started Aug 25 06:10:42 AM UTC 24
Finished Aug 25 06:10:46 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166873
444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_txstretch.1166873444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_perf.617172733
Short name T896
Test name
Test status
Simulation time 1015163834 ps
CPU time 11.23 seconds
Started Aug 25 06:10:34 AM UTC 24
Finished Aug 25 06:10:47 AM UTC 24
Peak memory 232948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6171727
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.617172733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.676777218
Short name T866
Test name
Test status
Simulation time 507137349 ps
CPU time 4.04 seconds
Started Aug 25 06:10:40 AM UTC 24
Finished Aug 25 06:10:45 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6767772
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.676777218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.1601188627
Short name T906
Test name
Test status
Simulation time 2411827930 ps
CPU time 50.49 seconds
Started Aug 25 06:10:17 AM UTC 24
Finished Aug 25 06:11:09 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601188627 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.1601188627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.1742968947
Short name T1079
Test name
Test status
Simulation time 34204099429 ps
CPU time 290.58 seconds
Started Aug 25 06:10:34 AM UTC 24
Finished Aug 25 06:15:30 AM UTC 24
Peak memory 2445576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174296
8947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.1742968947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.1228170256
Short name T879
Test name
Test status
Simulation time 10836606887 ps
CPU time 13.28 seconds
Started Aug 25 06:10:20 AM UTC 24
Finished Aug 25 06:10:34 AM UTC 24
Peak memory 233904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228170256 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.1228170256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.20710077
Short name T883
Test name
Test status
Simulation time 17600226023 ps
CPU time 16.76 seconds
Started Aug 25 06:10:18 AM UTC 24
Finished Aug 25 06:10:36 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20710077 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.20710077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.1543479489
Short name T876
Test name
Test status
Simulation time 648026298 ps
CPU time 7.38 seconds
Started Aug 25 06:10:21 AM UTC 24
Finished Aug 25 06:10:29 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543479489 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.1543479489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.3299689130
Short name T889
Test name
Test status
Simulation time 2536472573 ps
CPU time 12.14 seconds
Started Aug 25 06:10:28 AM UTC 24
Finished Aug 25 06:10:41 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299689
130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.3299689130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.2818943260
Short name T894
Test name
Test status
Simulation time 356637572 ps
CPU time 5.04 seconds
Started Aug 25 06:10:40 AM UTC 24
Finished Aug 25 06:10:46 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818943
260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2818943260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_alert_test.3596550900
Short name T927
Test name
Test status
Simulation time 20646120 ps
CPU time 0.96 seconds
Started Aug 25 06:11:25 AM UTC 24
Finished Aug 25 06:11:27 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596550900 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3596550900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.737314945
Short name T901
Test name
Test status
Simulation time 280372718 ps
CPU time 6.98 seconds
Started Aug 25 06:10:50 AM UTC 24
Finished Aug 25 06:10:58 AM UTC 24
Peak memory 233252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737314945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.737314945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.3380217834
Short name T900
Test name
Test status
Simulation time 770036818 ps
CPU time 9.32 seconds
Started Aug 25 06:10:47 AM UTC 24
Finished Aug 25 06:10:57 AM UTC 24
Peak memory 303200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380217834 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.3380217834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.1760223861
Short name T1036
Test name
Test status
Simulation time 11461641868 ps
CPU time 196.15 seconds
Started Aug 25 06:10:48 AM UTC 24
Finished Aug 25 06:14:08 AM UTC 24
Peak memory 387536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760223861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1760223861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.3686935149
Short name T941
Test name
Test status
Simulation time 3649378841 ps
CPU time 53.01 seconds
Started Aug 25 06:10:47 AM UTC 24
Finished Aug 25 06:11:41 AM UTC 24
Peak memory 671992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686935149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3686935149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.427580989
Short name T898
Test name
Test status
Simulation time 95631516 ps
CPU time 1.68 seconds
Started Aug 25 06:10:47 AM UTC 24
Finished Aug 25 06:10:49 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427580989 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.427580989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.618172321
Short name T899
Test name
Test status
Simulation time 433822303 ps
CPU time 8.34 seconds
Started Aug 25 06:10:47 AM UTC 24
Finished Aug 25 06:10:56 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618172321 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.618172321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.1902165584
Short name T1020
Test name
Test status
Simulation time 18034045091 ps
CPU time 166.57 seconds
Started Aug 25 06:10:45 AM UTC 24
Finished Aug 25 06:13:35 AM UTC 24
Peak memory 1372508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902165584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1902165584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.2434383532
Short name T939
Test name
Test status
Simulation time 495133666 ps
CPU time 21.78 seconds
Started Aug 25 06:11:17 AM UTC 24
Finished Aug 25 06:11:40 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434383532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2434383532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2766709392
Short name T1748
Test name
Test status
Simulation time 51263700701 ps
CPU time 2280.4 seconds
Started Aug 25 06:10:48 AM UTC 24
Finished Aug 25 06:49:16 AM UTC 24
Peak memory 2877616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766709392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2766709392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.1394835720
Short name T1044
Test name
Test status
Simulation time 3143560373 ps
CPU time 206.96 seconds
Started Aug 25 06:10:49 AM UTC 24
Finished Aug 25 06:14:20 AM UTC 24
Peak memory 698596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394835720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1394835720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.2335343897
Short name T988
Test name
Test status
Simulation time 1937723819 ps
CPU time 117.61 seconds
Started Aug 25 06:10:45 AM UTC 24
Finished Aug 25 06:12:46 AM UTC 24
Peak memory 346264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335343897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2335343897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.395571713
Short name T909
Test name
Test status
Simulation time 3557168655 ps
CPU time 21.43 seconds
Started Aug 25 06:10:50 AM UTC 24
Finished Aug 25 06:11:13 AM UTC 24
Peak memory 232776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395571713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.395571713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3529177138
Short name T922
Test name
Test status
Simulation time 10911914400 ps
CPU time 8.63 seconds
Started Aug 25 06:11:14 AM UTC 24
Finished Aug 25 06:11:24 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3529177138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.3529177138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.142143856
Short name T914
Test name
Test status
Simulation time 178740199 ps
CPU time 2.37 seconds
Started Aug 25 06:11:12 AM UTC 24
Finished Aug 25 06:11:15 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421438
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.142143856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.2977361210
Short name T915
Test name
Test status
Simulation time 234528055 ps
CPU time 1.43 seconds
Started Aug 25 06:11:13 AM UTC 24
Finished Aug 25 06:11:16 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977361
210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.2977361210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3202659214
Short name T923
Test name
Test status
Simulation time 544740152 ps
CPU time 5.16 seconds
Started Aug 25 06:11:18 AM UTC 24
Finished Aug 25 06:11:24 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202659
214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar
ks_acq.3202659214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1883845088
Short name T921
Test name
Test status
Simulation time 151645474 ps
CPU time 1.95 seconds
Started Aug 25 06:11:20 AM UTC 24
Finished Aug 25 06:11:23 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883845
088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.1883845088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_hrst.3879974082
Short name T918
Test name
Test status
Simulation time 3956414747 ps
CPU time 3.73 seconds
Started Aug 25 06:11:15 AM UTC 24
Finished Aug 25 06:11:20 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879974
082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.3879974082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.60066191
Short name T916
Test name
Test status
Simulation time 3947721049 ps
CPU time 10.37 seconds
Started Aug 25 06:11:06 AM UTC 24
Finished Aug 25 06:11:17 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600661
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.60066191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.1643131979
Short name T926
Test name
Test status
Simulation time 16511066080 ps
CPU time 16.59 seconds
Started Aug 25 06:11:09 AM UTC 24
Finished Aug 25 06:11:27 AM UTC 24
Peak memory 444640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1643131979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres
s_wr.1643131979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.104505062
Short name T934
Test name
Test status
Simulation time 511150717 ps
CPU time 4.78 seconds
Started Aug 25 06:11:23 AM UTC 24
Finished Aug 25 06:11:29 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045050
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.104505062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.218184370
Short name T933
Test name
Test status
Simulation time 501583460 ps
CPU time 4.13 seconds
Started Aug 25 06:11:24 AM UTC 24
Finished Aug 25 06:11:29 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181843
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.218184370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_perf.2322143529
Short name T924
Test name
Test status
Simulation time 753440066 ps
CPU time 8.88 seconds
Started Aug 25 06:11:14 AM UTC 24
Finished Aug 25 06:11:24 AM UTC 24
Peak memory 232904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322143
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.2322143529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1287736140
Short name T925
Test name
Test status
Simulation time 468667237 ps
CPU time 3.36 seconds
Started Aug 25 06:11:21 AM UTC 24
Finished Aug 25 06:11:26 AM UTC 24
Peak memory 216276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287736
140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.1287736140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1843306878
Short name T912
Test name
Test status
Simulation time 6290994252 ps
CPU time 14.15 seconds
Started Aug 25 06:10:58 AM UTC 24
Finished Aug 25 06:11:14 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843306878 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.1843306878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.4260617655
Short name T967
Test name
Test status
Simulation time 38272094783 ps
CPU time 56.99 seconds
Started Aug 25 06:11:14 AM UTC 24
Finished Aug 25 06:12:14 AM UTC 24
Peak memory 364676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426061
7655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.4260617655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3515688150
Short name T917
Test name
Test status
Simulation time 1166108808 ps
CPU time 17.14 seconds
Started Aug 25 06:11:00 AM UTC 24
Finished Aug 25 06:11:19 AM UTC 24
Peak memory 231156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515688150 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.3515688150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.2659142301
Short name T1483
Test name
Test status
Simulation time 48472005249 ps
CPU time 783.11 seconds
Started Aug 25 06:10:59 AM UTC 24
Finished Aug 25 06:24:13 AM UTC 24
Peak memory 6406360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659142301 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.2659142301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.1657410661
Short name T908
Test name
Test status
Simulation time 2899152232 ps
CPU time 6.41 seconds
Started Aug 25 06:11:04 AM UTC 24
Finished Aug 25 06:11:11 AM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657410661 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.1657410661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.3890956133
Short name T920
Test name
Test status
Simulation time 6374609402 ps
CPU time 11.61 seconds
Started Aug 25 06:11:10 AM UTC 24
Finished Aug 25 06:11:23 AM UTC 24
Peak memory 231052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890956
133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.3890956133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.3932975085
Short name T929
Test name
Test status
Simulation time 116442888 ps
CPU time 4.91 seconds
Started Aug 25 06:11:21 AM UTC 24
Finished Aug 25 06:11:27 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932975
085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3932975085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2049622357
Short name T959
Test name
Test status
Simulation time 41079955 ps
CPU time 0.89 seconds
Started Aug 25 06:12:04 AM UTC 24
Finished Aug 25 06:12:06 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049622357 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2049622357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.4181740615
Short name T936
Test name
Test status
Simulation time 936797654 ps
CPU time 1.85 seconds
Started Aug 25 06:11:31 AM UTC 24
Finished Aug 25 06:11:34 AM UTC 24
Peak memory 228412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181740615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4181740615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2000859367
Short name T937
Test name
Test status
Simulation time 343879370 ps
CPU time 9.89 seconds
Started Aug 25 06:11:28 AM UTC 24
Finished Aug 25 06:11:40 AM UTC 24
Peak memory 280604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000859367 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.2000859367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.4153010928
Short name T1062
Test name
Test status
Simulation time 2740961845 ps
CPU time 199.08 seconds
Started Aug 25 06:11:29 AM UTC 24
Finished Aug 25 06:14:51 AM UTC 24
Peak memory 630940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153010928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.4153010928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.3248985697
Short name T1000
Test name
Test status
Simulation time 8312660430 ps
CPU time 88 seconds
Started Aug 25 06:11:27 AM UTC 24
Finished Aug 25 06:12:58 AM UTC 24
Peak memory 747804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248985697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3248985697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.3993330994
Short name T935
Test name
Test status
Simulation time 261994388 ps
CPU time 1.7 seconds
Started Aug 25 06:11:28 AM UTC 24
Finished Aug 25 06:11:31 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993330994 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.3993330994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.2449219185
Short name T940
Test name
Test status
Simulation time 836340587 ps
CPU time 10.51 seconds
Started Aug 25 06:11:29 AM UTC 24
Finished Aug 25 06:11:40 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449219185 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.2449219185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.51090096
Short name T1067
Test name
Test status
Simulation time 28022849473 ps
CPU time 223.83 seconds
Started Aug 25 06:11:26 AM UTC 24
Finished Aug 25 06:15:14 AM UTC 24
Peak memory 1034644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51090096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.51090096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.425047675
Short name T278
Test name
Test status
Simulation time 628315405 ps
CPU time 11.38 seconds
Started Aug 25 06:11:58 AM UTC 24
Finished Aug 25 06:12:11 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425047675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.425047675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_override.2946681491
Short name T928
Test name
Test status
Simulation time 46598404 ps
CPU time 1.01 seconds
Started Aug 25 06:11:25 AM UTC 24
Finished Aug 25 06:11:27 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946681491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2946681491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2019425654
Short name T938
Test name
Test status
Simulation time 626012414 ps
CPU time 10.21 seconds
Started Aug 25 06:11:29 AM UTC 24
Finished Aug 25 06:11:40 AM UTC 24
Peak memory 243820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019425654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2019425654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.3534226272
Short name T1095
Test name
Test status
Simulation time 24413686157 ps
CPU time 260.84 seconds
Started Aug 25 06:11:30 AM UTC 24
Finished Aug 25 06:15:56 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534226272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3534226272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.768198547
Short name T951
Test name
Test status
Simulation time 1757775321 ps
CPU time 32.4 seconds
Started Aug 25 06:11:25 AM UTC 24
Finished Aug 25 06:11:59 AM UTC 24
Peak memory 331724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768198547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.768198547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.3007251320
Short name T942
Test name
Test status
Simulation time 475226951 ps
CPU time 11.61 seconds
Started Aug 25 06:11:31 AM UTC 24
Finished Aug 25 06:11:44 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007251320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3007251320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.4169937472
Short name T962
Test name
Test status
Simulation time 4398529940 ps
CPU time 11.44 seconds
Started Aug 25 06:11:54 AM UTC 24
Finished Aug 25 06:12:07 AM UTC 24
Peak memory 228996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4169937472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad
dr.4169937472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.2163285172
Short name T944
Test name
Test status
Simulation time 193471267 ps
CPU time 2.4 seconds
Started Aug 25 06:11:48 AM UTC 24
Finished Aug 25 06:11:51 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163285
172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.2163285172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.2161284579
Short name T945
Test name
Test status
Simulation time 560601182 ps
CPU time 1.28 seconds
Started Aug 25 06:11:51 AM UTC 24
Finished Aug 25 06:11:53 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161284
579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.2161284579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.3697289681
Short name T956
Test name
Test status
Simulation time 3771296110 ps
CPU time 3.02 seconds
Started Aug 25 06:11:59 AM UTC 24
Finished Aug 25 06:12:04 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697289
681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.3697289681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.3495602025
Short name T955
Test name
Test status
Simulation time 77273122 ps
CPU time 1.48 seconds
Started Aug 25 06:12:00 AM UTC 24
Finished Aug 25 06:12:02 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495602
025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermark
s_tx.3495602025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.2119999520
Short name T943
Test name
Test status
Simulation time 608080976 ps
CPU time 6.87 seconds
Started Aug 25 06:11:42 AM UTC 24
Finished Aug 25 06:11:50 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211999
9520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.2119999520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.451869046
Short name T954
Test name
Test status
Simulation time 3326583176 ps
CPU time 17.46 seconds
Started Aug 25 06:11:42 AM UTC 24
Finished Aug 25 06:12:01 AM UTC 24
Peak memory 567448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=451869046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stress
_wr.451869046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.3682565444
Short name T53
Test name
Test status
Simulation time 2036823074 ps
CPU time 5.02 seconds
Started Aug 25 06:12:02 AM UTC 24
Finished Aug 25 06:12:08 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682565
444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.3682565444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.2084514319
Short name T964
Test name
Test status
Simulation time 2123578200 ps
CPU time 4.55 seconds
Started Aug 25 06:12:02 AM UTC 24
Finished Aug 25 06:12:07 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084514
319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad
dr.2084514319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.3743413830
Short name T960
Test name
Test status
Simulation time 1473497748 ps
CPU time 2.32 seconds
Started Aug 25 06:12:03 AM UTC 24
Finished Aug 25 06:12:06 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743413
830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_txstretch.3743413830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_perf.2012053552
Short name T950
Test name
Test status
Simulation time 1011329036 ps
CPU time 5.81 seconds
Started Aug 25 06:11:52 AM UTC 24
Finished Aug 25 06:11:59 AM UTC 24
Peak memory 233016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012053
552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.2012053552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.519390845
Short name T957
Test name
Test status
Simulation time 884535500 ps
CPU time 2.75 seconds
Started Aug 25 06:12:01 AM UTC 24
Finished Aug 25 06:12:04 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5193908
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.519390845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.1791908977
Short name T946
Test name
Test status
Simulation time 13683605931 ps
CPU time 16.56 seconds
Started Aug 25 06:11:35 AM UTC 24
Finished Aug 25 06:11:53 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791908977 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.1791908977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.2300693568
Short name T1209
Test name
Test status
Simulation time 52792272986 ps
CPU time 395.09 seconds
Started Aug 25 06:11:54 AM UTC 24
Finished Aug 25 06:18:34 AM UTC 24
Peak memory 2470152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230069
3568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.2300693568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.2645220342
Short name T952
Test name
Test status
Simulation time 768730550 ps
CPU time 17.69 seconds
Started Aug 25 06:11:40 AM UTC 24
Finished Aug 25 06:12:00 AM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645220342 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.2645220342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.4123135087
Short name T1724
Test name
Test status
Simulation time 51529544887 ps
CPU time 1073 seconds
Started Aug 25 06:11:36 AM UTC 24
Finished Aug 25 06:29:43 AM UTC 24
Peak memory 7762320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123135087 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.4123135087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.2856128976
Short name T966
Test name
Test status
Simulation time 3402443324 ps
CPU time 29.62 seconds
Started Aug 25 06:11:41 AM UTC 24
Finished Aug 25 06:12:13 AM UTC 24
Peak memory 602264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856128976 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.2856128976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.1033530250
Short name T948
Test name
Test status
Simulation time 1227967855 ps
CPU time 12.23 seconds
Started Aug 25 06:11:43 AM UTC 24
Finished Aug 25 06:11:56 AM UTC 24
Peak memory 243788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033530
250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.1033530250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.752462060
Short name T958
Test name
Test status
Simulation time 82802415 ps
CPU time 2.86 seconds
Started Aug 25 06:12:01 AM UTC 24
Finished Aug 25 06:12:04 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7524620
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.752462060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_alert_test.3006411688
Short name T991
Test name
Test status
Simulation time 23303655 ps
CPU time 1.02 seconds
Started Aug 25 06:12:44 AM UTC 24
Finished Aug 25 06:12:46 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006411688 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3006411688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.1976667686
Short name T932
Test name
Test status
Simulation time 301115256 ps
CPU time 2.54 seconds
Started Aug 25 06:12:14 AM UTC 24
Finished Aug 25 06:12:18 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976667686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1976667686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.4085439780
Short name T970
Test name
Test status
Simulation time 2408260132 ps
CPU time 18.82 seconds
Started Aug 25 06:12:07 AM UTC 24
Finished Aug 25 06:12:27 AM UTC 24
Peak memory 370952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085439780 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.4085439780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.1797457714
Short name T1048
Test name
Test status
Simulation time 3205109256 ps
CPU time 135.8 seconds
Started Aug 25 06:12:08 AM UTC 24
Finished Aug 25 06:14:27 AM UTC 24
Peak memory 665860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797457714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1797457714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.1210081095
Short name T1002
Test name
Test status
Simulation time 1380927785 ps
CPU time 52.3 seconds
Started Aug 25 06:12:07 AM UTC 24
Finished Aug 25 06:13:01 AM UTC 24
Peak memory 528664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210081095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1210081095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.2789341368
Short name T965
Test name
Test status
Simulation time 517872316 ps
CPU time 1.69 seconds
Started Aug 25 06:12:07 AM UTC 24
Finished Aug 25 06:12:10 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789341368 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.2789341368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.2351771446
Short name T911
Test name
Test status
Simulation time 1802934819 ps
CPU time 6.4 seconds
Started Aug 25 06:12:08 AM UTC 24
Finished Aug 25 06:12:16 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351771446 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.2351771446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.656866707
Short name T1088
Test name
Test status
Simulation time 14134080389 ps
CPU time 206.46 seconds
Started Aug 25 06:12:07 AM UTC 24
Finished Aug 25 06:15:37 AM UTC 24
Peak memory 774360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656866707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.656866707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.4223879731
Short name T986
Test name
Test status
Simulation time 1403571899 ps
CPU time 6.72 seconds
Started Aug 25 06:12:36 AM UTC 24
Finished Aug 25 06:12:44 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223879731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.4223879731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_override.1506907827
Short name T963
Test name
Test status
Simulation time 50627015 ps
CPU time 0.98 seconds
Started Aug 25 06:12:05 AM UTC 24
Finished Aug 25 06:12:07 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506907827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1506907827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_perf.3542954067
Short name T1001
Test name
Test status
Simulation time 2749012077 ps
CPU time 50.73 seconds
Started Aug 25 06:12:09 AM UTC 24
Finished Aug 25 06:13:01 AM UTC 24
Peak memory 216952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542954067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3542954067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.2016572594
Short name T910
Test name
Test status
Simulation time 43606876 ps
CPU time 2.22 seconds
Started Aug 25 06:12:11 AM UTC 24
Finished Aug 25 06:12:14 AM UTC 24
Peak memory 239044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016572594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2016572594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.1703159040
Short name T1040
Test name
Test status
Simulation time 8166683574 ps
CPU time 125.52 seconds
Started Aug 25 06:12:05 AM UTC 24
Finished Aug 25 06:14:13 AM UTC 24
Peak memory 514296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703159040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1703159040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.391642881
Short name T972
Test name
Test status
Simulation time 3288994422 ps
CPU time 14.85 seconds
Started Aug 25 06:12:12 AM UTC 24
Finished Aug 25 06:12:28 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391642881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.391642881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.942239787
Short name T983
Test name
Test status
Simulation time 2602178191 ps
CPU time 7.18 seconds
Started Aug 25 06:12:33 AM UTC 24
Finished Aug 25 06:12:42 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=942239787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.942239787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.577213817
Short name T976
Test name
Test status
Simulation time 1917409185 ps
CPU time 2.56 seconds
Started Aug 25 06:12:29 AM UTC 24
Finished Aug 25 06:12:32 AM UTC 24
Peak memory 228876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5772138
17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.577213817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.2615243870
Short name T975
Test name
Test status
Simulation time 583065172 ps
CPU time 1.89 seconds
Started Aug 25 06:12:29 AM UTC 24
Finished Aug 25 06:12:32 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615243
870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.2615243870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2835817013
Short name T984
Test name
Test status
Simulation time 3045536778 ps
CPU time 2.66 seconds
Started Aug 25 06:12:38 AM UTC 24
Finished Aug 25 06:12:42 AM UTC 24
Peak memory 216476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835817
013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar
ks_acq.2835817013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.802899219
Short name T982
Test name
Test status
Simulation time 105498190 ps
CPU time 1.75 seconds
Started Aug 25 06:12:38 AM UTC 24
Finished Aug 25 06:12:41 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8028992
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermarks
_tx.802899219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.3747353287
Short name T317
Test name
Test status
Simulation time 662666998 ps
CPU time 2.57 seconds
Started Aug 25 06:12:33 AM UTC 24
Finished Aug 25 06:12:37 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747353
287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.3747353287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.1106182734
Short name T971
Test name
Test status
Simulation time 642952086 ps
CPU time 8.26 seconds
Started Aug 25 06:12:18 AM UTC 24
Finished Aug 25 06:12:28 AM UTC 24
Peak memory 228808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110618
2734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.1106182734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.2351473540
Short name T1158
Test name
Test status
Simulation time 17828503736 ps
CPU time 279.56 seconds
Started Aug 25 06:12:22 AM UTC 24
Finished Aug 25 06:17:07 AM UTC 24
Peak memory 2902104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2351473540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres
s_wr.2351473540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.3541323397
Short name T992
Test name
Test status
Simulation time 7487924780 ps
CPU time 4.78 seconds
Started Aug 25 06:12:42 AM UTC 24
Finished Aug 25 06:12:47 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541323
397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.3541323397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.792795693
Short name T993
Test name
Test status
Simulation time 590443916 ps
CPU time 4.07 seconds
Started Aug 25 06:12:43 AM UTC 24
Finished Aug 25 06:12:48 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7927956
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.792795693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.1678678456
Short name T990
Test name
Test status
Simulation time 522811794 ps
CPU time 2.36 seconds
Started Aug 25 06:12:43 AM UTC 24
Finished Aug 25 06:12:46 AM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678678
456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.1678678456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_perf.1411240776
Short name T981
Test name
Test status
Simulation time 2946636891 ps
CPU time 8.95 seconds
Started Aug 25 06:12:30 AM UTC 24
Finished Aug 25 06:12:40 AM UTC 24
Peak memory 233088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411240
776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.1411240776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.75149224
Short name T987
Test name
Test status
Simulation time 551753728 ps
CPU time 3.47 seconds
Started Aug 25 06:12:40 AM UTC 24
Finished Aug 25 06:12:45 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7514922
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.75149224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.2941666796
Short name T997
Test name
Test status
Simulation time 1879230097 ps
CPU time 38.35 seconds
Started Aug 25 06:12:15 AM UTC 24
Finished Aug 25 06:12:55 AM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941666796 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.2941666796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3241094309
Short name T1590
Test name
Test status
Simulation time 44446339156 ps
CPU time 826.29 seconds
Started Aug 25 06:12:32 AM UTC 24
Finished Aug 25 06:26:29 AM UTC 24
Peak memory 8018072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324109
4309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.3241094309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.3160010550
Short name T843
Test name
Test status
Simulation time 242854697 ps
CPU time 4.83 seconds
Started Aug 25 06:12:16 AM UTC 24
Finished Aug 25 06:12:22 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160010550 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.3160010550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.539612513
Short name T1345
Test name
Test status
Simulation time 37616201084 ps
CPU time 546.14 seconds
Started Aug 25 06:12:16 AM UTC 24
Finished Aug 25 06:21:29 AM UTC 24
Peak memory 4665752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539612513 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.539612513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.3769115469
Short name T973
Test name
Test status
Simulation time 1780683296 ps
CPU time 9.89 seconds
Started Aug 25 06:12:17 AM UTC 24
Finished Aug 25 06:12:28 AM UTC 24
Peak memory 235904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769115469 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.3769115469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.3384414339
Short name T977
Test name
Test status
Simulation time 4070163075 ps
CPU time 10.42 seconds
Started Aug 25 06:12:22 AM UTC 24
Finished Aug 25 06:12:34 AM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384414
339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.3384414339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.4173365974
Short name T989
Test name
Test status
Simulation time 171066380 ps
CPU time 5.63 seconds
Started Aug 25 06:12:38 AM UTC 24
Finished Aug 25 06:12:46 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173365
974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.4173365974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_alert_test.3061841668
Short name T1022
Test name
Test status
Simulation time 17303823 ps
CPU time 1.01 seconds
Started Aug 25 06:13:35 AM UTC 24
Finished Aug 25 06:13:37 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061841668 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3061841668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.1268887553
Short name T1003
Test name
Test status
Simulation time 1376792552 ps
CPU time 4.7 seconds
Started Aug 25 06:12:56 AM UTC 24
Finished Aug 25 06:13:02 AM UTC 24
Peak memory 247908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268887553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1268887553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.2820074633
Short name T996
Test name
Test status
Simulation time 607753622 ps
CPU time 4.12 seconds
Started Aug 25 06:12:47 AM UTC 24
Finished Aug 25 06:12:53 AM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820074633 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.2820074633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.1875780912
Short name T1063
Test name
Test status
Simulation time 2964055107 ps
CPU time 124.06 seconds
Started Aug 25 06:12:48 AM UTC 24
Finished Aug 25 06:14:56 AM UTC 24
Peak memory 649416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875780912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1875780912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.315442450
Short name T1099
Test name
Test status
Simulation time 4644550395 ps
CPU time 190.41 seconds
Started Aug 25 06:12:47 AM UTC 24
Finished Aug 25 06:16:01 AM UTC 24
Peak memory 768360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315442450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.315442450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.1386083039
Short name T995
Test name
Test status
Simulation time 103643754 ps
CPU time 1.68 seconds
Started Aug 25 06:12:47 AM UTC 24
Finished Aug 25 06:12:50 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386083039 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.1386083039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.2583664271
Short name T999
Test name
Test status
Simulation time 623498180 ps
CPU time 6.98 seconds
Started Aug 25 06:12:48 AM UTC 24
Finished Aug 25 06:12:57 AM UTC 24
Peak memory 245792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583664271 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.2583664271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.3416187046
Short name T1195
Test name
Test status
Simulation time 4375643421 ps
CPU time 323.49 seconds
Started Aug 25 06:12:47 AM UTC 24
Finished Aug 25 06:18:16 AM UTC 24
Peak memory 1335420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416187046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3416187046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.1237529491
Short name T1030
Test name
Test status
Simulation time 566817026 ps
CPU time 26.03 seconds
Started Aug 25 06:13:22 AM UTC 24
Finished Aug 25 06:13:50 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237529491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1237529491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_override.1192210467
Short name T994
Test name
Test status
Simulation time 75142463 ps
CPU time 1.03 seconds
Started Aug 25 06:12:46 AM UTC 24
Finished Aug 25 06:12:48 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192210467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1192210467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_perf.930165852
Short name T1109
Test name
Test status
Simulation time 30729934863 ps
CPU time 197.96 seconds
Started Aug 25 06:12:49 AM UTC 24
Finished Aug 25 06:16:12 AM UTC 24
Peak memory 217008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930165852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.930165852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.1882929118
Short name T998
Test name
Test status
Simulation time 238905673 ps
CPU time 4.16 seconds
Started Aug 25 06:12:52 AM UTC 24
Finished Aug 25 06:12:57 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882929118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1882929118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.1589999292
Short name T1035
Test name
Test status
Simulation time 1450660042 ps
CPU time 77.45 seconds
Started Aug 25 06:12:45 AM UTC 24
Finished Aug 25 06:14:04 AM UTC 24
Peak memory 338012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589999292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1589999292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.884661135
Short name T1007
Test name
Test status
Simulation time 1484383784 ps
CPU time 21.68 seconds
Started Aug 25 06:12:54 AM UTC 24
Finished Aug 25 06:13:17 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884661135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.884661135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.1592285911
Short name T1012
Test name
Test status
Simulation time 3613806560 ps
CPU time 7.07 seconds
Started Aug 25 06:13:18 AM UTC 24
Finished Aug 25 06:13:26 AM UTC 24
Peak memory 230992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1592285911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_ad
dr.1592285911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.3149190232
Short name T1005
Test name
Test status
Simulation time 345697598 ps
CPU time 1.39 seconds
Started Aug 25 06:13:09 AM UTC 24
Finished Aug 25 06:13:11 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149190
232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.3149190232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.1850514741
Short name T1006
Test name
Test status
Simulation time 223585169 ps
CPU time 2.04 seconds
Started Aug 25 06:13:13 AM UTC 24
Finished Aug 25 06:13:16 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850514
741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.1850514741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.583123518
Short name T1017
Test name
Test status
Simulation time 2896483463 ps
CPU time 4.6 seconds
Started Aug 25 06:13:25 AM UTC 24
Finished Aug 25 06:13:31 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5831235
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_acq.583123518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.2494328925
Short name T1015
Test name
Test status
Simulation time 749634263 ps
CPU time 1.38 seconds
Started Aug 25 06:13:27 AM UTC 24
Finished Aug 25 06:13:30 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494328
925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_tx.2494328925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.1663250459
Short name T1008
Test name
Test status
Simulation time 2392457632 ps
CPU time 13.5 seconds
Started Aug 25 06:13:02 AM UTC 24
Finished Aug 25 06:13:17 AM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166325
0459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.1663250459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.2998380507
Short name T1038
Test name
Test status
Simulation time 10208881663 ps
CPU time 66.76 seconds
Started Aug 25 06:13:02 AM UTC 24
Finished Aug 25 06:14:11 AM UTC 24
Peak memory 930008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2998380507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stres
s_wr.2998380507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.836949775
Short name T1024
Test name
Test status
Simulation time 1035828080 ps
CPU time 5.43 seconds
Started Aug 25 06:13:31 AM UTC 24
Finished Aug 25 06:13:37 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8369497
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.836949775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.382370855
Short name T1023
Test name
Test status
Simulation time 1047026731 ps
CPU time 4.24 seconds
Started Aug 25 06:13:32 AM UTC 24
Finished Aug 25 06:13:37 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823708
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.382370855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_perf.3671337208
Short name T1013
Test name
Test status
Simulation time 1374426753 ps
CPU time 8.54 seconds
Started Aug 25 06:13:17 AM UTC 24
Finished Aug 25 06:13:26 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671337
208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.3671337208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.1267202723
Short name T1021
Test name
Test status
Simulation time 562797108 ps
CPU time 3.57 seconds
Started Aug 25 06:13:30 AM UTC 24
Finished Aug 25 06:13:36 AM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267202
723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.1267202723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.3767492687
Short name T1011
Test name
Test status
Simulation time 1116887228 ps
CPU time 22.48 seconds
Started Aug 25 06:12:58 AM UTC 24
Finished Aug 25 06:13:22 AM UTC 24
Peak memory 228808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767492687 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.3767492687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.1004508985
Short name T1126
Test name
Test status
Simulation time 29261128618 ps
CPU time 183.02 seconds
Started Aug 25 06:13:18 AM UTC 24
Finished Aug 25 06:16:24 AM UTC 24
Peak memory 1763668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100450
8985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.1004508985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.982972470
Short name T1027
Test name
Test status
Simulation time 8041792052 ps
CPU time 42.7 seconds
Started Aug 25 06:12:59 AM UTC 24
Finished Aug 25 06:13:43 AM UTC 24
Peak memory 250264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982972470 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.982972470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.1561698697
Short name T1010
Test name
Test status
Simulation time 14052037050 ps
CPU time 22.27 seconds
Started Aug 25 06:12:58 AM UTC 24
Finished Aug 25 06:13:21 AM UTC 24
Peak memory 216940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561698697 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.1561698697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.3209995567
Short name T1014
Test name
Test status
Simulation time 2460449074 ps
CPU time 25.69 seconds
Started Aug 25 06:13:02 AM UTC 24
Finished Aug 25 06:13:30 AM UTC 24
Peak memory 327884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209995567 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.3209995567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.2927892181
Short name T1009
Test name
Test status
Simulation time 2611518134 ps
CPU time 11.92 seconds
Started Aug 25 06:13:04 AM UTC 24
Finished Aug 25 06:13:18 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927892
181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.2927892181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.1501055694
Short name T1029
Test name
Test status
Simulation time 701655495 ps
CPU time 16.69 seconds
Started Aug 25 06:13:27 AM UTC 24
Finished Aug 25 06:13:46 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501055
694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1501055694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_alert_test.3113525771
Short name T1052
Test name
Test status
Simulation time 34056599 ps
CPU time 0.88 seconds
Started Aug 25 06:14:29 AM UTC 24
Finished Aug 25 06:14:31 AM UTC 24
Peak memory 215468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113525771 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3113525771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.3486110985
Short name T1031
Test name
Test status
Simulation time 444382435 ps
CPU time 2.89 seconds
Started Aug 25 06:13:47 AM UTC 24
Finished Aug 25 06:13:50 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486110985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3486110985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.1958542539
Short name T1028
Test name
Test status
Simulation time 228938614 ps
CPU time 6.26 seconds
Started Aug 25 06:13:38 AM UTC 24
Finished Aug 25 06:13:46 AM UTC 24
Peak memory 254244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958542539 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.1958542539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.3920768918
Short name T1059
Test name
Test status
Simulation time 2224610679 ps
CPU time 63.73 seconds
Started Aug 25 06:13:39 AM UTC 24
Finished Aug 25 06:14:45 AM UTC 24
Peak memory 254176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920768918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3920768918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.2227219049
Short name T1064
Test name
Test status
Simulation time 9555760117 ps
CPU time 87.54 seconds
Started Aug 25 06:13:37 AM UTC 24
Finished Aug 25 06:15:07 AM UTC 24
Peak memory 753876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227219049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2227219049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.3417694769
Short name T1026
Test name
Test status
Simulation time 115053417 ps
CPU time 1.95 seconds
Started Aug 25 06:13:38 AM UTC 24
Finished Aug 25 06:13:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417694769 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.3417694769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.1592208872
Short name T1032
Test name
Test status
Simulation time 845742360 ps
CPU time 12.77 seconds
Started Aug 25 06:13:38 AM UTC 24
Finished Aug 25 06:13:52 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592208872 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.1592208872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.2162834058
Short name T124
Test name
Test status
Simulation time 4263503852 ps
CPU time 125.66 seconds
Started Aug 25 06:13:36 AM UTC 24
Finished Aug 25 06:15:44 AM UTC 24
Peak memory 1304664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162834058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2162834058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.2452747078
Short name T271
Test name
Test status
Simulation time 1388268239 ps
CPU time 19.5 seconds
Started Aug 25 06:14:21 AM UTC 24
Finished Aug 25 06:14:42 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452747078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2452747078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_mode_toggle.3059153185
Short name T978
Test name
Test status
Simulation time 297013870 ps
CPU time 1.87 seconds
Started Aug 25 06:14:19 AM UTC 24
Finished Aug 25 06:14:22 AM UTC 24
Peak memory 228404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059153185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3059153185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_override.1944521876
Short name T1025
Test name
Test status
Simulation time 26305676 ps
CPU time 0.96 seconds
Started Aug 25 06:13:36 AM UTC 24
Finished Aug 25 06:13:38 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944521876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1944521876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_perf.1790619918
Short name T1072
Test name
Test status
Simulation time 6853243022 ps
CPU time 97.89 seconds
Started Aug 25 06:13:42 AM UTC 24
Finished Aug 25 06:15:22 AM UTC 24
Peak memory 901384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790619918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1790619918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.3408327602
Short name T1730
Test name
Test status
Simulation time 24415725103 ps
CPU time 1052.67 seconds
Started Aug 25 06:13:44 AM UTC 24
Finished Aug 25 06:31:31 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408327602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3408327602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.250068502
Short name T1033
Test name
Test status
Simulation time 1058835862 ps
CPU time 21.71 seconds
Started Aug 25 06:13:35 AM UTC 24
Finished Aug 25 06:13:58 AM UTC 24
Peak memory 309532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250068502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.250068502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.2389460520
Short name T1034
Test name
Test status
Simulation time 532881544 ps
CPU time 12.34 seconds
Started Aug 25 06:13:47 AM UTC 24
Finished Aug 25 06:14:00 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389460520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2389460520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.1355665433
Short name T1049
Test name
Test status
Simulation time 2216558777 ps
CPU time 9.85 seconds
Started Aug 25 06:14:17 AM UTC 24
Finished Aug 25 06:14:28 AM UTC 24
Peak memory 233692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1355665433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_ad
dr.1355665433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.2979983855
Short name T1041
Test name
Test status
Simulation time 576836868 ps
CPU time 2.29 seconds
Started Aug 25 06:14:12 AM UTC 24
Finished Aug 25 06:14:16 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979983
855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.2979983855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.216840363
Short name T1042
Test name
Test status
Simulation time 1662588593 ps
CPU time 1.95 seconds
Started Aug 25 06:14:14 AM UTC 24
Finished Aug 25 06:14:17 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168403
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.216840363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.2398018634
Short name T1047
Test name
Test status
Simulation time 251297286 ps
CPU time 2.28 seconds
Started Aug 25 06:14:21 AM UTC 24
Finished Aug 25 06:14:25 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398018
634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermar
ks_acq.2398018634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.4280786380
Short name T1046
Test name
Test status
Simulation time 237906466 ps
CPU time 1.88 seconds
Started Aug 25 06:14:21 AM UTC 24
Finished Aug 25 06:14:24 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280786
380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_tx.4280786380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_hrst.1529069727
Short name T1018
Test name
Test status
Simulation time 433529469 ps
CPU time 2.65 seconds
Started Aug 25 06:14:18 AM UTC 24
Finished Aug 25 06:14:22 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529069
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_hrst.1529069727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.867782405
Short name T1039
Test name
Test status
Simulation time 759789520 ps
CPU time 6.83 seconds
Started Aug 25 06:14:05 AM UTC 24
Finished Aug 25 06:14:13 AM UTC 24
Peak memory 227072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867782
405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.867782405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.477792176
Short name T1061
Test name
Test status
Simulation time 12731806202 ps
CPU time 36.88 seconds
Started Aug 25 06:14:08 AM UTC 24
Finished Aug 25 06:14:47 AM UTC 24
Peak memory 829588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=477792176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.477792176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.3261525079
Short name T1053
Test name
Test status
Simulation time 523583805 ps
CPU time 4.96 seconds
Started Aug 25 06:14:25 AM UTC 24
Finished Aug 25 06:14:31 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261525
079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.3261525079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.4002674005
Short name T1054
Test name
Test status
Simulation time 2212697334 ps
CPU time 4.92 seconds
Started Aug 25 06:14:25 AM UTC 24
Finished Aug 25 06:14:31 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002674
005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad
dr.4002674005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.2840626572
Short name T1055
Test name
Test status
Simulation time 1413328798 ps
CPU time 2 seconds
Started Aug 25 06:14:29 AM UTC 24
Finished Aug 25 06:14:32 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840626
572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_txstretch.2840626572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_perf.1230859371
Short name T1045
Test name
Test status
Simulation time 1983891283 ps
CPU time 5.24 seconds
Started Aug 25 06:14:14 AM UTC 24
Finished Aug 25 06:14:20 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230859
371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.1230859371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.2731793156
Short name T1050
Test name
Test status
Simulation time 1195067908 ps
CPU time 3.76 seconds
Started Aug 25 06:14:23 AM UTC 24
Finished Aug 25 06:14:28 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731793
156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.2731793156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2829572258
Short name T1037
Test name
Test status
Simulation time 2674103504 ps
CPU time 14.87 seconds
Started Aug 25 06:13:52 AM UTC 24
Finished Aug 25 06:14:08 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829572258 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.2829572258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.4254127078
Short name T1471
Test name
Test status
Simulation time 25225005260 ps
CPU time 609.54 seconds
Started Aug 25 06:14:15 AM UTC 24
Finished Aug 25 06:24:32 AM UTC 24
Peak memory 4641048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425412
7078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.4254127078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.1491027235
Short name T1066
Test name
Test status
Simulation time 8213724379 ps
CPU time 71.53 seconds
Started Aug 25 06:13:59 AM UTC 24
Finished Aug 25 06:15:12 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491027235 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.1491027235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.1776424747
Short name T1093
Test name
Test status
Simulation time 40281249313 ps
CPU time 115.29 seconds
Started Aug 25 06:13:53 AM UTC 24
Finished Aug 25 06:15:50 AM UTC 24
Peak memory 1784024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776424747 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.1776424747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2041614497
Short name T1043
Test name
Test status
Simulation time 2359368351 ps
CPU time 15.95 seconds
Started Aug 25 06:14:01 AM UTC 24
Finished Aug 25 06:14:18 AM UTC 24
Peak memory 283092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041614497 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.2041614497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.1005150408
Short name T974
Test name
Test status
Simulation time 2733205438 ps
CPU time 10.79 seconds
Started Aug 25 06:14:08 AM UTC 24
Finished Aug 25 06:14:20 AM UTC 24
Peak memory 233816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005150
408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.1005150408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3414200782
Short name T1051
Test name
Test status
Simulation time 188026787 ps
CPU time 4.68 seconds
Started Aug 25 06:14:23 AM UTC 24
Finished Aug 25 06:14:29 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414200
782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3414200782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_alert_test.4139681819
Short name T201
Test name
Test status
Simulation time 26964630 ps
CPU time 0.93 seconds
Started Aug 25 05:56:22 AM UTC 24
Finished Aug 25 05:56:24 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139681819 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4139681819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.4284089924
Short name T23
Test name
Test status
Simulation time 125034912 ps
CPU time 2.12 seconds
Started Aug 25 05:55:52 AM UTC 24
Finished Aug 25 05:55:56 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284089924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.4284089924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.521014055
Short name T42
Test name
Test status
Simulation time 598430017 ps
CPU time 8.1 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:56:00 AM UTC 24
Peak memory 282908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521014055 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.521014055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.1046107016
Short name T132
Test name
Test status
Simulation time 11674083022 ps
CPU time 182.85 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:58:58 AM UTC 24
Peak memory 440464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046107016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1046107016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.3080812583
Short name T104
Test name
Test status
Simulation time 8047834749 ps
CPU time 59.74 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:56:53 AM UTC 24
Peak memory 680136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080812583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3080812583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.3071358606
Short name T84
Test name
Test status
Simulation time 785769708 ps
CPU time 14.93 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:56:07 AM UTC 24
Peak memory 252196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071358606 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.3071358606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.87382452
Short name T86
Test name
Test status
Simulation time 13115230612 ps
CPU time 174.34 seconds
Started Aug 25 05:55:50 AM UTC 24
Finished Aug 25 05:58:48 AM UTC 24
Peak memory 889284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87382452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.87382452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.512464559
Short name T346
Test name
Test status
Simulation time 219910912 ps
CPU time 4.33 seconds
Started Aug 25 05:56:17 AM UTC 24
Finished Aug 25 05:56:22 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512464559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.512464559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_override.1311131573
Short name T333
Test name
Test status
Simulation time 28495813 ps
CPU time 1.04 seconds
Started Aug 25 05:55:48 AM UTC 24
Finished Aug 25 05:55:50 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311131573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1311131573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_perf.687901208
Short name T169
Test name
Test status
Simulation time 3168600115 ps
CPU time 43.33 seconds
Started Aug 25 05:55:51 AM UTC 24
Finished Aug 25 05:56:36 AM UTC 24
Peak memory 237228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687901208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.687901208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2404594531
Short name T335
Test name
Test status
Simulation time 74094119 ps
CPU time 2.6 seconds
Started Aug 25 05:55:52 AM UTC 24
Finished Aug 25 05:55:56 AM UTC 24
Peak memory 230856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404594531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2404594531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.2327686299
Short name T43
Test name
Test status
Simulation time 6134107578 ps
CPU time 27.49 seconds
Started Aug 25 05:55:48 AM UTC 24
Finished Aug 25 05:56:17 AM UTC 24
Peak memory 342284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327686299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2327686299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3888878608
Short name T339
Test name
Test status
Simulation time 729481648 ps
CPU time 16.08 seconds
Started Aug 25 05:55:52 AM UTC 24
Finished Aug 25 05:56:10 AM UTC 24
Peak memory 230908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888878608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3888878608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.3054419951
Short name T206
Test name
Test status
Simulation time 221728178 ps
CPU time 1.23 seconds
Started Aug 25 05:56:22 AM UTC 24
Finished Aug 25 05:56:25 AM UTC 24
Peak memory 246856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054419951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3054419951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.479827797
Short name T338
Test name
Test status
Simulation time 143066012 ps
CPU time 1.45 seconds
Started Aug 25 05:56:07 AM UTC 24
Finished Aug 25 05:56:10 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4798277
97 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.479827797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.1353572888
Short name T344
Test name
Test status
Simulation time 251018114 ps
CPU time 3.35 seconds
Started Aug 25 05:56:17 AM UTC 24
Finished Aug 25 05:56:21 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353572
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.1353572888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.3262669663
Short name T343
Test name
Test status
Simulation time 130357210 ps
CPU time 2.09 seconds
Started Aug 25 05:56:18 AM UTC 24
Finished Aug 25 05:56:21 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262669
663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks
_tx.3262669663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.4279643409
Short name T196
Test name
Test status
Simulation time 253808808 ps
CPU time 3.46 seconds
Started Aug 25 05:56:10 AM UTC 24
Finished Aug 25 05:56:15 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279643
409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.4279643409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.2744645253
Short name T299
Test name
Test status
Simulation time 818238807 ps
CPU time 8.62 seconds
Started Aug 25 05:55:57 AM UTC 24
Finished Aug 25 05:56:07 AM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274464
5253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.2744645253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.3707981026
Short name T397
Test name
Test status
Simulation time 10578656630 ps
CPU time 158.84 seconds
Started Aug 25 05:56:01 AM UTC 24
Finished Aug 25 05:58:43 AM UTC 24
Peak memory 2689232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3707981026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.3707981026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.460313773
Short name T168
Test name
Test status
Simulation time 2764196584 ps
CPU time 4.56 seconds
Started Aug 25 05:56:19 AM UTC 24
Finished Aug 25 05:56:25 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4603137
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.460313773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.3804099433
Short name T167
Test name
Test status
Simulation time 6029915799 ps
CPU time 4.48 seconds
Started Aug 25 05:56:19 AM UTC 24
Finished Aug 25 05:56:25 AM UTC 24
Peak memory 216860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804099
433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.3804099433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_perf.3614564712
Short name T341
Test name
Test status
Simulation time 2392673838 ps
CPU time 6.85 seconds
Started Aug 25 05:56:08 AM UTC 24
Finished Aug 25 05:56:16 AM UTC 24
Peak memory 222860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614564
712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.3614564712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.533307943
Short name T345
Test name
Test status
Simulation time 1052588798 ps
CPU time 3 seconds
Started Aug 25 05:56:18 AM UTC 24
Finished Aug 25 05:56:22 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5333079
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.533307943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.1230201299
Short name T225
Test name
Test status
Simulation time 1470030295 ps
CPU time 22.36 seconds
Started Aug 25 05:55:54 AM UTC 24
Finished Aug 25 05:56:17 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230201299 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.1230201299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.3140589382
Short name T844
Test name
Test status
Simulation time 39684071702 ps
CPU time 820.04 seconds
Started Aug 25 05:56:09 AM UTC 24
Finished Aug 25 06:09:59 AM UTC 24
Peak memory 7233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314058
9382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.3140589382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.1623587567
Short name T367
Test name
Test status
Simulation time 2926617478 ps
CPU time 76.83 seconds
Started Aug 25 05:55:56 AM UTC 24
Finished Aug 25 05:57:15 AM UTC 24
Peak memory 229288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623587567 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.1623587567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.2150699447
Short name T54
Test name
Test status
Simulation time 55740060559 ps
CPU time 119.29 seconds
Started Aug 25 05:55:55 AM UTC 24
Finished Aug 25 05:57:57 AM UTC 24
Peak memory 1446040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150699447 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.2150699447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.1226288242
Short name T379
Test name
Test status
Simulation time 2286887786 ps
CPU time 113.6 seconds
Started Aug 25 05:55:57 AM UTC 24
Finished Aug 25 05:57:53 AM UTC 24
Peak memory 731304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226288242 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.1226288242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.156704365
Short name T340
Test name
Test status
Simulation time 1600947638 ps
CPU time 13.76 seconds
Started Aug 25 05:56:01 AM UTC 24
Finished Aug 25 05:56:16 AM UTC 24
Peak memory 230924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567043
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.156704365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.2192675915
Short name T349
Test name
Test status
Simulation time 550304826 ps
CPU time 14.93 seconds
Started Aug 25 05:56:18 AM UTC 24
Finished Aug 25 05:56:34 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192675
915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2192675915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_alert_test.1610584088
Short name T1082
Test name
Test status
Simulation time 35066116 ps
CPU time 0.92 seconds
Started Aug 25 06:15:30 AM UTC 24
Finished Aug 25 06:15:33 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610584088 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1610584088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.1524463467
Short name T1060
Test name
Test status
Simulation time 219522330 ps
CPU time 2.67 seconds
Started Aug 25 06:14:42 AM UTC 24
Finished Aug 25 06:14:46 AM UTC 24
Peak memory 231196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524463467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1524463467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1974806698
Short name T1058
Test name
Test status
Simulation time 1903471875 ps
CPU time 7.12 seconds
Started Aug 25 06:14:33 AM UTC 24
Finished Aug 25 06:14:41 AM UTC 24
Peak memory 278520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974806698 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.1974806698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.177630553
Short name T1123
Test name
Test status
Simulation time 8152771915 ps
CPU time 104.2 seconds
Started Aug 25 06:14:33 AM UTC 24
Finished Aug 25 06:16:20 AM UTC 24
Peak memory 635112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177630553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.177630553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.1433276868
Short name T1090
Test name
Test status
Simulation time 11654487350 ps
CPU time 69.67 seconds
Started Aug 25 06:14:32 AM UTC 24
Finished Aug 25 06:15:44 AM UTC 24
Peak memory 690448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433276868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1433276868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.812908740
Short name T1056
Test name
Test status
Simulation time 121419319 ps
CPU time 1.43 seconds
Started Aug 25 06:14:32 AM UTC 24
Finished Aug 25 06:14:35 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812908740 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.812908740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.4254378568
Short name T1057
Test name
Test status
Simulation time 803573062 ps
CPU time 6.48 seconds
Started Aug 25 06:14:33 AM UTC 24
Finished Aug 25 06:14:41 AM UTC 24
Peak memory 256316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254378568 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.4254378568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3788560551
Short name T1265
Test name
Test status
Simulation time 17997539373 ps
CPU time 313.23 seconds
Started Aug 25 06:14:32 AM UTC 24
Finished Aug 25 06:19:51 AM UTC 24
Peak memory 1253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788560551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3788560551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.4171234621
Short name T282
Test name
Test status
Simulation time 273813009 ps
CPU time 5.89 seconds
Started Aug 25 06:15:23 AM UTC 24
Finished Aug 25 06:15:30 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171234621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.4171234621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_override.735867089
Short name T153
Test name
Test status
Simulation time 60126972 ps
CPU time 0.93 seconds
Started Aug 25 06:14:30 AM UTC 24
Finished Aug 25 06:14:32 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735867089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.735867089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_perf.344376118
Short name T1154
Test name
Test status
Simulation time 8833886238 ps
CPU time 143.76 seconds
Started Aug 25 06:14:35 AM UTC 24
Finished Aug 25 06:17:02 AM UTC 24
Peak memory 737444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344376118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.344376118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.1228300014
Short name T1252
Test name
Test status
Simulation time 5853693911 ps
CPU time 277.01 seconds
Started Aug 25 06:14:41 AM UTC 24
Finished Aug 25 06:19:23 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228300014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1228300014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.1645709243
Short name T1068
Test name
Test status
Simulation time 7618116040 ps
CPU time 44.5 seconds
Started Aug 25 06:14:29 AM UTC 24
Finished Aug 25 06:15:15 AM UTC 24
Peak memory 329952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645709243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1645709243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.3525792874
Short name T1071
Test name
Test status
Simulation time 533502880 ps
CPU time 35.46 seconds
Started Aug 25 06:14:42 AM UTC 24
Finished Aug 25 06:15:19 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525792874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3525792874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.3751623074
Short name T1080
Test name
Test status
Simulation time 1382759911 ps
CPU time 10.58 seconds
Started Aug 25 06:15:19 AM UTC 24
Finished Aug 25 06:15:30 AM UTC 24
Peak memory 233468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3751623074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_ad
dr.3751623074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.2963339217
Short name T253
Test name
Test status
Simulation time 687183283 ps
CPU time 2.13 seconds
Started Aug 25 06:15:15 AM UTC 24
Finished Aug 25 06:15:19 AM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963339
217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.2963339217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.3947041643
Short name T1069
Test name
Test status
Simulation time 246099030 ps
CPU time 1.24 seconds
Started Aug 25 06:15:15 AM UTC 24
Finished Aug 25 06:15:18 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947041
643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.3947041643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.160183962
Short name T1077
Test name
Test status
Simulation time 218233882 ps
CPU time 2.47 seconds
Started Aug 25 06:15:24 AM UTC 24
Finished Aug 25 06:15:27 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601839
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_acq.160183962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.4110486599
Short name T1076
Test name
Test status
Simulation time 168321669 ps
CPU time 2.09 seconds
Started Aug 25 06:15:24 AM UTC 24
Finished Aug 25 06:15:27 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110486
599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_tx.4110486599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.1950545654
Short name T1073
Test name
Test status
Simulation time 487697734 ps
CPU time 2.35 seconds
Started Aug 25 06:15:20 AM UTC 24
Finished Aug 25 06:15:23 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950545
654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.1950545654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.3027593740
Short name T1070
Test name
Test status
Simulation time 6301521017 ps
CPU time 8.96 seconds
Started Aug 25 06:15:08 AM UTC 24
Finished Aug 25 06:15:18 AM UTC 24
Peak memory 227208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302759
3740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.3027593740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.2850956936
Short name T1130
Test name
Test status
Simulation time 20123246823 ps
CPU time 86.04 seconds
Started Aug 25 06:15:09 AM UTC 24
Finished Aug 25 06:16:37 AM UTC 24
Peak memory 1372380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2850956936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres
s_wr.2850956936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.1803770303
Short name T1086
Test name
Test status
Simulation time 546413510 ps
CPU time 5.46 seconds
Started Aug 25 06:15:28 AM UTC 24
Finished Aug 25 06:15:35 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803770
303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.1803770303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.1222059260
Short name T1083
Test name
Test status
Simulation time 569528113 ps
CPU time 4.15 seconds
Started Aug 25 06:15:28 AM UTC 24
Finished Aug 25 06:15:34 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222059
260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad
dr.1222059260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.973171603
Short name T1085
Test name
Test status
Simulation time 162214036 ps
CPU time 2.33 seconds
Started Aug 25 06:15:30 AM UTC 24
Finished Aug 25 06:15:34 AM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9731716
03 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_txstretch.973171603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_perf.305560337
Short name T1075
Test name
Test status
Simulation time 592350343 ps
CPU time 7.32 seconds
Started Aug 25 06:15:16 AM UTC 24
Finished Aug 25 06:15:25 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055603
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.305560337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.123936007
Short name T1081
Test name
Test status
Simulation time 509829673 ps
CPU time 3.08 seconds
Started Aug 25 06:15:26 AM UTC 24
Finished Aug 25 06:15:30 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239360
07 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.123936007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.1093041620
Short name T91
Test name
Test status
Simulation time 1119495039 ps
CPU time 21.02 seconds
Started Aug 25 06:14:47 AM UTC 24
Finished Aug 25 06:15:09 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093041620 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.1093041620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.2533305312
Short name T1114
Test name
Test status
Simulation time 12954785052 ps
CPU time 54.33 seconds
Started Aug 25 06:15:19 AM UTC 24
Finished Aug 25 06:16:15 AM UTC 24
Peak memory 235744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253330
5312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.2533305312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.2601326606
Short name T1107
Test name
Test status
Simulation time 1435739586 ps
CPU time 76.73 seconds
Started Aug 25 06:14:52 AM UTC 24
Finished Aug 25 06:16:11 AM UTC 24
Peak memory 228908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601326606 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.2601326606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.2249381584
Short name T1124
Test name
Test status
Simulation time 29750203056 ps
CPU time 90.62 seconds
Started Aug 25 06:14:48 AM UTC 24
Finished Aug 25 06:16:20 AM UTC 24
Peak memory 1266064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249381584 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.2249381584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.3826686043
Short name T1065
Test name
Test status
Simulation time 5514214449 ps
CPU time 10.55 seconds
Started Aug 25 06:14:57 AM UTC 24
Finished Aug 25 06:15:09 AM UTC 24
Peak memory 297476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826686043 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.3826686043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.1346382152
Short name T1074
Test name
Test status
Simulation time 4545833434 ps
CPU time 12.17 seconds
Started Aug 25 06:15:10 AM UTC 24
Finished Aug 25 06:15:24 AM UTC 24
Peak memory 233792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346382
152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.1346382152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.2052725246
Short name T1078
Test name
Test status
Simulation time 83878333 ps
CPU time 2.14 seconds
Started Aug 25 06:15:26 AM UTC 24
Finished Aug 25 06:15:29 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052725
246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.2052725246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_alert_test.2546791772
Short name T1116
Test name
Test status
Simulation time 32604736 ps
CPU time 0.93 seconds
Started Aug 25 06:16:14 AM UTC 24
Finished Aug 25 06:16:16 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546791772 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2546791772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3660121072
Short name T1094
Test name
Test status
Simulation time 497770987 ps
CPU time 5.8 seconds
Started Aug 25 06:15:44 AM UTC 24
Finished Aug 25 06:15:51 AM UTC 24
Peak memory 226972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660121072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3660121072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.1101361292
Short name T1092
Test name
Test status
Simulation time 130170317 ps
CPU time 10.02 seconds
Started Aug 25 06:15:35 AM UTC 24
Finished Aug 25 06:15:46 AM UTC 24
Peak memory 237700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101361292 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.1101361292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.2591611615
Short name T1168
Test name
Test status
Simulation time 8728738911 ps
CPU time 110.48 seconds
Started Aug 25 06:15:36 AM UTC 24
Finished Aug 25 06:17:29 AM UTC 24
Peak memory 702924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591611615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2591611615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.835082522
Short name T1161
Test name
Test status
Simulation time 2463557207 ps
CPU time 97.37 seconds
Started Aug 25 06:15:34 AM UTC 24
Finished Aug 25 06:17:14 AM UTC 24
Peak memory 788796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835082522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.835082522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.1879742917
Short name T1089
Test name
Test status
Simulation time 274849410 ps
CPU time 1.64 seconds
Started Aug 25 06:15:35 AM UTC 24
Finished Aug 25 06:15:38 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879742917 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.1879742917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.2673162720
Short name T1091
Test name
Test status
Simulation time 961210238 ps
CPU time 9.56 seconds
Started Aug 25 06:15:35 AM UTC 24
Finished Aug 25 06:15:46 AM UTC 24
Peak memory 264548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673162720 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.2673162720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.4184221678
Short name T1204
Test name
Test status
Simulation time 10971428589 ps
CPU time 175.71 seconds
Started Aug 25 06:15:32 AM UTC 24
Finished Aug 25 06:18:31 AM UTC 24
Peak memory 752028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184221678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4184221678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.1271412539
Short name T1128
Test name
Test status
Simulation time 362998618 ps
CPU time 18.95 seconds
Started Aug 25 06:16:09 AM UTC 24
Finished Aug 25 06:16:29 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271412539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1271412539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_override.1511592570
Short name T1084
Test name
Test status
Simulation time 29858617 ps
CPU time 0.99 seconds
Started Aug 25 06:15:32 AM UTC 24
Finished Aug 25 06:15:34 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511592570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1511592570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_perf.3112703345
Short name T1185
Test name
Test status
Simulation time 13425668477 ps
CPU time 142.34 seconds
Started Aug 25 06:15:36 AM UTC 24
Finished Aug 25 06:18:01 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112703345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3112703345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.1751623315
Short name T1097
Test name
Test status
Simulation time 1401900182 ps
CPU time 19.17 seconds
Started Aug 25 06:15:38 AM UTC 24
Finished Aug 25 06:15:59 AM UTC 24
Peak memory 288780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751623315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1751623315
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.2450960255
Short name T1105
Test name
Test status
Simulation time 5450099023 ps
CPU time 36.36 seconds
Started Aug 25 06:15:32 AM UTC 24
Finished Aug 25 06:16:10 AM UTC 24
Peak memory 399640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450960255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2450960255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.3000013654
Short name T1098
Test name
Test status
Simulation time 895188312 ps
CPU time 21.63 seconds
Started Aug 25 06:15:38 AM UTC 24
Finished Aug 25 06:16:01 AM UTC 24
Peak memory 243340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000013654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3000013654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.4163609596
Short name T1111
Test name
Test status
Simulation time 1322719950 ps
CPU time 8.17 seconds
Started Aug 25 06:16:05 AM UTC 24
Finished Aug 25 06:16:14 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4163609596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_ad
dr.4163609596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.3424029396
Short name T1102
Test name
Test status
Simulation time 118239035 ps
CPU time 1.46 seconds
Started Aug 25 06:16:02 AM UTC 24
Finished Aug 25 06:16:05 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424029
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.3424029396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.1969063696
Short name T1103
Test name
Test status
Simulation time 161989930 ps
CPU time 1.81 seconds
Started Aug 25 06:16:02 AM UTC 24
Finished Aug 25 06:16:05 AM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969063
696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.1969063696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.52678193
Short name T1113
Test name
Test status
Simulation time 3868990247 ps
CPU time 3.18 seconds
Started Aug 25 06:16:10 AM UTC 24
Finished Aug 25 06:16:14 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5267819
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermarks
_acq.52678193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.1684716397
Short name T1112
Test name
Test status
Simulation time 539554320 ps
CPU time 2.01 seconds
Started Aug 25 06:16:11 AM UTC 24
Finished Aug 25 06:16:14 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684716
397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark
s_tx.1684716397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.2986902740
Short name T1106
Test name
Test status
Simulation time 5006171706 ps
CPU time 3.47 seconds
Started Aug 25 06:16:06 AM UTC 24
Finished Aug 25 06:16:10 AM UTC 24
Peak memory 228992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986902
740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.2986902740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.3875549180
Short name T1100
Test name
Test status
Simulation time 3919174221 ps
CPU time 9.51 seconds
Started Aug 25 06:15:52 AM UTC 24
Finished Aug 25 06:16:02 AM UTC 24
Peak memory 227248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387554
9180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.3875549180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.1447430019
Short name T1101
Test name
Test status
Simulation time 2832218645 ps
CPU time 6.51 seconds
Started Aug 25 06:15:56 AM UTC 24
Finished Aug 25 06:16:03 AM UTC 24
Peak memory 305368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1447430019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stres
s_wr.1447430019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.3782025754
Short name T1120
Test name
Test status
Simulation time 2028851993 ps
CPU time 4.43 seconds
Started Aug 25 06:16:12 AM UTC 24
Finished Aug 25 06:16:18 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782025
754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.3782025754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.2361221376
Short name T1119
Test name
Test status
Simulation time 578166515 ps
CPU time 4.12 seconds
Started Aug 25 06:16:12 AM UTC 24
Finished Aug 25 06:16:17 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361221
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_ad
dr.2361221376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_perf.3570529686
Short name T1110
Test name
Test status
Simulation time 2602882142 ps
CPU time 7.69 seconds
Started Aug 25 06:16:03 AM UTC 24
Finished Aug 25 06:16:12 AM UTC 24
Peak memory 231340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570529
686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.3570529686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.2055765931
Short name T1117
Test name
Test status
Simulation time 420754886 ps
CPU time 4.24 seconds
Started Aug 25 06:16:11 AM UTC 24
Finished Aug 25 06:16:16 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055765
931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.2055765931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.129269655
Short name T1122
Test name
Test status
Simulation time 862709334 ps
CPU time 30.8 seconds
Started Aug 25 06:15:47 AM UTC 24
Finished Aug 25 06:16:19 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129269655 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.129269655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.2108726796
Short name T1162
Test name
Test status
Simulation time 12652356782 ps
CPU time 67.86 seconds
Started Aug 25 06:16:04 AM UTC 24
Finished Aug 25 06:17:14 AM UTC 24
Peak memory 233804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210872
6796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.2108726796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.81431603
Short name T1096
Test name
Test status
Simulation time 588860305 ps
CPU time 7.46 seconds
Started Aug 25 06:15:48 AM UTC 24
Finished Aug 25 06:15:56 AM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81431603 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.81431603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.3513457606
Short name T1741
Test name
Test status
Simulation time 58120045610 ps
CPU time 1462.07 seconds
Started Aug 25 06:15:47 AM UTC 24
Finished Aug 25 06:40:24 AM UTC 24
Peak memory 9799824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513457606 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.3513457606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.1080739607
Short name T1104
Test name
Test status
Simulation time 1462009816 ps
CPU time 16.27 seconds
Started Aug 25 06:15:51 AM UTC 24
Finished Aug 25 06:16:08 AM UTC 24
Peak memory 335968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080739607 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.1080739607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.4260198192
Short name T1108
Test name
Test status
Simulation time 1464545834 ps
CPU time 12.83 seconds
Started Aug 25 06:15:57 AM UTC 24
Finished Aug 25 06:16:11 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260198
192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.4260198192
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.2485368067
Short name T1115
Test name
Test status
Simulation time 108886919 ps
CPU time 3.2 seconds
Started Aug 25 06:16:11 AM UTC 24
Finished Aug 25 06:16:15 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485368
067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2485368067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_alert_test.4116320075
Short name T1152
Test name
Test status
Simulation time 29752176 ps
CPU time 0.96 seconds
Started Aug 25 06:16:59 AM UTC 24
Finished Aug 25 06:17:01 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116320075 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.4116320075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.1957546790
Short name T1125
Test name
Test status
Simulation time 64481046 ps
CPU time 1.86 seconds
Started Aug 25 06:16:20 AM UTC 24
Finished Aug 25 06:16:23 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957546790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1957546790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.1353383032
Short name T1129
Test name
Test status
Simulation time 1983539926 ps
CPU time 15.04 seconds
Started Aug 25 06:16:18 AM UTC 24
Finished Aug 25 06:16:34 AM UTC 24
Peak memory 321564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353383032 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.1353383032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.3971737680
Short name T1164
Test name
Test status
Simulation time 1710991326 ps
CPU time 57.29 seconds
Started Aug 25 06:16:18 AM UTC 24
Finished Aug 25 06:17:17 AM UTC 24
Peak memory 264396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971737680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3971737680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.3234929849
Short name T1136
Test name
Test status
Simulation time 10036069935 ps
CPU time 113.98 seconds
Started Aug 25 06:16:17 AM UTC 24
Finished Aug 25 06:18:13 AM UTC 24
Peak memory 885164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234929849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3234929849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.52296794
Short name T1127
Test name
Test status
Simulation time 911974112 ps
CPU time 6.37 seconds
Started Aug 25 06:16:18 AM UTC 24
Finished Aug 25 06:16:25 AM UTC 24
Peak memory 250148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52296794 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.52296794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.691393666
Short name T1387
Test name
Test status
Simulation time 4863642423 ps
CPU time 350.21 seconds
Started Aug 25 06:16:16 AM UTC 24
Finished Aug 25 06:22:11 AM UTC 24
Peak memory 1423820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691393666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.691393666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_override.3111784540
Short name T1121
Test name
Test status
Simulation time 21440062 ps
CPU time 1.14 seconds
Started Aug 25 06:16:15 AM UTC 24
Finished Aug 25 06:16:18 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111784540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3111784540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_perf.89989134
Short name T1182
Test name
Test status
Simulation time 3122765407 ps
CPU time 86.49 seconds
Started Aug 25 06:16:19 AM UTC 24
Finished Aug 25 06:17:48 AM UTC 24
Peak memory 283156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89989134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.89989134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.1499036942
Short name T1153
Test name
Test status
Simulation time 2471156593 ps
CPU time 41.18 seconds
Started Aug 25 06:16:19 AM UTC 24
Finished Aug 25 06:17:02 AM UTC 24
Peak memory 581724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499036942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1499036942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.505071050
Short name T1143
Test name
Test status
Simulation time 1779668341 ps
CPU time 37.24 seconds
Started Aug 25 06:16:14 AM UTC 24
Finished Aug 25 06:16:53 AM UTC 24
Peak memory 313672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505071050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.505071050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.737357054
Short name T1132
Test name
Test status
Simulation time 2954996482 ps
CPU time 20.64 seconds
Started Aug 25 06:16:20 AM UTC 24
Finished Aug 25 06:16:42 AM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737357054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.737357054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.4179385805
Short name T1144
Test name
Test status
Simulation time 5035111293 ps
CPU time 8.31 seconds
Started Aug 25 06:16:44 AM UTC 24
Finished Aug 25 06:16:54 AM UTC 24
Peak memory 218768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4179385805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_ad
dr.4179385805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.1110462804
Short name T1133
Test name
Test status
Simulation time 641848923 ps
CPU time 1.58 seconds
Started Aug 25 06:16:40 AM UTC 24
Finished Aug 25 06:16:43 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110462
804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.1110462804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.3741199717
Short name T1137
Test name
Test status
Simulation time 337310342 ps
CPU time 1.6 seconds
Started Aug 25 06:16:43 AM UTC 24
Finished Aug 25 06:16:46 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741199
717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.3741199717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.342096913
Short name T1146
Test name
Test status
Simulation time 296178089 ps
CPU time 2.99 seconds
Started Aug 25 06:16:54 AM UTC 24
Finished Aug 25 06:16:58 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420969
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_acq.342096913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.3977700392
Short name T1145
Test name
Test status
Simulation time 342139347 ps
CPU time 1.46 seconds
Started Aug 25 06:16:54 AM UTC 24
Finished Aug 25 06:16:56 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977700
392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_tx.3977700392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.614127897
Short name T1139
Test name
Test status
Simulation time 1033701982 ps
CPU time 2.75 seconds
Started Aug 25 06:16:46 AM UTC 24
Finished Aug 25 06:16:50 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6141278
97 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.614127897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.1114987542
Short name T1135
Test name
Test status
Simulation time 2066015843 ps
CPU time 11.16 seconds
Started Aug 25 06:16:31 AM UTC 24
Finished Aug 25 06:16:43 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111498
7542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.1114987542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3946104824
Short name T1201
Test name
Test status
Simulation time 15435483172 ps
CPU time 111.9 seconds
Started Aug 25 06:16:35 AM UTC 24
Finished Aug 25 06:18:29 AM UTC 24
Peak memory 1407196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3946104824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stres
s_wr.3946104824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.571371420
Short name T1148
Test name
Test status
Simulation time 1173168343 ps
CPU time 5.02 seconds
Started Aug 25 06:16:54 AM UTC 24
Finished Aug 25 06:17:00 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5713714
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.571371420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.4161406843
Short name T1150
Test name
Test status
Simulation time 500957226 ps
CPU time 4.39 seconds
Started Aug 25 06:16:55 AM UTC 24
Finished Aug 25 06:17:01 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161406
843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_ad
dr.4161406843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.2951329061
Short name T1151
Test name
Test status
Simulation time 137526299 ps
CPU time 2.62 seconds
Started Aug 25 06:16:57 AM UTC 24
Finished Aug 25 06:17:01 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951329
061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_txstretch.2951329061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_perf.3765026258
Short name T1142
Test name
Test status
Simulation time 745780424 ps
CPU time 8.48 seconds
Started Aug 25 06:16:43 AM UTC 24
Finished Aug 25 06:16:53 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765026
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.3765026258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.1195032900
Short name T1147
Test name
Test status
Simulation time 5558812151 ps
CPU time 4.63 seconds
Started Aug 25 06:16:54 AM UTC 24
Finished Aug 25 06:17:00 AM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195032
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.1195032900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.3948941117
Short name T1131
Test name
Test status
Simulation time 1099893819 ps
CPU time 15.84 seconds
Started Aug 25 06:16:21 AM UTC 24
Finished Aug 25 06:16:39 AM UTC 24
Peak memory 231024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948941117 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.3948941117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.1709298561
Short name T1738
Test name
Test status
Simulation time 52492581077 ps
CPU time 1243.97 seconds
Started Aug 25 06:16:44 AM UTC 24
Finished Aug 25 06:37:43 AM UTC 24
Peak memory 7641560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170929
8561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.1709298561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.1454162463
Short name T1138
Test name
Test status
Simulation time 1800437011 ps
CPU time 21.91 seconds
Started Aug 25 06:16:25 AM UTC 24
Finished Aug 25 06:16:49 AM UTC 24
Peak memory 230840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454162463 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.1454162463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2488950024
Short name T1327
Test name
Test status
Simulation time 31582248532 ps
CPU time 277.03 seconds
Started Aug 25 06:16:24 AM UTC 24
Finished Aug 25 06:21:06 AM UTC 24
Peak memory 2998424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488950024 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.2488950024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.2307401784
Short name T1141
Test name
Test status
Simulation time 19851098256 ps
CPU time 12.31 seconds
Started Aug 25 06:16:39 AM UTC 24
Finished Aug 25 06:16:53 AM UTC 24
Peak memory 233076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307401
784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.2307401784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.1725222660
Short name T1149
Test name
Test status
Simulation time 135550975 ps
CPU time 5.37 seconds
Started Aug 25 06:16:54 AM UTC 24
Finished Aug 25 06:17:01 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725222
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1725222660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_alert_test.473871558
Short name T1183
Test name
Test status
Simulation time 127902860 ps
CPU time 0.93 seconds
Started Aug 25 06:17:46 AM UTC 24
Finished Aug 25 06:17:48 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473871558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.473871558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.2026628053
Short name T1163
Test name
Test status
Simulation time 898231104 ps
CPU time 6.69 seconds
Started Aug 25 06:17:08 AM UTC 24
Finished Aug 25 06:17:16 AM UTC 24
Peak memory 256268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026628053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2026628053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.1743022790
Short name T1169
Test name
Test status
Simulation time 1496097146 ps
CPU time 25.08 seconds
Started Aug 25 06:17:03 AM UTC 24
Finished Aug 25 06:17:29 AM UTC 24
Peak memory 301192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743022790 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.1743022790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.1775423584
Short name T1363
Test name
Test status
Simulation time 3761679201 ps
CPU time 282.76 seconds
Started Aug 25 06:17:03 AM UTC 24
Finished Aug 25 06:21:50 AM UTC 24
Peak memory 741596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775423584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1775423584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2568608285
Short name T1218
Test name
Test status
Simulation time 11791797774 ps
CPU time 96.82 seconds
Started Aug 25 06:17:01 AM UTC 24
Finished Aug 25 06:18:40 AM UTC 24
Peak memory 848340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568608285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2568608285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.2235867553
Short name T1157
Test name
Test status
Simulation time 119199534 ps
CPU time 1.67 seconds
Started Aug 25 06:17:01 AM UTC 24
Finished Aug 25 06:17:04 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235867553 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.2235867553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.2902398199
Short name T1160
Test name
Test status
Simulation time 865522698 ps
CPU time 8.42 seconds
Started Aug 25 06:17:03 AM UTC 24
Finished Aug 25 06:17:12 AM UTC 24
Peak memory 258120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902398199 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.2902398199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.207526141
Short name T125
Test name
Test status
Simulation time 6042894022 ps
CPU time 79.68 seconds
Started Aug 25 06:17:01 AM UTC 24
Finished Aug 25 06:18:23 AM UTC 24
Peak memory 987356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207526141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.207526141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.4256779357
Short name T1180
Test name
Test status
Simulation time 652574411 ps
CPU time 4.97 seconds
Started Aug 25 06:17:40 AM UTC 24
Finished Aug 25 06:17:46 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256779357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.4256779357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_override.2909868639
Short name T1155
Test name
Test status
Simulation time 68492239 ps
CPU time 0.94 seconds
Started Aug 25 06:17:01 AM UTC 24
Finished Aug 25 06:17:03 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909868639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2909868639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_perf.2301741856
Short name T1174
Test name
Test status
Simulation time 2718786917 ps
CPU time 36.46 seconds
Started Aug 25 06:17:04 AM UTC 24
Finished Aug 25 06:17:42 AM UTC 24
Peak memory 264400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301741856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2301741856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.1722597042
Short name T1159
Test name
Test status
Simulation time 132874345 ps
CPU time 3.36 seconds
Started Aug 25 06:17:05 AM UTC 24
Finished Aug 25 06:17:09 AM UTC 24
Peak memory 237060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722597042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1722597042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.2467937296
Short name T1166
Test name
Test status
Simulation time 12619125597 ps
CPU time 26.51 seconds
Started Aug 25 06:17:00 AM UTC 24
Finished Aug 25 06:17:28 AM UTC 24
Peak memory 313464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467937296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2467937296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.3462498598
Short name T1175
Test name
Test status
Simulation time 2139708403 ps
CPU time 35.71 seconds
Started Aug 25 06:17:05 AM UTC 24
Finished Aug 25 06:17:42 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462498598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3462498598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.3837105557
Short name T1179
Test name
Test status
Simulation time 5220062831 ps
CPU time 9.53 seconds
Started Aug 25 06:17:34 AM UTC 24
Finished Aug 25 06:17:45 AM UTC 24
Peak memory 233904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3837105557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_ad
dr.3837105557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.2067879099
Short name T1171
Test name
Test status
Simulation time 338407317 ps
CPU time 1.82 seconds
Started Aug 25 06:17:30 AM UTC 24
Finished Aug 25 06:17:33 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067879
099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.2067879099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.1898639794
Short name T1170
Test name
Test status
Simulation time 540387234 ps
CPU time 1.76 seconds
Started Aug 25 06:17:30 AM UTC 24
Finished Aug 25 06:17:33 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898639
794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.1898639794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.2168202396
Short name T1178
Test name
Test status
Simulation time 935534083 ps
CPU time 3.05 seconds
Started Aug 25 06:17:40 AM UTC 24
Finished Aug 25 06:17:44 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168202
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermar
ks_acq.2168202396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.1994529055
Short name T1177
Test name
Test status
Simulation time 456137383 ps
CPU time 1.64 seconds
Started Aug 25 06:17:41 AM UTC 24
Finished Aug 25 06:17:44 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994529
055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.1994529055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.2981832483
Short name T1167
Test name
Test status
Simulation time 3666365900 ps
CPU time 11.04 seconds
Started Aug 25 06:17:16 AM UTC 24
Finished Aug 25 06:17:29 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298183
2483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.2981832483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.1692050030
Short name T1228
Test name
Test status
Simulation time 34563960358 ps
CPU time 95.2 seconds
Started Aug 25 06:17:17 AM UTC 24
Finished Aug 25 06:18:55 AM UTC 24
Peak memory 1702032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1692050030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stres
s_wr.1692050030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.552306811
Short name T1187
Test name
Test status
Simulation time 4219139187 ps
CPU time 5.49 seconds
Started Aug 25 06:17:44 AM UTC 24
Finished Aug 25 06:17:50 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5523068
11 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.552306811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.1831830936
Short name T1188
Test name
Test status
Simulation time 591923949 ps
CPU time 5.66 seconds
Started Aug 25 06:17:45 AM UTC 24
Finished Aug 25 06:17:51 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831830
936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.1831830936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_perf.3489030264
Short name T1173
Test name
Test status
Simulation time 3302102504 ps
CPU time 8.03 seconds
Started Aug 25 06:17:30 AM UTC 24
Finished Aug 25 06:17:39 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489030
264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.3489030264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3412388627
Short name T1181
Test name
Test status
Simulation time 991561850 ps
CPU time 3.38 seconds
Started Aug 25 06:17:43 AM UTC 24
Finished Aug 25 06:17:47 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412388
627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.3412388627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1996057709
Short name T1193
Test name
Test status
Simulation time 1083074485 ps
CPU time 44.54 seconds
Started Aug 25 06:17:13 AM UTC 24
Finished Aug 25 06:17:59 AM UTC 24
Peak memory 231164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996057709 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.1996057709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.4156420659
Short name T1334
Test name
Test status
Simulation time 15141332266 ps
CPU time 218.63 seconds
Started Aug 25 06:17:33 AM UTC 24
Finished Aug 25 06:21:15 AM UTC 24
Peak memory 1669404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415642
0659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.4156420659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.4044529163
Short name T1184
Test name
Test status
Simulation time 1319091981 ps
CPU time 32.49 seconds
Started Aug 25 06:17:15 AM UTC 24
Finished Aug 25 06:17:49 AM UTC 24
Peak memory 243924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044529163 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.4044529163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.4093517630
Short name T1383
Test name
Test status
Simulation time 50619898422 ps
CPU time 281.58 seconds
Started Aug 25 06:17:14 AM UTC 24
Finished Aug 25 06:22:00 AM UTC 24
Peak memory 2943128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093517630 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.4093517630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.1146217457
Short name T1165
Test name
Test status
Simulation time 1561036164 ps
CPU time 4.62 seconds
Started Aug 25 06:17:16 AM UTC 24
Finished Aug 25 06:17:22 AM UTC 24
Peak memory 233328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146217457 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.1146217457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2677203720
Short name T1172
Test name
Test status
Simulation time 5702342914 ps
CPU time 12.58 seconds
Started Aug 25 06:17:23 AM UTC 24
Finished Aug 25 06:17:36 AM UTC 24
Peak memory 231088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677203
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.2677203720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.2477003872
Short name T1118
Test name
Test status
Simulation time 972132106 ps
CPU time 19.33 seconds
Started Aug 25 06:17:42 AM UTC 24
Finished Aug 25 06:18:03 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477003
872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2477003872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_alert_test.4163719833
Short name T1212
Test name
Test status
Simulation time 27150988 ps
CPU time 0.91 seconds
Started Aug 25 06:18:35 AM UTC 24
Finished Aug 25 06:18:37 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163719833 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.4163719833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2945206410
Short name T1134
Test name
Test status
Simulation time 226960201 ps
CPU time 2.19 seconds
Started Aug 25 06:18:00 AM UTC 24
Finished Aug 25 06:18:03 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945206410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2945206410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.4010288201
Short name T1191
Test name
Test status
Simulation time 256243508 ps
CPU time 7.33 seconds
Started Aug 25 06:17:50 AM UTC 24
Finished Aug 25 06:17:59 AM UTC 24
Peak memory 266376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010288201 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.4010288201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.3698370986
Short name T1257
Test name
Test status
Simulation time 3352429375 ps
CPU time 106.58 seconds
Started Aug 25 06:17:51 AM UTC 24
Finished Aug 25 06:19:40 AM UTC 24
Peak memory 524752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698370986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3698370986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3918122954
Short name T1286
Test name
Test status
Simulation time 1999981489 ps
CPU time 139.49 seconds
Started Aug 25 06:17:49 AM UTC 24
Finished Aug 25 06:20:12 AM UTC 24
Peak memory 589920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918122954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3918122954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2775786649
Short name T1189
Test name
Test status
Simulation time 101351613 ps
CPU time 1.96 seconds
Started Aug 25 06:17:50 AM UTC 24
Finished Aug 25 06:17:53 AM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775786649 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.2775786649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.57427868
Short name T1192
Test name
Test status
Simulation time 216288398 ps
CPU time 6.63 seconds
Started Aug 25 06:17:51 AM UTC 24
Finished Aug 25 06:17:59 AM UTC 24
Peak memory 247956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57427868 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.57427868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1471915723
Short name T1280
Test name
Test status
Simulation time 19010696525 ps
CPU time 132.57 seconds
Started Aug 25 06:17:49 AM UTC 24
Finished Aug 25 06:20:04 AM UTC 24
Peak memory 1384608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471915723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1471915723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.2916422963
Short name T1211
Test name
Test status
Simulation time 10528806599 ps
CPU time 9.05 seconds
Started Aug 25 06:18:26 AM UTC 24
Finished Aug 25 06:18:36 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916422963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2916422963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_override.3127173036
Short name T1186
Test name
Test status
Simulation time 25371436 ps
CPU time 0.95 seconds
Started Aug 25 06:17:48 AM UTC 24
Finished Aug 25 06:17:50 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127173036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3127173036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_perf.1479285574
Short name T1344
Test name
Test status
Simulation time 6994279448 ps
CPU time 208.47 seconds
Started Aug 25 06:17:52 AM UTC 24
Finished Aug 25 06:21:25 AM UTC 24
Peak memory 1429708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479285574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1479285574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.3848295306
Short name T1190
Test name
Test status
Simulation time 117152719 ps
CPU time 1.97 seconds
Started Aug 25 06:17:55 AM UTC 24
Finished Aug 25 06:17:58 AM UTC 24
Peak memory 236424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848295306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3848295306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.1075997324
Short name T1217
Test name
Test status
Simulation time 3906159653 ps
CPU time 51.13 seconds
Started Aug 25 06:17:47 AM UTC 24
Finished Aug 25 06:18:40 AM UTC 24
Peak memory 444900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075997324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1075997324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_stress_all.1076933619
Short name T303
Test name
Test status
Simulation time 23617072336 ps
CPU time 2032.19 seconds
Started Aug 25 06:18:00 AM UTC 24
Finished Aug 25 06:52:15 AM UTC 24
Peak memory 3905932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076933619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1076933619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.2398041421
Short name T1194
Test name
Test status
Simulation time 3180762454 ps
CPU time 14.26 seconds
Started Aug 25 06:17:59 AM UTC 24
Finished Aug 25 06:18:14 AM UTC 24
Peak memory 231404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398041421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2398041421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.2009835070
Short name T1208
Test name
Test status
Simulation time 1967794621 ps
CPU time 10.16 seconds
Started Aug 25 06:18:23 AM UTC 24
Finished Aug 25 06:18:34 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2009835070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_ad
dr.2009835070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.4107718889
Short name T1196
Test name
Test status
Simulation time 559412592 ps
CPU time 1.97 seconds
Started Aug 25 06:18:17 AM UTC 24
Finished Aug 25 06:18:20 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107718
889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.4107718889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.736765599
Short name T1198
Test name
Test status
Simulation time 536207493 ps
CPU time 1.86 seconds
Started Aug 25 06:18:20 AM UTC 24
Finished Aug 25 06:18:23 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7367655
99 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.736765599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.2481478355
Short name T1206
Test name
Test status
Simulation time 452557540 ps
CPU time 3.72 seconds
Started Aug 25 06:18:28 AM UTC 24
Finished Aug 25 06:18:33 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481478
355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermar
ks_acq.2481478355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.1014506797
Short name T1205
Test name
Test status
Simulation time 442394283 ps
CPU time 1.33 seconds
Started Aug 25 06:18:29 AM UTC 24
Finished Aug 25 06:18:32 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014506
797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.1014506797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.2374035425
Short name T1140
Test name
Test status
Simulation time 1978151665 ps
CPU time 4.31 seconds
Started Aug 25 06:18:04 AM UTC 24
Finished Aug 25 06:18:10 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237403
5425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.2374035425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3839271381
Short name T1251
Test name
Test status
Simulation time 6003435011 ps
CPU time 69.32 seconds
Started Aug 25 06:18:10 AM UTC 24
Finished Aug 25 06:19:22 AM UTC 24
Peak memory 1503640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3839271381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.3839271381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.1316613646
Short name T1215
Test name
Test status
Simulation time 1241687162 ps
CPU time 6.19 seconds
Started Aug 25 06:18:32 AM UTC 24
Finished Aug 25 06:18:39 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316613
646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.1316613646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.3047863556
Short name T1214
Test name
Test status
Simulation time 854071680 ps
CPU time 4.61 seconds
Started Aug 25 06:18:33 AM UTC 24
Finished Aug 25 06:18:38 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047863
556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_ad
dr.3047863556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_perf.3219575865
Short name T1200
Test name
Test status
Simulation time 4319744167 ps
CPU time 6.43 seconds
Started Aug 25 06:18:20 AM UTC 24
Finished Aug 25 06:18:27 AM UTC 24
Peak memory 233636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219575
865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.3219575865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.2178336864
Short name T1210
Test name
Test status
Simulation time 4608576473 ps
CPU time 3.1 seconds
Started Aug 25 06:18:31 AM UTC 24
Finished Aug 25 06:18:36 AM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178336
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.2178336864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.3476402965
Short name T1220
Test name
Test status
Simulation time 4028505501 ps
CPU time 40.89 seconds
Started Aug 25 06:18:00 AM UTC 24
Finished Aug 25 06:18:43 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476402965 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.3476402965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2325120635
Short name T1739
Test name
Test status
Simulation time 48425417660 ps
CPU time 1186.74 seconds
Started Aug 25 06:18:21 AM UTC 24
Finished Aug 25 06:38:21 AM UTC 24
Peak memory 6490328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232512
0635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.2325120635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3109288842
Short name T1224
Test name
Test status
Simulation time 8019144348 ps
CPU time 43.5 seconds
Started Aug 25 06:18:02 AM UTC 24
Finished Aug 25 06:18:47 AM UTC 24
Peak memory 250084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109288842 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.3109288842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.3397797844
Short name T1342
Test name
Test status
Simulation time 54469276086 ps
CPU time 198.62 seconds
Started Aug 25 06:18:00 AM UTC 24
Finished Aug 25 06:21:23 AM UTC 24
Peak memory 2207952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397797844 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.3397797844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.234683484
Short name T1199
Test name
Test status
Simulation time 1215251915 ps
CPU time 10.02 seconds
Started Aug 25 06:18:14 AM UTC 24
Finished Aug 25 06:18:26 AM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346834
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.234683484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.1655449684
Short name T1207
Test name
Test status
Simulation time 67933236 ps
CPU time 2.01 seconds
Started Aug 25 06:18:30 AM UTC 24
Finished Aug 25 06:18:34 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655449
684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.1655449684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_alert_test.2044940724
Short name T1244
Test name
Test status
Simulation time 15549450 ps
CPU time 0.98 seconds
Started Aug 25 06:19:12 AM UTC 24
Finished Aug 25 06:19:14 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044940724 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2044940724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.2820165700
Short name T1222
Test name
Test status
Simulation time 231147753 ps
CPU time 2.42 seconds
Started Aug 25 06:18:42 AM UTC 24
Finished Aug 25 06:18:46 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820165700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2820165700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.828578317
Short name T1223
Test name
Test status
Simulation time 1452753684 ps
CPU time 7.87 seconds
Started Aug 25 06:18:38 AM UTC 24
Finished Aug 25 06:18:47 AM UTC 24
Peak memory 268488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828578317 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.828578317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.1770759905
Short name T1335
Test name
Test status
Simulation time 20163360551 ps
CPU time 154.64 seconds
Started Aug 25 06:18:39 AM UTC 24
Finished Aug 25 06:21:17 AM UTC 24
Peak memory 706836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770759905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1770759905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.1058964838
Short name T1262
Test name
Test status
Simulation time 2112255770 ps
CPU time 70.19 seconds
Started Aug 25 06:18:37 AM UTC 24
Finished Aug 25 06:19:49 AM UTC 24
Peak memory 559236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058964838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1058964838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.304563913
Short name T1219
Test name
Test status
Simulation time 275664620 ps
CPU time 1.36 seconds
Started Aug 25 06:18:38 AM UTC 24
Finished Aug 25 06:18:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304563913 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.304563913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.709794112
Short name T1225
Test name
Test status
Simulation time 128618982 ps
CPU time 8.14 seconds
Started Aug 25 06:18:38 AM UTC 24
Finished Aug 25 06:18:47 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709794112 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.709794112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.3805885079
Short name T1285
Test name
Test status
Simulation time 14776388999 ps
CPU time 92.01 seconds
Started Aug 25 06:18:37 AM UTC 24
Finished Aug 25 06:20:11 AM UTC 24
Peak memory 1050944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805885079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3805885079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.3987640801
Short name T1254
Test name
Test status
Simulation time 2086301124 ps
CPU time 21.96 seconds
Started Aug 25 06:19:01 AM UTC 24
Finished Aug 25 06:19:24 AM UTC 24
Peak memory 216680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987640801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3987640801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.3888055633
Short name T1236
Test name
Test status
Simulation time 94611400 ps
CPU time 2.6 seconds
Started Aug 25 06:19:00 AM UTC 24
Finished Aug 25 06:19:04 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888055633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3888055633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_override.2301381270
Short name T284
Test name
Test status
Simulation time 17674115 ps
CPU time 0.97 seconds
Started Aug 25 06:18:36 AM UTC 24
Finished Aug 25 06:18:38 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301381270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2301381270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_perf.1085024240
Short name T1409
Test name
Test status
Simulation time 27353756973 ps
CPU time 233.36 seconds
Started Aug 25 06:18:40 AM UTC 24
Finished Aug 25 06:22:38 AM UTC 24
Peak memory 252308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085024240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1085024240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.4053296573
Short name T1221
Test name
Test status
Simulation time 78248572 ps
CPU time 1.7 seconds
Started Aug 25 06:18:40 AM UTC 24
Finished Aug 25 06:18:43 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053296573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.4053296573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.3080461600
Short name T1246
Test name
Test status
Simulation time 7232361957 ps
CPU time 38.31 seconds
Started Aug 25 06:18:35 AM UTC 24
Finished Aug 25 06:19:15 AM UTC 24
Peak memory 375044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080461600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3080461600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.207591721
Short name T1751
Test name
Test status
Simulation time 86308453554 ps
CPU time 3062.74 seconds
Started Aug 25 06:18:42 AM UTC 24
Finished Aug 25 07:10:20 AM UTC 24
Peak memory 4723336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207591721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.207591721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.640982293
Short name T1227
Test name
Test status
Simulation time 11293981788 ps
CPU time 11.56 seconds
Started Aug 25 06:18:40 AM UTC 24
Finished Aug 25 06:18:53 AM UTC 24
Peak memory 229308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640982293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.640982293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.2652407367
Short name T1239
Test name
Test status
Simulation time 854192849 ps
CPU time 8.22 seconds
Started Aug 25 06:18:59 AM UTC 24
Finished Aug 25 06:19:08 AM UTC 24
Peak memory 230916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2652407367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_ad
dr.2652407367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3687181272
Short name T1231
Test name
Test status
Simulation time 258841569 ps
CPU time 2.55 seconds
Started Aug 25 06:18:54 AM UTC 24
Finished Aug 25 06:18:58 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687181
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3687181272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.4024981069
Short name T1230
Test name
Test status
Simulation time 203900796 ps
CPU time 1.33 seconds
Started Aug 25 06:18:55 AM UTC 24
Finished Aug 25 06:18:58 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024981
069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.4024981069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.313895235
Short name T1240
Test name
Test status
Simulation time 1056397229 ps
CPU time 4.72 seconds
Started Aug 25 06:19:03 AM UTC 24
Finished Aug 25 06:19:09 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138952
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_acq.313895235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2623982480
Short name T1238
Test name
Test status
Simulation time 705131537 ps
CPU time 2.57 seconds
Started Aug 25 06:19:04 AM UTC 24
Finished Aug 25 06:19:08 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623982
480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_tx.2623982480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_hrst.4253349181
Short name T1234
Test name
Test status
Simulation time 318348603 ps
CPU time 2.18 seconds
Started Aug 25 06:18:59 AM UTC 24
Finished Aug 25 06:19:02 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253349
181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_hrst.4253349181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.2268817122
Short name T1232
Test name
Test status
Simulation time 995769797 ps
CPU time 9.73 seconds
Started Aug 25 06:18:48 AM UTC 24
Finished Aug 25 06:18:59 AM UTC 24
Peak memory 233456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226881
7122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.2268817122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.399516427
Short name T1396
Test name
Test status
Simulation time 15928397412 ps
CPU time 214.59 seconds
Started Aug 25 06:18:48 AM UTC 24
Finished Aug 25 06:22:27 AM UTC 24
Peak memory 2400404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=399516427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stress
_wr.399516427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.3991621053
Short name T1247
Test name
Test status
Simulation time 2144114915 ps
CPU time 5.41 seconds
Started Aug 25 06:19:09 AM UTC 24
Finished Aug 25 06:19:16 AM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991621
053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.3991621053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.3138139257
Short name T1248
Test name
Test status
Simulation time 1376073049 ps
CPU time 5.36 seconds
Started Aug 25 06:19:09 AM UTC 24
Finished Aug 25 06:19:16 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138139
257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_ad
dr.3138139257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_nack_txstretch.3813090283
Short name T1245
Test name
Test status
Simulation time 896056996 ps
CPU time 2.3 seconds
Started Aug 25 06:19:10 AM UTC 24
Finished Aug 25 06:19:14 AM UTC 24
Peak memory 233488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813090
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_txstretch.3813090283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3676762915
Short name T1235
Test name
Test status
Simulation time 935742756 ps
CPU time 4.47 seconds
Started Aug 25 06:18:58 AM UTC 24
Finished Aug 25 06:19:03 AM UTC 24
Peak memory 231160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676762
915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.3676762915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.1805880809
Short name T1242
Test name
Test status
Simulation time 3812722864 ps
CPU time 5.11 seconds
Started Aug 25 06:19:05 AM UTC 24
Finished Aug 25 06:19:12 AM UTC 24
Peak memory 216496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805880
809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.1805880809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.1507737265
Short name T1237
Test name
Test status
Simulation time 4594229887 ps
CPU time 19.59 seconds
Started Aug 25 06:18:44 AM UTC 24
Finished Aug 25 06:19:05 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507737265 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.1507737265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.2740196435
Short name T1291
Test name
Test status
Simulation time 9756800853 ps
CPU time 80.49 seconds
Started Aug 25 06:18:58 AM UTC 24
Finished Aug 25 06:20:20 AM UTC 24
Peak memory 241832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274019
6435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.2740196435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.4217137072
Short name T1203
Test name
Test status
Simulation time 1150826933 ps
CPU time 64.92 seconds
Started Aug 25 06:18:47 AM UTC 24
Finished Aug 25 06:19:54 AM UTC 24
Peak memory 229048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217137072 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.4217137072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1462837296
Short name T1267
Test name
Test status
Simulation time 40804448091 ps
CPU time 67.03 seconds
Started Aug 25 06:18:44 AM UTC 24
Finished Aug 25 06:19:53 AM UTC 24
Peak memory 876756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462837296 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.1462837296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.2811233172
Short name T1241
Test name
Test status
Simulation time 2139915284 ps
CPU time 21.14 seconds
Started Aug 25 06:18:48 AM UTC 24
Finished Aug 25 06:19:11 AM UTC 24
Peak memory 422056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811233172 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.2811233172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.852346065
Short name T1233
Test name
Test status
Simulation time 4242126689 ps
CPU time 8.82 seconds
Started Aug 25 06:18:50 AM UTC 24
Finished Aug 25 06:19:00 AM UTC 24
Peak memory 233636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8523460
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.852346065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.2348851688
Short name T1243
Test name
Test status
Simulation time 295049440 ps
CPU time 7.69 seconds
Started Aug 25 06:19:04 AM UTC 24
Finished Aug 25 06:19:13 AM UTC 24
Peak memory 216484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348851
688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2348851688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_alert_test.162544591
Short name T1277
Test name
Test status
Simulation time 42424159 ps
CPU time 1.03 seconds
Started Aug 25 06:20:02 AM UTC 24
Finished Aug 25 06:20:04 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162544591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.162544591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.2237724916
Short name T1256
Test name
Test status
Simulation time 235565515 ps
CPU time 10.51 seconds
Started Aug 25 06:19:24 AM UTC 24
Finished Aug 25 06:19:36 AM UTC 24
Peak memory 227076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237724916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2237724916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.4131164701
Short name T1263
Test name
Test status
Simulation time 2001579257 ps
CPU time 30.82 seconds
Started Aug 25 06:19:17 AM UTC 24
Finished Aug 25 06:19:49 AM UTC 24
Peak memory 327764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131164701 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.4131164701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.2308583592
Short name T1352
Test name
Test status
Simulation time 17811534135 ps
CPU time 140.31 seconds
Started Aug 25 06:19:17 AM UTC 24
Finished Aug 25 06:21:40 AM UTC 24
Peak memory 706760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308583592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2308583592
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.2359811489
Short name T1394
Test name
Test status
Simulation time 9143397868 ps
CPU time 186.65 seconds
Started Aug 25 06:19:15 AM UTC 24
Finished Aug 25 06:22:25 AM UTC 24
Peak memory 770392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359811489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2359811489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.3822105470
Short name T1250
Test name
Test status
Simulation time 1645144332 ps
CPU time 1.48 seconds
Started Aug 25 06:19:16 AM UTC 24
Finished Aug 25 06:19:18 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822105470 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.3822105470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.1699727799
Short name T1255
Test name
Test status
Simulation time 365947368 ps
CPU time 7.12 seconds
Started Aug 25 06:19:17 AM UTC 24
Finished Aug 25 06:19:25 AM UTC 24
Peak memory 249992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699727799 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.1699727799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.1560935886
Short name T1445
Test name
Test status
Simulation time 26586619556 ps
CPU time 249.02 seconds
Started Aug 25 06:19:15 AM UTC 24
Finished Aug 25 06:23:28 AM UTC 24
Peak memory 1099984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560935886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1560935886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.1892659600
Short name T1287
Test name
Test status
Simulation time 328953390 ps
CPU time 16.59 seconds
Started Aug 25 06:19:54 AM UTC 24
Finished Aug 25 06:20:12 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892659600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1892659600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_mode_toggle.2539198775
Short name T1216
Test name
Test status
Simulation time 463322922 ps
CPU time 2.34 seconds
Started Aug 25 06:19:54 AM UTC 24
Finished Aug 25 06:19:57 AM UTC 24
Peak memory 216800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539198775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2539198775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_override.645807669
Short name T1249
Test name
Test status
Simulation time 115027905 ps
CPU time 1.08 seconds
Started Aug 25 06:19:14 AM UTC 24
Finished Aug 25 06:19:16 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645807669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.645807669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_perf.2211121250
Short name T1627
Test name
Test status
Simulation time 50964972426 ps
CPU time 457.15 seconds
Started Aug 25 06:19:19 AM UTC 24
Finished Aug 25 06:27:04 AM UTC 24
Peak memory 2502812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211121250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2211121250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.2447400083
Short name T1253
Test name
Test status
Simulation time 770884698 ps
CPU time 3.39 seconds
Started Aug 25 06:19:19 AM UTC 24
Finished Aug 25 06:19:24 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447400083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2447400083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1440901897
Short name T1264
Test name
Test status
Simulation time 4136185207 ps
CPU time 36.78 seconds
Started Aug 25 06:19:13 AM UTC 24
Finished Aug 25 06:19:51 AM UTC 24
Peak memory 332076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440901897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1440901897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.1068820888
Short name T1258
Test name
Test status
Simulation time 740839329 ps
CPU time 17.48 seconds
Started Aug 25 06:19:22 AM UTC 24
Finished Aug 25 06:19:41 AM UTC 24
Peak memory 229164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068820888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1068820888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.3071360340
Short name T1275
Test name
Test status
Simulation time 1373379122 ps
CPU time 7.48 seconds
Started Aug 25 06:19:54 AM UTC 24
Finished Aug 25 06:20:02 AM UTC 24
Peak memory 233852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3071360340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.3071360340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.3922984586
Short name T1268
Test name
Test status
Simulation time 152211457 ps
CPU time 1.4 seconds
Started Aug 25 06:19:50 AM UTC 24
Finished Aug 25 06:19:53 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922984
586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.3922984586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.1332153977
Short name T1213
Test name
Test status
Simulation time 231589696 ps
CPU time 2.29 seconds
Started Aug 25 06:19:50 AM UTC 24
Finished Aug 25 06:19:54 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332153
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.1332153977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.3901441111
Short name T1273
Test name
Test status
Simulation time 1166004234 ps
CPU time 5.3 seconds
Started Aug 25 06:19:54 AM UTC 24
Finished Aug 25 06:20:00 AM UTC 24
Peak memory 216476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901441
111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar
ks_acq.3901441111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.946656781
Short name T1269
Test name
Test status
Simulation time 111905085 ps
CPU time 1.88 seconds
Started Aug 25 06:19:55 AM UTC 24
Finished Aug 25 06:19:58 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9466567
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermarks
_tx.946656781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.3971007845
Short name T1266
Test name
Test status
Simulation time 899951558 ps
CPU time 9.31 seconds
Started Aug 25 06:19:42 AM UTC 24
Finished Aug 25 06:19:53 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397100
7845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.3971007845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.3493957596
Short name T1261
Test name
Test status
Simulation time 3533034871 ps
CPU time 4.74 seconds
Started Aug 25 06:19:43 AM UTC 24
Finished Aug 25 06:19:49 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3493957596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stres
s_wr.3493957596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.474315095
Short name T1281
Test name
Test status
Simulation time 563276242 ps
CPU time 4.21 seconds
Started Aug 25 06:19:59 AM UTC 24
Finished Aug 25 06:20:05 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4743150
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.474315095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.4034537182
Short name T1279
Test name
Test status
Simulation time 3448449883 ps
CPU time 3.8 seconds
Started Aug 25 06:19:59 AM UTC 24
Finished Aug 25 06:20:04 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034537
182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.4034537182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.3085243085
Short name T1278
Test name
Test status
Simulation time 629450992 ps
CPU time 2.41 seconds
Started Aug 25 06:20:00 AM UTC 24
Finished Aug 25 06:20:04 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085243
085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_txstretch.3085243085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_perf.1481676157
Short name T1272
Test name
Test status
Simulation time 15072202853 ps
CPU time 7.41 seconds
Started Aug 25 06:19:52 AM UTC 24
Finished Aug 25 06:20:00 AM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481676
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.1481676157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.3725278673
Short name T1276
Test name
Test status
Simulation time 1004804195 ps
CPU time 3.58 seconds
Started Aug 25 06:19:58 AM UTC 24
Finished Aug 25 06:20:03 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725278
673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.3725278673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.866970951
Short name T1260
Test name
Test status
Simulation time 4591101720 ps
CPU time 21.77 seconds
Started Aug 25 06:19:26 AM UTC 24
Finished Aug 25 06:19:49 AM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866970951 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.866970951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.1285501399
Short name T1548
Test name
Test status
Simulation time 65570615901 ps
CPU time 328.25 seconds
Started Aug 25 06:19:52 AM UTC 24
Finished Aug 25 06:25:25 AM UTC 24
Peak memory 2195604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128550
1399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.1285501399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.2874604844
Short name T1202
Test name
Test status
Simulation time 6174378956 ps
CPU time 16.06 seconds
Started Aug 25 06:19:36 AM UTC 24
Finished Aug 25 06:19:53 AM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874604844 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.2874604844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.1362120304
Short name T1367
Test name
Test status
Simulation time 28795913197 ps
CPU time 198.53 seconds
Started Aug 25 06:19:27 AM UTC 24
Finished Aug 25 06:22:49 AM UTC 24
Peak memory 2271384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362120304 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.1362120304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.903262291
Short name T1271
Test name
Test status
Simulation time 3613133864 ps
CPU time 16.99 seconds
Started Aug 25 06:19:41 AM UTC 24
Finished Aug 25 06:19:59 AM UTC 24
Peak memory 385164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903262291 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.903262291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.3216350310
Short name T1274
Test name
Test status
Simulation time 3187832820 ps
CPU time 10.2 seconds
Started Aug 25 06:19:50 AM UTC 24
Finished Aug 25 06:20:02 AM UTC 24
Peak memory 233292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216350
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.3216350310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.436140612
Short name T1270
Test name
Test status
Simulation time 51283402 ps
CPU time 2.42 seconds
Started Aug 25 06:19:55 AM UTC 24
Finished Aug 25 06:19:59 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4361406
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.436140612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_alert_test.2543297945
Short name T1307
Test name
Test status
Simulation time 52757964 ps
CPU time 0.99 seconds
Started Aug 25 06:20:35 AM UTC 24
Finished Aug 25 06:20:37 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543297945 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2543297945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.3178967495
Short name T1288
Test name
Test status
Simulation time 181402745 ps
CPU time 2.67 seconds
Started Aug 25 06:20:09 AM UTC 24
Finished Aug 25 06:20:13 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178967495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3178967495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.2121952652
Short name T1292
Test name
Test status
Simulation time 255018945 ps
CPU time 15.39 seconds
Started Aug 25 06:20:05 AM UTC 24
Finished Aug 25 06:20:22 AM UTC 24
Peak memory 270668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121952652 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.2121952652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.2126893763
Short name T1354
Test name
Test status
Simulation time 2863374251 ps
CPU time 95.39 seconds
Started Aug 25 06:20:05 AM UTC 24
Finished Aug 25 06:21:43 AM UTC 24
Peak memory 496084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126893763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2126893763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.4004259113
Short name T1349
Test name
Test status
Simulation time 4646141824 ps
CPU time 87.88 seconds
Started Aug 25 06:20:04 AM UTC 24
Finished Aug 25 06:21:34 AM UTC 24
Peak memory 811480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004259113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.4004259113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.3936635931
Short name T1283
Test name
Test status
Simulation time 660125071 ps
CPU time 2.19 seconds
Started Aug 25 06:20:05 AM UTC 24
Finished Aug 25 06:20:08 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936635931 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.3936635931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.2308162557
Short name T1290
Test name
Test status
Simulation time 374669511 ps
CPU time 12.48 seconds
Started Aug 25 06:20:05 AM UTC 24
Finished Aug 25 06:20:19 AM UTC 24
Peak memory 254344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308162557 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.2308162557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1627326438
Short name T1408
Test name
Test status
Simulation time 4928157849 ps
CPU time 150.5 seconds
Started Aug 25 06:20:04 AM UTC 24
Finished Aug 25 06:22:37 AM UTC 24
Peak memory 1423500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627326438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1627326438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.585495284
Short name T1311
Test name
Test status
Simulation time 409894144 ps
CPU time 6.57 seconds
Started Aug 25 06:20:31 AM UTC 24
Finished Aug 25 06:20:38 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585495284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.585495284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_mode_toggle.1549222993
Short name T1303
Test name
Test status
Simulation time 142879866 ps
CPU time 3.32 seconds
Started Aug 25 06:20:29 AM UTC 24
Finished Aug 25 06:20:33 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549222993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1549222993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_override.878608913
Short name T1282
Test name
Test status
Simulation time 77898178 ps
CPU time 0.99 seconds
Started Aug 25 06:20:03 AM UTC 24
Finished Aug 25 06:20:05 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878608913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.878608913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_perf.3469980179
Short name T1289
Test name
Test status
Simulation time 1185934126 ps
CPU time 8.25 seconds
Started Aug 25 06:20:05 AM UTC 24
Finished Aug 25 06:20:15 AM UTC 24
Peak memory 256084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469980179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3469980179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.954988876
Short name T1284
Test name
Test status
Simulation time 94436630 ps
CPU time 1.91 seconds
Started Aug 25 06:20:06 AM UTC 24
Finished Aug 25 06:20:09 AM UTC 24
Peak memory 234380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954988876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.954988876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.4126395613
Short name T1298
Test name
Test status
Simulation time 5248164106 ps
CPU time 26.73 seconds
Started Aug 25 06:20:02 AM UTC 24
Finished Aug 25 06:20:30 AM UTC 24
Peak memory 317664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126395613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.4126395613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.4082947679
Short name T1318
Test name
Test status
Simulation time 2832973480 ps
CPU time 38.21 seconds
Started Aug 25 06:20:06 AM UTC 24
Finished Aug 25 06:20:46 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082947679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4082947679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.2690677084
Short name T1306
Test name
Test status
Simulation time 977805528 ps
CPU time 8.25 seconds
Started Aug 25 06:20:25 AM UTC 24
Finished Aug 25 06:20:35 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2690677084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad
dr.2690677084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.3657936026
Short name T1295
Test name
Test status
Simulation time 274114326 ps
CPU time 1.53 seconds
Started Aug 25 06:20:22 AM UTC 24
Finished Aug 25 06:20:25 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657936
026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.3657936026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.595994607
Short name T1296
Test name
Test status
Simulation time 318546354 ps
CPU time 1.41 seconds
Started Aug 25 06:20:25 AM UTC 24
Finished Aug 25 06:20:28 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5959946
07 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.595994607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.1892332115
Short name T1310
Test name
Test status
Simulation time 2439383314 ps
CPU time 5.21 seconds
Started Aug 25 06:20:32 AM UTC 24
Finished Aug 25 06:20:38 AM UTC 24
Peak memory 216172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892332
115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar
ks_acq.1892332115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.2108403459
Short name T1305
Test name
Test status
Simulation time 139254122 ps
CPU time 1.74 seconds
Started Aug 25 06:20:32 AM UTC 24
Finished Aug 25 06:20:34 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108403
459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermark
s_tx.2108403459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.607229661
Short name T1302
Test name
Test status
Simulation time 1491291747 ps
CPU time 2.85 seconds
Started Aug 25 06:20:29 AM UTC 24
Finished Aug 25 06:20:33 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6072296
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.607229661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.675915720
Short name T1297
Test name
Test status
Simulation time 5219106664 ps
CPU time 12.83 seconds
Started Aug 25 06:20:14 AM UTC 24
Finished Aug 25 06:20:28 AM UTC 24
Peak memory 231040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675915
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.675915720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.1294873225
Short name T1325
Test name
Test status
Simulation time 14108940192 ps
CPU time 47.53 seconds
Started Aug 25 06:20:16 AM UTC 24
Finished Aug 25 06:21:05 AM UTC 24
Peak memory 938392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1294873225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres
s_wr.1294873225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3838322791
Short name T1313
Test name
Test status
Simulation time 517299787 ps
CPU time 4.62 seconds
Started Aug 25 06:20:34 AM UTC 24
Finished Aug 25 06:20:40 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838322
791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.3838322791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.977566164
Short name T48
Test name
Test status
Simulation time 475397917 ps
CPU time 5 seconds
Started Aug 25 06:20:34 AM UTC 24
Finished Aug 25 06:20:40 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9775661
64 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.977566164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_perf.4050646384
Short name T1301
Test name
Test status
Simulation time 1925628119 ps
CPU time 5.15 seconds
Started Aug 25 06:20:25 AM UTC 24
Finished Aug 25 06:20:32 AM UTC 24
Peak memory 228904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050646
384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.4050646384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.3649357722
Short name T1309
Test name
Test status
Simulation time 531788680 ps
CPU time 3.76 seconds
Started Aug 25 06:20:33 AM UTC 24
Finished Aug 25 06:20:38 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649357
722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.3649357722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.3681787079
Short name T1299
Test name
Test status
Simulation time 4287562770 ps
CPU time 18.42 seconds
Started Aug 25 06:20:12 AM UTC 24
Finished Aug 25 06:20:31 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681787079 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.3681787079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.1685447442
Short name T1452
Test name
Test status
Simulation time 30023144659 ps
CPU time 192.59 seconds
Started Aug 25 06:20:25 AM UTC 24
Finished Aug 25 06:23:41 AM UTC 24
Peak memory 1675484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168544
7442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.1685447442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.3058907483
Short name T1315
Test name
Test status
Simulation time 1206897480 ps
CPU time 26.73 seconds
Started Aug 25 06:20:13 AM UTC 24
Finished Aug 25 06:20:41 AM UTC 24
Peak memory 250172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058907483 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.3058907483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.2448220822
Short name T1308
Test name
Test status
Simulation time 45333716389 ps
CPU time 24.74 seconds
Started Aug 25 06:20:12 AM UTC 24
Finished Aug 25 06:20:38 AM UTC 24
Peak memory 477680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448220822 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.2448220822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3514935195
Short name T1300
Test name
Test status
Simulation time 1412409960 ps
CPU time 10.23 seconds
Started Aug 25 06:20:20 AM UTC 24
Finished Aug 25 06:20:31 AM UTC 24
Peak memory 233828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514935
195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3514935195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.2058118017
Short name T1312
Test name
Test status
Simulation time 198234914 ps
CPU time 5.58 seconds
Started Aug 25 06:20:33 AM UTC 24
Finished Aug 25 06:20:40 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058118
017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2058118017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_alert_test.2840465800
Short name T1337
Test name
Test status
Simulation time 32935931 ps
CPU time 0.91 seconds
Started Aug 25 06:21:16 AM UTC 24
Finished Aug 25 06:21:18 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840465800 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2840465800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.2435319875
Short name T1320
Test name
Test status
Simulation time 836551436 ps
CPU time 4.72 seconds
Started Aug 25 06:20:42 AM UTC 24
Finished Aug 25 06:20:48 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435319875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2435319875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3192323854
Short name T1317
Test name
Test status
Simulation time 132576007 ps
CPU time 3.84 seconds
Started Aug 25 06:20:40 AM UTC 24
Finished Aug 25 06:20:45 AM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192323854 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.3192323854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.364430963
Short name T1430
Test name
Test status
Simulation time 12191257279 ps
CPU time 146.9 seconds
Started Aug 25 06:20:41 AM UTC 24
Finished Aug 25 06:23:11 AM UTC 24
Peak memory 909780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364430963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.364430963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.2424111815
Short name T1427
Test name
Test status
Simulation time 7244694323 ps
CPU time 145.52 seconds
Started Aug 25 06:20:39 AM UTC 24
Finished Aug 25 06:23:07 AM UTC 24
Peak memory 635084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424111815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2424111815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.3306966775
Short name T1316
Test name
Test status
Simulation time 81143136 ps
CPU time 1.21 seconds
Started Aug 25 06:20:40 AM UTC 24
Finished Aug 25 06:20:42 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306966775 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.3306966775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.1648830247
Short name T1319
Test name
Test status
Simulation time 259145608 ps
CPU time 4.46 seconds
Started Aug 25 06:20:41 AM UTC 24
Finished Aug 25 06:20:46 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648830247 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.1648830247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.1079898637
Short name T1473
Test name
Test status
Simulation time 2959814386 ps
CPU time 197.98 seconds
Started Aug 25 06:20:39 AM UTC 24
Finished Aug 25 06:24:00 AM UTC 24
Peak memory 942336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079898637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1079898637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.2586885580
Short name T1357
Test name
Test status
Simulation time 2777000225 ps
CPU time 37.33 seconds
Started Aug 25 06:21:07 AM UTC 24
Finished Aug 25 06:21:46 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586885580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2586885580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_override.2230014885
Short name T1314
Test name
Test status
Simulation time 25930131 ps
CPU time 1.1 seconds
Started Aug 25 06:20:38 AM UTC 24
Finished Aug 25 06:20:41 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230014885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2230014885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_perf.1042863521
Short name T1750
Test name
Test status
Simulation time 50012316630 ps
CPU time 2078.7 seconds
Started Aug 25 06:20:41 AM UTC 24
Finished Aug 25 06:55:45 AM UTC 24
Peak memory 311776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042863521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1042863521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.785544435
Short name T1321
Test name
Test status
Simulation time 156739315 ps
CPU time 4.83 seconds
Started Aug 25 06:20:42 AM UTC 24
Finished Aug 25 06:20:48 AM UTC 24
Peak memory 241544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785544435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.785544435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.1416222547
Short name T1351
Test name
Test status
Simulation time 2115039135 ps
CPU time 57.32 seconds
Started Aug 25 06:20:38 AM UTC 24
Finished Aug 25 06:21:38 AM UTC 24
Peak memory 522336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416222547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1416222547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.714005636
Short name T1322
Test name
Test status
Simulation time 1564731657 ps
CPU time 8.01 seconds
Started Aug 25 06:20:42 AM UTC 24
Finished Aug 25 06:20:51 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714005636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.714005636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.51103867
Short name T1331
Test name
Test status
Simulation time 1545535575 ps
CPU time 6.63 seconds
Started Aug 25 06:21:05 AM UTC 24
Finished Aug 25 06:21:13 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=51103867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.51103867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.3827132278
Short name T1326
Test name
Test status
Simulation time 737123153 ps
CPU time 2.13 seconds
Started Aug 25 06:21:02 AM UTC 24
Finished Aug 25 06:21:05 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827132
278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.3827132278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1289353356
Short name T1328
Test name
Test status
Simulation time 140958369 ps
CPU time 1.61 seconds
Started Aug 25 06:21:03 AM UTC 24
Finished Aug 25 06:21:06 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289353
356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.1289353356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.4134648948
Short name T1332
Test name
Test status
Simulation time 2320752944 ps
CPU time 5.38 seconds
Started Aug 25 06:21:07 AM UTC 24
Finished Aug 25 06:21:13 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134648
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar
ks_acq.4134648948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1343718651
Short name T1330
Test name
Test status
Simulation time 551050679 ps
CPU time 2.63 seconds
Started Aug 25 06:21:08 AM UTC 24
Finished Aug 25 06:21:12 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343718
651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.1343718651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.2053270872
Short name T1323
Test name
Test status
Simulation time 8500352167 ps
CPU time 11.22 seconds
Started Aug 25 06:20:49 AM UTC 24
Finished Aug 25 06:21:01 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205327
0872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.2053270872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.3452059029
Short name T1397
Test name
Test status
Simulation time 12065122130 ps
CPU time 97 seconds
Started Aug 25 06:20:49 AM UTC 24
Finished Aug 25 06:22:28 AM UTC 24
Peak memory 1409212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3452059029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stres
s_wr.3452059029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.259638234
Short name T1340
Test name
Test status
Simulation time 557928545 ps
CPU time 4.59 seconds
Started Aug 25 06:21:14 AM UTC 24
Finished Aug 25 06:21:20 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596382
34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.259638234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3776636436
Short name T1339
Test name
Test status
Simulation time 484829221 ps
CPU time 4.19 seconds
Started Aug 25 06:21:14 AM UTC 24
Finished Aug 25 06:21:20 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776636
436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_ad
dr.3776636436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_nack_txstretch.1632603447
Short name T1338
Test name
Test status
Simulation time 485712749 ps
CPU time 2.29 seconds
Started Aug 25 06:21:16 AM UTC 24
Finished Aug 25 06:21:20 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632603
447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_txstretch.1632603447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_perf.3005934882
Short name T1333
Test name
Test status
Simulation time 7148975301 ps
CPU time 10.41 seconds
Started Aug 25 06:21:03 AM UTC 24
Finished Aug 25 06:21:15 AM UTC 24
Peak memory 233940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005934
882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.3005934882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.782368626
Short name T1336
Test name
Test status
Simulation time 711607978 ps
CPU time 3 seconds
Started Aug 25 06:21:13 AM UTC 24
Finished Aug 25 06:21:17 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7823686
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.782368626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.3111234059
Short name T1329
Test name
Test status
Simulation time 1223477295 ps
CPU time 19.89 seconds
Started Aug 25 06:20:45 AM UTC 24
Finished Aug 25 06:21:07 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111234059 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.3111234059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.2044751661
Short name T1516
Test name
Test status
Simulation time 15977136911 ps
CPU time 233.92 seconds
Started Aug 25 06:21:05 AM UTC 24
Finished Aug 25 06:25:03 AM UTC 24
Peak memory 2259416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204475
1661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.2044751661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.2281191991
Short name T1380
Test name
Test status
Simulation time 5064468071 ps
CPU time 69.19 seconds
Started Aug 25 06:20:47 AM UTC 24
Finished Aug 25 06:21:59 AM UTC 24
Peak memory 228932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281191991 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.2281191991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.3082934171
Short name T1373
Test name
Test status
Simulation time 37524237525 ps
CPU time 68.51 seconds
Started Aug 25 06:20:46 AM UTC 24
Finished Aug 25 06:21:57 AM UTC 24
Peak memory 954772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082934171 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.3082934171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.359999443
Short name T1324
Test name
Test status
Simulation time 1254753824 ps
CPU time 10.75 seconds
Started Aug 25 06:20:53 AM UTC 24
Finished Aug 25 06:21:05 AM UTC 24
Peak memory 233276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599994
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.359999443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.2543077927
Short name T1293
Test name
Test status
Simulation time 292577058 ps
CPU time 7.63 seconds
Started Aug 25 06:21:12 AM UTC 24
Finished Aug 25 06:21:21 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543077
927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.2543077927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_alert_test.3736425963
Short name T1375
Test name
Test status
Simulation time 53233667 ps
CPU time 0.97 seconds
Started Aug 25 06:21:55 AM UTC 24
Finished Aug 25 06:21:57 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736425963 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3736425963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.3800960768
Short name T1348
Test name
Test status
Simulation time 241900136 ps
CPU time 2.6 seconds
Started Aug 25 06:21:28 AM UTC 24
Finished Aug 25 06:21:32 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800960768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3800960768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.2363028767
Short name T1350
Test name
Test status
Simulation time 1934143062 ps
CPU time 12.63 seconds
Started Aug 25 06:21:21 AM UTC 24
Finished Aug 25 06:21:34 AM UTC 24
Peak memory 325660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363028767 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.2363028767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.2194684595
Short name T1420
Test name
Test status
Simulation time 15741217565 ps
CPU time 80.49 seconds
Started Aug 25 06:21:22 AM UTC 24
Finished Aug 25 06:22:44 AM UTC 24
Peak memory 639396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194684595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2194684595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.2470080770
Short name T1399
Test name
Test status
Simulation time 6932159391 ps
CPU time 66.05 seconds
Started Aug 25 06:21:21 AM UTC 24
Finished Aug 25 06:22:29 AM UTC 24
Peak memory 622872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470080770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2470080770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.1411007022
Short name T1343
Test name
Test status
Simulation time 572830777 ps
CPU time 1.81 seconds
Started Aug 25 06:21:21 AM UTC 24
Finished Aug 25 06:21:23 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411007022 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.1411007022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.3750787681
Short name T1347
Test name
Test status
Simulation time 449324835 ps
CPU time 7.24 seconds
Started Aug 25 06:21:22 AM UTC 24
Finished Aug 25 06:21:30 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750787681 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.3750787681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.2646333300
Short name T1623
Test name
Test status
Simulation time 18349432491 ps
CPU time 331.2 seconds
Started Aug 25 06:21:19 AM UTC 24
Finished Aug 25 06:26:56 AM UTC 24
Peak memory 1298840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646333300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2646333300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.1400971704
Short name T273
Test name
Test status
Simulation time 3047474160 ps
CPU time 13.39 seconds
Started Aug 25 06:21:48 AM UTC 24
Finished Aug 25 06:22:03 AM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400971704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1400971704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_override.3793880998
Short name T1341
Test name
Test status
Simulation time 37876783 ps
CPU time 1.05 seconds
Started Aug 25 06:21:18 AM UTC 24
Finished Aug 25 06:21:20 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793880998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3793880998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1431991820
Short name T1444
Test name
Test status
Simulation time 2488835591 ps
CPU time 121.28 seconds
Started Aug 25 06:21:24 AM UTC 24
Finished Aug 25 06:23:28 AM UTC 24
Peak memory 241932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431991820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1431991820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.1828499927
Short name T1346
Test name
Test status
Simulation time 204946036 ps
CPU time 4.46 seconds
Started Aug 25 06:21:24 AM UTC 24
Finished Aug 25 06:21:29 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828499927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1828499927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.1912094670
Short name T1360
Test name
Test status
Simulation time 1284175625 ps
CPU time 28 seconds
Started Aug 25 06:21:18 AM UTC 24
Finished Aug 25 06:21:48 AM UTC 24
Peak memory 309212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912094670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1912094670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1754358221
Short name T1353
Test name
Test status
Simulation time 1293198782 ps
CPU time 14.87 seconds
Started Aug 25 06:21:26 AM UTC 24
Finished Aug 25 06:21:42 AM UTC 24
Peak memory 233140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754358221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1754358221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.1031635215
Short name T1371
Test name
Test status
Simulation time 557603325 ps
CPU time 6.28 seconds
Started Aug 25 06:21:48 AM UTC 24
Finished Aug 25 06:21:56 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1031635215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_ad
dr.1031635215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.3497460820
Short name T1358
Test name
Test status
Simulation time 609978127 ps
CPU time 1.96 seconds
Started Aug 25 06:21:44 AM UTC 24
Finished Aug 25 06:21:47 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497460
820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.3497460820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.170293931
Short name T1361
Test name
Test status
Simulation time 403230012 ps
CPU time 1.76 seconds
Started Aug 25 06:21:45 AM UTC 24
Finished Aug 25 06:21:48 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702939
31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.170293931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.4057634969
Short name T1372
Test name
Test status
Simulation time 489531188 ps
CPU time 4.13 seconds
Started Aug 25 06:21:50 AM UTC 24
Finished Aug 25 06:21:56 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057634
969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermar
ks_acq.4057634969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.554853124
Short name T1368
Test name
Test status
Simulation time 557039015 ps
CPU time 1.86 seconds
Started Aug 25 06:21:51 AM UTC 24
Finished Aug 25 06:21:53 AM UTC 24
Peak memory 214508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5548531
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks
_tx.554853124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.4202662729
Short name T1366
Test name
Test status
Simulation time 707612469 ps
CPU time 2.89 seconds
Started Aug 25 06:21:48 AM UTC 24
Finished Aug 25 06:21:52 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202662
729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_hrst.4202662729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.3231780322
Short name T1355
Test name
Test status
Simulation time 1658984719 ps
CPU time 7.59 seconds
Started Aug 25 06:21:36 AM UTC 24
Finished Aug 25 06:21:44 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323178
0322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.3231780322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.925029327
Short name T1382
Test name
Test status
Simulation time 11086110605 ps
CPU time 19.14 seconds
Started Aug 25 06:21:39 AM UTC 24
Finished Aug 25 06:21:59 AM UTC 24
Peak memory 360708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=925029327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stress
_wr.925029327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.562106054
Short name T1381
Test name
Test status
Simulation time 1197093345 ps
CPU time 5.26 seconds
Started Aug 25 06:21:53 AM UTC 24
Finished Aug 25 06:21:59 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5621060
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.562106054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.535119203
Short name T1379
Test name
Test status
Simulation time 5117827245 ps
CPU time 3.71 seconds
Started Aug 25 06:21:54 AM UTC 24
Finished Aug 25 06:21:59 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5351192
03 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.535119203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.96322759
Short name T1374
Test name
Test status
Simulation time 128999603 ps
CPU time 1.98 seconds
Started Aug 25 06:21:54 AM UTC 24
Finished Aug 25 06:21:57 AM UTC 24
Peak memory 232604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9632275
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.96322759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_perf.3068437320
Short name T1376
Test name
Test status
Simulation time 3793096570 ps
CPU time 9.77 seconds
Started Aug 25 06:21:46 AM UTC 24
Finished Aug 25 06:21:57 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068437
320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.3068437320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.3804523934
Short name T1378
Test name
Test status
Simulation time 2789010704 ps
CPU time 4.63 seconds
Started Aug 25 06:21:53 AM UTC 24
Finished Aug 25 06:21:58 AM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804523
934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.3804523934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.1343764698
Short name T1369
Test name
Test status
Simulation time 1299054594 ps
CPU time 22.33 seconds
Started Aug 25 06:21:30 AM UTC 24
Finished Aug 25 06:21:54 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343764698 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.1343764698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.2078004716
Short name T1745
Test name
Test status
Simulation time 69601575575 ps
CPU time 1270.46 seconds
Started Aug 25 06:21:46 AM UTC 24
Finished Aug 25 06:43:12 AM UTC 24
Peak memory 5515420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207800
4716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.2078004716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.4200905369
Short name T1362
Test name
Test status
Simulation time 2984296903 ps
CPU time 15.67 seconds
Started Aug 25 06:21:32 AM UTC 24
Finished Aug 25 06:21:50 AM UTC 24
Peak memory 233392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200905369 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.4200905369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.2426952758
Short name T1461
Test name
Test status
Simulation time 30936445186 ps
CPU time 139.1 seconds
Started Aug 25 06:21:31 AM UTC 24
Finished Aug 25 06:23:53 AM UTC 24
Peak memory 1904852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426952758 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.2426952758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.1972032836
Short name T1364
Test name
Test status
Simulation time 3225212399 ps
CPU time 14.89 seconds
Started Aug 25 06:21:35 AM UTC 24
Finished Aug 25 06:21:51 AM UTC 24
Peak memory 334084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972032836 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.1972032836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.1880036224
Short name T1365
Test name
Test status
Simulation time 1827619519 ps
CPU time 9.8 seconds
Started Aug 25 06:21:41 AM UTC 24
Finished Aug 25 06:21:52 AM UTC 24
Peak memory 233888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880036
224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.1880036224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.631158066
Short name T1370
Test name
Test status
Simulation time 38708207 ps
CPU time 1.5 seconds
Started Aug 25 06:21:52 AM UTC 24
Finished Aug 25 06:21:54 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6311580
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.631158066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_alert_test.4236395360
Short name T361
Test name
Test status
Simulation time 88894427 ps
CPU time 0.98 seconds
Started Aug 25 05:57:07 AM UTC 24
Finished Aug 25 05:57:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236395360 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.4236395360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.1921976018
Short name T22
Test name
Test status
Simulation time 218556971 ps
CPU time 2.24 seconds
Started Aug 25 05:56:35 AM UTC 24
Finished Aug 25 05:56:38 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921976018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1921976018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.148158011
Short name T180
Test name
Test status
Simulation time 632742338 ps
CPU time 21.6 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:56:49 AM UTC 24
Peak memory 272408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148158011 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.148158011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.4218337067
Short name T171
Test name
Test status
Simulation time 11630621558 ps
CPU time 120.27 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:58:29 AM UTC 24
Peak memory 737548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218337067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.4218337067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.2495419963
Short name T105
Test name
Test status
Simulation time 9491284176 ps
CPU time 67.95 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:57:35 AM UTC 24
Peak memory 637136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495419963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2495419963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.3709492211
Short name T259
Test name
Test status
Simulation time 473004645 ps
CPU time 1.77 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:56:28 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709492211 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.3709492211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.178047794
Short name T170
Test name
Test status
Simulation time 1049166870 ps
CPU time 9.61 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:56:37 AM UTC 24
Peak memory 268304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178047794 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.178047794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.3273071523
Short name T97
Test name
Test status
Simulation time 5162865411 ps
CPU time 142.47 seconds
Started Aug 25 05:56:26 AM UTC 24
Finished Aug 25 05:58:51 AM UTC 24
Peak memory 1532244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273071523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3273071523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_mode_toggle.3749494397
Short name T27
Test name
Test status
Simulation time 87268349 ps
CPU time 1.75 seconds
Started Aug 25 05:56:56 AM UTC 24
Finished Aug 25 05:56:59 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749494397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3749494397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_override.2196264712
Short name T348
Test name
Test status
Simulation time 42974989 ps
CPU time 1.01 seconds
Started Aug 25 05:56:23 AM UTC 24
Finished Aug 25 05:56:25 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196264712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2196264712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_perf.1142870722
Short name T350
Test name
Test status
Simulation time 2140155399 ps
CPU time 8.34 seconds
Started Aug 25 05:56:27 AM UTC 24
Finished Aug 25 05:56:36 AM UTC 24
Peak memory 243728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142870722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1142870722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.1327734646
Short name T250
Test name
Test status
Simulation time 251575528 ps
CPU time 5.25 seconds
Started Aug 25 05:56:29 AM UTC 24
Finished Aug 25 05:56:35 AM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327734646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1327734646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.1975965411
Short name T179
Test name
Test status
Simulation time 3731484176 ps
CPU time 20.55 seconds
Started Aug 25 05:56:23 AM UTC 24
Finished Aug 25 05:56:45 AM UTC 24
Peak memory 282836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975965411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1975965411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.3342905935
Short name T353
Test name
Test status
Simulation time 7113744393 ps
CPU time 31.05 seconds
Started Aug 25 05:56:30 AM UTC 24
Finished Aug 25 05:57:02 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342905935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3342905935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2697348149
Short name T207
Test name
Test status
Simulation time 66140901 ps
CPU time 1.46 seconds
Started Aug 25 05:57:07 AM UTC 24
Finished Aug 25 05:57:09 AM UTC 24
Peak memory 246796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697348149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2697348149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.1078895333
Short name T358
Test name
Test status
Simulation time 1600455347 ps
CPU time 14.51 seconds
Started Aug 25 05:56:50 AM UTC 24
Finished Aug 25 05:57:06 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1078895333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1078895333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.2638493515
Short name T163
Test name
Test status
Simulation time 222211592 ps
CPU time 2.19 seconds
Started Aug 25 05:56:46 AM UTC 24
Finished Aug 25 05:56:49 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638493
515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.2638493515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.3833324232
Short name T181
Test name
Test status
Simulation time 352652194 ps
CPU time 1.8 seconds
Started Aug 25 05:56:47 AM UTC 24
Finished Aug 25 05:56:50 AM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833324
232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.3833324232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.2882417539
Short name T356
Test name
Test status
Simulation time 764269235 ps
CPU time 3.25 seconds
Started Aug 25 05:57:00 AM UTC 24
Finished Aug 25 05:57:05 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882417
539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermark
s_acq.2882417539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.1309789185
Short name T354
Test name
Test status
Simulation time 293073600 ps
CPU time 1.5 seconds
Started Aug 25 05:57:00 AM UTC 24
Finished Aug 25 05:57:03 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309789
185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.1309789185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.3477182272
Short name T182
Test name
Test status
Simulation time 14916693096 ps
CPU time 9.72 seconds
Started Aug 25 05:56:40 AM UTC 24
Finished Aug 25 05:56:51 AM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347718
2272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.3477182272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.2262338801
Short name T372
Test name
Test status
Simulation time 17560784590 ps
CPU time 55.35 seconds
Started Aug 25 05:56:40 AM UTC 24
Finished Aug 25 05:57:38 AM UTC 24
Peak memory 971152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2262338801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress
_wr.2262338801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.1508760373
Short name T362
Test name
Test status
Simulation time 2214134131 ps
CPU time 3.67 seconds
Started Aug 25 05:57:05 AM UTC 24
Finished Aug 25 05:57:10 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508760
373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.1508760373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.2572751637
Short name T363
Test name
Test status
Simulation time 496293629 ps
CPU time 4.75 seconds
Started Aug 25 05:57:05 AM UTC 24
Finished Aug 25 05:57:11 AM UTC 24
Peak memory 216408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572751
637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.2572751637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.711770337
Short name T185
Test name
Test status
Simulation time 493663870 ps
CPU time 2.25 seconds
Started Aug 25 05:57:06 AM UTC 24
Finished Aug 25 05:57:09 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7117703
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.711770337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_perf.3371419295
Short name T352
Test name
Test status
Simulation time 2419121086 ps
CPU time 7.16 seconds
Started Aug 25 05:56:50 AM UTC 24
Finished Aug 25 05:56:59 AM UTC 24
Peak memory 231052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371419
295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.3371419295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.42641150
Short name T360
Test name
Test status
Simulation time 1197152010 ps
CPU time 3.63 seconds
Started Aug 25 05:57:04 AM UTC 24
Finished Aug 25 05:57:09 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264115
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.42641150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.3340873853
Short name T368
Test name
Test status
Simulation time 1845904763 ps
CPU time 37.6 seconds
Started Aug 25 05:56:37 AM UTC 24
Finished Aug 25 05:57:16 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340873853 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.3340873853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.2328256540
Short name T575
Test name
Test status
Simulation time 35319407850 ps
CPU time 400.09 seconds
Started Aug 25 05:56:50 AM UTC 24
Finished Aug 25 06:03:36 AM UTC 24
Peak memory 2576796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232825
6540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.2328256540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2231333614
Short name T365
Test name
Test status
Simulation time 4272452071 ps
CPU time 34.5 seconds
Started Aug 25 05:56:37 AM UTC 24
Finished Aug 25 05:57:13 AM UTC 24
Peak memory 245984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231333614 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2231333614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3819232460
Short name T746
Test name
Test status
Simulation time 58534849436 ps
CPU time 641.63 seconds
Started Aug 25 05:56:37 AM UTC 24
Finished Aug 25 06:07:28 AM UTC 24
Peak memory 4976792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819232460 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.3819232460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3629258652
Short name T355
Test name
Test status
Simulation time 3877268965 ps
CPU time 22.92 seconds
Started Aug 25 05:56:39 AM UTC 24
Finished Aug 25 05:57:04 AM UTC 24
Peak memory 420048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629258652 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.3629258652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.3694551651
Short name T183
Test name
Test status
Simulation time 9264684626 ps
CPU time 10.42 seconds
Started Aug 25 05:56:44 AM UTC 24
Finished Aug 25 05:56:55 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694551
651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.3694551651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_alert_test.1391521739
Short name T1412
Test name
Test status
Simulation time 42409030 ps
CPU time 0.92 seconds
Started Aug 25 06:22:37 AM UTC 24
Finished Aug 25 06:22:39 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391521739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1391521739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.1587526392
Short name T1385
Test name
Test status
Simulation time 110262889 ps
CPU time 2.73 seconds
Started Aug 25 06:22:00 AM UTC 24
Finished Aug 25 06:22:04 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587526392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1587526392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.1276117694
Short name T1398
Test name
Test status
Simulation time 468879636 ps
CPU time 28.57 seconds
Started Aug 25 06:21:58 AM UTC 24
Finished Aug 25 06:22:28 AM UTC 24
Peak memory 321500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276117694 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.1276117694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.3446322354
Short name T1507
Test name
Test status
Simulation time 2390445134 ps
CPU time 156.98 seconds
Started Aug 25 06:22:00 AM UTC 24
Finished Aug 25 06:24:40 AM UTC 24
Peak memory 325828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446322354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3446322354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.3498651374
Short name T1536
Test name
Test status
Simulation time 4351100559 ps
CPU time 198.68 seconds
Started Aug 25 06:21:57 AM UTC 24
Finished Aug 25 06:25:20 AM UTC 24
Peak memory 782768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498651374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3498651374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.3419544780
Short name T1384
Test name
Test status
Simulation time 328090713 ps
CPU time 2.12 seconds
Started Aug 25 06:21:57 AM UTC 24
Finished Aug 25 06:22:00 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419544780 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.3419544780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.3770950690
Short name T1388
Test name
Test status
Simulation time 706697746 ps
CPU time 14.78 seconds
Started Aug 25 06:21:58 AM UTC 24
Finished Aug 25 06:22:15 AM UTC 24
Peak memory 250132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770950690 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.3770950690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.1314286176
Short name T1455
Test name
Test status
Simulation time 43529892363 ps
CPU time 108.49 seconds
Started Aug 25 06:21:56 AM UTC 24
Finished Aug 25 06:23:47 AM UTC 24
Peak memory 1073356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314286176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1314286176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.2029410949
Short name T1405
Test name
Test status
Simulation time 941882614 ps
CPU time 5.09 seconds
Started Aug 25 06:22:29 AM UTC 24
Finished Aug 25 06:22:36 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029410949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2029410949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_mode_toggle.3744512634
Short name T1401
Test name
Test status
Simulation time 294705483 ps
CPU time 1.66 seconds
Started Aug 25 06:22:28 AM UTC 24
Finished Aug 25 06:22:31 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744512634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3744512634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_override.772057982
Short name T1377
Test name
Test status
Simulation time 22457002 ps
CPU time 1.05 seconds
Started Aug 25 06:21:56 AM UTC 24
Finished Aug 25 06:21:58 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772057982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.772057982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3504799309
Short name T1459
Test name
Test status
Simulation time 13321472073 ps
CPU time 108.45 seconds
Started Aug 25 06:22:00 AM UTC 24
Finished Aug 25 06:23:51 AM UTC 24
Peak memory 246028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504799309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3504799309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.3183067761
Short name T1742
Test name
Test status
Simulation time 23230969336 ps
CPU time 1095.78 seconds
Started Aug 25 06:22:00 AM UTC 24
Finished Aug 25 06:40:30 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183067761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3183067761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.326353211
Short name T1439
Test name
Test status
Simulation time 5669741641 ps
CPU time 82.63 seconds
Started Aug 25 06:21:55 AM UTC 24
Finished Aug 25 06:23:20 AM UTC 24
Peak memory 325968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326353211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.326353211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.3955431693
Short name T1389
Test name
Test status
Simulation time 696376878 ps
CPU time 14.91 seconds
Started Aug 25 06:22:00 AM UTC 24
Finished Aug 25 06:22:16 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955431693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3955431693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.3671519598
Short name T1407
Test name
Test status
Simulation time 6613724155 ps
CPU time 9.87 seconds
Started Aug 25 06:22:26 AM UTC 24
Finished Aug 25 06:22:37 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3671519598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_ad
dr.3671519598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1833862239
Short name T1391
Test name
Test status
Simulation time 831479273 ps
CPU time 1.26 seconds
Started Aug 25 06:22:20 AM UTC 24
Finished Aug 25 06:22:22 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833862
239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1833862239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.2832682327
Short name T1393
Test name
Test status
Simulation time 144828919 ps
CPU time 1.86 seconds
Started Aug 25 06:22:22 AM UTC 24
Finished Aug 25 06:22:25 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832682
327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.2832682327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.2646199048
Short name T1404
Test name
Test status
Simulation time 510102181 ps
CPU time 4.36 seconds
Started Aug 25 06:22:29 AM UTC 24
Finished Aug 25 06:22:35 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646199
048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermar
ks_acq.2646199048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.3585303032
Short name T1402
Test name
Test status
Simulation time 198475470 ps
CPU time 1.29 seconds
Started Aug 25 06:22:29 AM UTC 24
Finished Aug 25 06:22:32 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585303
032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_tx.3585303032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.2550125765
Short name T1390
Test name
Test status
Simulation time 5103114571 ps
CPU time 11.99 seconds
Started Aug 25 06:22:07 AM UTC 24
Finished Aug 25 06:22:20 AM UTC 24
Peak memory 233636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255012
5765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.2550125765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.1026985133
Short name T1447
Test name
Test status
Simulation time 11242752011 ps
CPU time 73.87 seconds
Started Aug 25 06:22:12 AM UTC 24
Finished Aug 25 06:23:28 AM UTC 24
Peak memory 1439896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1026985133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stres
s_wr.1026985133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.3131257420
Short name T1411
Test name
Test status
Simulation time 578862595 ps
CPU time 4.92 seconds
Started Aug 25 06:22:33 AM UTC 24
Finished Aug 25 06:22:39 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131257
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.3131257420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.4086626745
Short name T1417
Test name
Test status
Simulation time 879915622 ps
CPU time 4.29 seconds
Started Aug 25 06:22:36 AM UTC 24
Finished Aug 25 06:22:41 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086626
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.4086626745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_perf.2174263632
Short name T1403
Test name
Test status
Simulation time 4398160303 ps
CPU time 10.86 seconds
Started Aug 25 06:22:23 AM UTC 24
Finished Aug 25 06:22:35 AM UTC 24
Peak memory 237724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174263
632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.2174263632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.4022778681
Short name T1406
Test name
Test status
Simulation time 490019491 ps
CPU time 4.02 seconds
Started Aug 25 06:22:31 AM UTC 24
Finished Aug 25 06:22:37 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022778
681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.4022778681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.3862727007
Short name T1410
Test name
Test status
Simulation time 10990049408 ps
CPU time 35.72 seconds
Started Aug 25 06:22:01 AM UTC 24
Finished Aug 25 06:22:38 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862727007 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.3862727007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.3322842579
Short name T1545
Test name
Test status
Simulation time 28354925115 ps
CPU time 174.62 seconds
Started Aug 25 06:22:26 AM UTC 24
Finished Aug 25 06:25:24 AM UTC 24
Peak memory 1423512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332284
2579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.3322842579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.1491133989
Short name T1400
Test name
Test status
Simulation time 435561508 ps
CPU time 24.96 seconds
Started Aug 25 06:22:04 AM UTC 24
Finished Aug 25 06:22:30 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491133989 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.1491133989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.3641736522
Short name T1413
Test name
Test status
Simulation time 15962067161 ps
CPU time 36.96 seconds
Started Aug 25 06:22:01 AM UTC 24
Finished Aug 25 06:22:39 AM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641736522 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.3641736522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.2421721751
Short name T1386
Test name
Test status
Simulation time 309930183 ps
CPU time 1.68 seconds
Started Aug 25 06:22:04 AM UTC 24
Finished Aug 25 06:22:07 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421721751 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.2421721751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.3656373947
Short name T1395
Test name
Test status
Simulation time 4672910466 ps
CPU time 10.59 seconds
Started Aug 25 06:22:15 AM UTC 24
Finished Aug 25 06:22:27 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656373
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.3656373947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3803605690
Short name T1416
Test name
Test status
Simulation time 405254962 ps
CPU time 8.24 seconds
Started Aug 25 06:22:31 AM UTC 24
Finished Aug 25 06:22:41 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803605
690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3803605690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_alert_test.366373165
Short name T1437
Test name
Test status
Simulation time 28298387 ps
CPU time 0.89 seconds
Started Aug 25 06:23:17 AM UTC 24
Finished Aug 25 06:23:18 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366373165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.366373165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.1219042603
Short name T1414
Test name
Test status
Simulation time 60865541 ps
CPU time 1.91 seconds
Started Aug 25 06:22:42 AM UTC 24
Finished Aug 25 06:22:44 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219042603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1219042603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.1993016518
Short name T1421
Test name
Test status
Simulation time 468852718 ps
CPU time 14.02 seconds
Started Aug 25 06:22:39 AM UTC 24
Finished Aug 25 06:22:54 AM UTC 24
Peak memory 323876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993016518 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.1993016518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.561757647
Short name T1515
Test name
Test status
Simulation time 3822793556 ps
CPU time 134.86 seconds
Started Aug 25 06:22:40 AM UTC 24
Finished Aug 25 06:24:58 AM UTC 24
Peak memory 784844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561757647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.561757647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.1420543768
Short name T1490
Test name
Test status
Simulation time 12600236091 ps
CPU time 102.08 seconds
Started Aug 25 06:22:39 AM UTC 24
Finished Aug 25 06:24:24 AM UTC 24
Peak memory 819408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420543768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1420543768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.2312040259
Short name T1418
Test name
Test status
Simulation time 180036843 ps
CPU time 1.24 seconds
Started Aug 25 06:22:39 AM UTC 24
Finished Aug 25 06:22:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312040259 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.2312040259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.2275275230
Short name T1356
Test name
Test status
Simulation time 608310606 ps
CPU time 9.64 seconds
Started Aug 25 06:22:39 AM UTC 24
Finished Aug 25 06:22:50 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275275230 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.2275275230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.539432399
Short name T1513
Test name
Test status
Simulation time 4640028507 ps
CPU time 130.9 seconds
Started Aug 25 06:22:38 AM UTC 24
Finished Aug 25 06:24:52 AM UTC 24
Peak memory 1345780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539432399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.539432399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.525507189
Short name T1433
Test name
Test status
Simulation time 1700504168 ps
CPU time 6.37 seconds
Started Aug 25 06:23:08 AM UTC 24
Finished Aug 25 06:23:15 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525507189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.525507189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_override.1726681207
Short name T1415
Test name
Test status
Simulation time 17120770 ps
CPU time 1.08 seconds
Started Aug 25 06:22:38 AM UTC 24
Finished Aug 25 06:22:40 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726681207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1726681207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_perf.441602701
Short name T1456
Test name
Test status
Simulation time 5259976357 ps
CPU time 65.34 seconds
Started Aug 25 06:22:40 AM UTC 24
Finished Aug 25 06:23:48 AM UTC 24
Peak memory 237380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441602701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.441602701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.870924245
Short name T1419
Test name
Test status
Simulation time 140429331 ps
CPU time 2.27 seconds
Started Aug 25 06:22:40 AM UTC 24
Finished Aug 25 06:22:44 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870924245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.870924245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.1785644487
Short name T1449
Test name
Test status
Simulation time 3887318517 ps
CPU time 52.99 seconds
Started Aug 25 06:22:38 AM UTC 24
Finished Aug 25 06:23:33 AM UTC 24
Peak memory 397784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785644487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1785644487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.2940654067
Short name T1422
Test name
Test status
Simulation time 545629734 ps
CPU time 13.38 seconds
Started Aug 25 06:22:42 AM UTC 24
Finished Aug 25 06:22:56 AM UTC 24
Peak memory 233228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940654067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2940654067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.2887733297
Short name T1429
Test name
Test status
Simulation time 1021335593 ps
CPU time 6.46 seconds
Started Aug 25 06:23:03 AM UTC 24
Finished Aug 25 06:23:10 AM UTC 24
Peak memory 230848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2887733297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad
dr.2887733297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.3551340898
Short name T1424
Test name
Test status
Simulation time 355181276 ps
CPU time 2.18 seconds
Started Aug 25 06:22:58 AM UTC 24
Finished Aug 25 06:23:02 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551340
898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.3551340898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.3361861233
Short name T320
Test name
Test status
Simulation time 2553125474 ps
CPU time 2.83 seconds
Started Aug 25 06:23:00 AM UTC 24
Finished Aug 25 06:23:04 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361861
233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.3361861233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.18590348
Short name T1434
Test name
Test status
Simulation time 1780341111 ps
CPU time 3.68 seconds
Started Aug 25 06:23:11 AM UTC 24
Finished Aug 25 06:23:16 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859034
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermarks
_acq.18590348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.915404436
Short name T1432
Test name
Test status
Simulation time 1472892419 ps
CPU time 2.79 seconds
Started Aug 25 06:23:11 AM UTC 24
Finished Aug 25 06:23:15 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9154044
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermarks
_tx.915404436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.3581572699
Short name T1423
Test name
Test status
Simulation time 1436785400 ps
CPU time 7.58 seconds
Started Aug 25 06:22:51 AM UTC 24
Finished Aug 25 06:23:00 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358157
2699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.3581572699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.2114140918
Short name T1620
Test name
Test status
Simulation time 16412331026 ps
CPU time 238.05 seconds
Started Aug 25 06:22:51 AM UTC 24
Finished Aug 25 06:26:53 AM UTC 24
Peak memory 2595036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2114140918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stres
s_wr.2114140918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.1432280833
Short name T1438
Test name
Test status
Simulation time 459730558 ps
CPU time 3.98 seconds
Started Aug 25 06:23:14 AM UTC 24
Finished Aug 25 06:23:19 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432280
833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.1432280833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.630692455
Short name T1442
Test name
Test status
Simulation time 2085358181 ps
CPU time 5.4 seconds
Started Aug 25 06:23:16 AM UTC 24
Finished Aug 25 06:23:23 AM UTC 24
Peak memory 216848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6306924
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.630692455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.1502107418
Short name T1440
Test name
Test status
Simulation time 140682856 ps
CPU time 2.48 seconds
Started Aug 25 06:23:16 AM UTC 24
Finished Aug 25 06:23:20 AM UTC 24
Peak memory 233348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502107
418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.1502107418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_perf.297931981
Short name T1431
Test name
Test status
Simulation time 923747428 ps
CPU time 10.35 seconds
Started Aug 25 06:23:02 AM UTC 24
Finished Aug 25 06:23:13 AM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979319
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.297931981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.2825039500
Short name T1435
Test name
Test status
Simulation time 562997392 ps
CPU time 3.86 seconds
Started Aug 25 06:23:12 AM UTC 24
Finished Aug 25 06:23:17 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825039
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.2825039500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.1315550665
Short name T1426
Test name
Test status
Simulation time 2158767513 ps
CPU time 19.71 seconds
Started Aug 25 06:22:45 AM UTC 24
Finished Aug 25 06:23:06 AM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315550665 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.1315550665
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2063493881
Short name T1555
Test name
Test status
Simulation time 37806006855 ps
CPU time 711.87 seconds
Started Aug 25 06:23:03 AM UTC 24
Finished Aug 25 06:35:03 AM UTC 24
Peak memory 4907164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206349
3881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.2063493881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.3393699900
Short name T1392
Test name
Test status
Simulation time 276014864 ps
CPU time 4.64 seconds
Started Aug 25 06:22:45 AM UTC 24
Finished Aug 25 06:22:51 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393699900 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.3393699900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.667439043
Short name T1487
Test name
Test status
Simulation time 54629734816 ps
CPU time 93.69 seconds
Started Aug 25 06:22:45 AM UTC 24
Finished Aug 25 06:24:21 AM UTC 24
Peak memory 1184152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667439043 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.667439043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.513609366
Short name T1425
Test name
Test status
Simulation time 2482113626 ps
CPU time 10.69 seconds
Started Aug 25 06:22:50 AM UTC 24
Finished Aug 25 06:23:02 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513609366 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.513609366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.212986791
Short name T1428
Test name
Test status
Simulation time 1267012874 ps
CPU time 13.12 seconds
Started Aug 25 06:22:55 AM UTC 24
Finished Aug 25 06:23:10 AM UTC 24
Peak memory 249468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129867
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.212986791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.2146173804
Short name T1436
Test name
Test status
Simulation time 180421857 ps
CPU time 5.02 seconds
Started Aug 25 06:23:12 AM UTC 24
Finished Aug 25 06:23:18 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146173
804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.2146173804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_alert_test.3790039100
Short name T1470
Test name
Test status
Simulation time 36212277 ps
CPU time 0.87 seconds
Started Aug 25 06:23:57 AM UTC 24
Finished Aug 25 06:23:59 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790039100 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3790039100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.2599196390
Short name T1450
Test name
Test status
Simulation time 126788181 ps
CPU time 2.35 seconds
Started Aug 25 06:23:29 AM UTC 24
Finished Aug 25 06:23:33 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599196390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2599196390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.2444519785
Short name T1453
Test name
Test status
Simulation time 5051536581 ps
CPU time 19.22 seconds
Started Aug 25 06:23:21 AM UTC 24
Finished Aug 25 06:23:42 AM UTC 24
Peak memory 286948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444519785 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.2444519785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.4287454541
Short name T1498
Test name
Test status
Simulation time 3653355886 ps
CPU time 68.96 seconds
Started Aug 25 06:23:24 AM UTC 24
Finished Aug 25 06:24:35 AM UTC 24
Peak memory 457160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287454541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.4287454541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.2018766965
Short name T1554
Test name
Test status
Simulation time 1590747280 ps
CPU time 131.26 seconds
Started Aug 25 06:23:21 AM UTC 24
Finished Aug 25 06:25:35 AM UTC 24
Peak memory 581736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018766965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2018766965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.3481072815
Short name T1443
Test name
Test status
Simulation time 304695738 ps
CPU time 1.95 seconds
Started Aug 25 06:23:21 AM UTC 24
Finished Aug 25 06:23:24 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481072815 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.3481072815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.1873785716
Short name T1448
Test name
Test status
Simulation time 130962016 ps
CPU time 5.29 seconds
Started Aug 25 06:23:22 AM UTC 24
Finished Aug 25 06:23:29 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873785716 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.1873785716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1094391635
Short name T1579
Test name
Test status
Simulation time 19655601630 ps
CPU time 158.52 seconds
Started Aug 25 06:23:20 AM UTC 24
Finished Aug 25 06:26:02 AM UTC 24
Peak memory 1421828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094391635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1094391635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.517110233
Short name T1481
Test name
Test status
Simulation time 3253142228 ps
CPU time 15.51 seconds
Started Aug 25 06:23:52 AM UTC 24
Finished Aug 25 06:24:08 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517110233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.517110233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_override.1497743820
Short name T1441
Test name
Test status
Simulation time 18372811 ps
CPU time 1.05 seconds
Started Aug 25 06:23:19 AM UTC 24
Finished Aug 25 06:23:21 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497743820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1497743820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_perf.3682319061
Short name T1446
Test name
Test status
Simulation time 823406041 ps
CPU time 1.96 seconds
Started Aug 25 06:23:25 AM UTC 24
Finished Aug 25 06:23:28 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682319061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3682319061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.3201506222
Short name T1514
Test name
Test status
Simulation time 1548897389 ps
CPU time 88.4 seconds
Started Aug 25 06:23:26 AM UTC 24
Finished Aug 25 06:24:57 AM UTC 24
Peak memory 460872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201506222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3201506222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.1455761095
Short name T1464
Test name
Test status
Simulation time 2448934794 ps
CPU time 35.65 seconds
Started Aug 25 06:23:18 AM UTC 24
Finished Aug 25 06:23:55 AM UTC 24
Peak memory 360652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455761095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1455761095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.1039450418
Short name T1482
Test name
Test status
Simulation time 714492504 ps
CPU time 39.42 seconds
Started Aug 25 06:23:28 AM UTC 24
Finished Aug 25 06:24:09 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039450418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1039450418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.3550814591
Short name T1468
Test name
Test status
Simulation time 4088818009 ps
CPU time 7.77 seconds
Started Aug 25 06:23:48 AM UTC 24
Finished Aug 25 06:23:57 AM UTC 24
Peak memory 226972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3550814591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_ad
dr.3550814591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.3017989134
Short name T1457
Test name
Test status
Simulation time 282627501 ps
CPU time 2.05 seconds
Started Aug 25 06:23:45 AM UTC 24
Finished Aug 25 06:23:48 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017989
134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.3017989134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3819335511
Short name T1458
Test name
Test status
Simulation time 421013968 ps
CPU time 1.9 seconds
Started Aug 25 06:23:46 AM UTC 24
Finished Aug 25 06:23:49 AM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819335
511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.3819335511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.271879910
Short name T1469
Test name
Test status
Simulation time 2443096865 ps
CPU time 5.33 seconds
Started Aug 25 06:23:52 AM UTC 24
Finished Aug 25 06:23:58 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718799
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermark
s_acq.271879910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.899032737
Short name T1466
Test name
Test status
Simulation time 381448633 ps
CPU time 1.14 seconds
Started Aug 25 06:23:54 AM UTC 24
Finished Aug 25 06:23:56 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8990327
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks
_tx.899032737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.2786816996
Short name T1462
Test name
Test status
Simulation time 481090481 ps
CPU time 3.1 seconds
Started Aug 25 06:23:50 AM UTC 24
Finished Aug 25 06:23:54 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786816
996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.2786816996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2701213567
Short name T1454
Test name
Test status
Simulation time 5795756766 ps
CPU time 10.99 seconds
Started Aug 25 06:23:34 AM UTC 24
Finished Aug 25 06:23:46 AM UTC 24
Peak memory 243912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270121
3567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.2701213567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.3205526446
Short name T1460
Test name
Test status
Simulation time 5689100040 ps
CPU time 9.88 seconds
Started Aug 25 06:23:40 AM UTC 24
Finished Aug 25 06:23:51 AM UTC 24
Peak memory 358548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3205526446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stres
s_wr.3205526446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2415997466
Short name T1472
Test name
Test status
Simulation time 1030317884 ps
CPU time 4.11 seconds
Started Aug 25 06:23:55 AM UTC 24
Finished Aug 25 06:24:00 AM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415997
466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.2415997466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.2638051522
Short name T1476
Test name
Test status
Simulation time 3447343406 ps
CPU time 4.48 seconds
Started Aug 25 06:23:56 AM UTC 24
Finished Aug 25 06:24:02 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638051
522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad
dr.2638051522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_perf.1217382960
Short name T1467
Test name
Test status
Simulation time 2622172139 ps
CPU time 8.54 seconds
Started Aug 25 06:23:47 AM UTC 24
Finished Aug 25 06:23:57 AM UTC 24
Peak memory 233032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217382
960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.1217382960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.3952984388
Short name T1475
Test name
Test status
Simulation time 3085466961 ps
CPU time 4.47 seconds
Started Aug 25 06:23:55 AM UTC 24
Finished Aug 25 06:24:01 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952984
388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.3952984388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.864576298
Short name T1451
Test name
Test status
Simulation time 849458075 ps
CPU time 8.94 seconds
Started Aug 25 06:23:30 AM UTC 24
Finished Aug 25 06:23:40 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864576298 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.864576298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.596780058
Short name T1527
Test name
Test status
Simulation time 17638876252 ps
CPU time 83.73 seconds
Started Aug 25 06:23:48 AM UTC 24
Finished Aug 25 06:25:14 AM UTC 24
Peak memory 301284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596780
058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.596780058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.817210527
Short name T1463
Test name
Test status
Simulation time 4495689562 ps
CPU time 23.65 seconds
Started Aug 25 06:23:30 AM UTC 24
Finished Aug 25 06:23:55 AM UTC 24
Peak memory 235732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817210527 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.817210527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3715288957
Short name T1681
Test name
Test status
Simulation time 39915370821 ps
CPU time 267.08 seconds
Started Aug 25 06:23:30 AM UTC 24
Finished Aug 25 06:28:01 AM UTC 24
Peak memory 2758996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715288957 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.3715288957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.3688081272
Short name T1465
Test name
Test status
Simulation time 2880173059 ps
CPU time 11.99 seconds
Started Aug 25 06:23:42 AM UTC 24
Finished Aug 25 06:23:55 AM UTC 24
Peak memory 243864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688081
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.3688081272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.1378506838
Short name T1478
Test name
Test status
Simulation time 325502505 ps
CPU time 7.05 seconds
Started Aug 25 06:23:55 AM UTC 24
Finished Aug 25 06:24:03 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378506
838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.1378506838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_alert_test.1615344422
Short name T1500
Test name
Test status
Simulation time 17322344 ps
CPU time 1.03 seconds
Started Aug 25 06:24:35 AM UTC 24
Finished Aug 25 06:24:37 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615344422 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1615344422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.1407219956
Short name T1485
Test name
Test status
Simulation time 1057614876 ps
CPU time 13.09 seconds
Started Aug 25 06:24:03 AM UTC 24
Finished Aug 25 06:24:17 AM UTC 24
Peak memory 266516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407219956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1407219956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.1915042767
Short name T1479
Test name
Test status
Simulation time 183695543 ps
CPU time 4.59 seconds
Started Aug 25 06:24:01 AM UTC 24
Finished Aug 25 06:24:06 AM UTC 24
Peak memory 249956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915042767 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.1915042767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.3343660473
Short name T1603
Test name
Test status
Simulation time 16430502970 ps
CPU time 155.36 seconds
Started Aug 25 06:24:01 AM UTC 24
Finished Aug 25 06:26:39 AM UTC 24
Peak memory 635036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343660473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3343660473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.101731292
Short name T1559
Test name
Test status
Simulation time 9542191626 ps
CPU time 99.1 seconds
Started Aug 25 06:24:00 AM UTC 24
Finished Aug 25 06:25:41 AM UTC 24
Peak memory 825792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101731292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.101731292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.325033687
Short name T1477
Test name
Test status
Simulation time 115788779 ps
CPU time 1.83 seconds
Started Aug 25 06:24:00 AM UTC 24
Finished Aug 25 06:24:02 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325033687 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.325033687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.1458040749
Short name T1480
Test name
Test status
Simulation time 773511948 ps
CPU time 6.47 seconds
Started Aug 25 06:24:01 AM UTC 24
Finished Aug 25 06:24:08 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458040749 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.1458040749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3872627005
Short name T1726
Test name
Test status
Simulation time 20011447850 ps
CPU time 357.5 seconds
Started Aug 25 06:23:59 AM UTC 24
Finished Aug 25 06:30:03 AM UTC 24
Peak memory 1413288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872627005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3872627005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.1729986181
Short name T1494
Test name
Test status
Simulation time 264290821 ps
CPU time 4.23 seconds
Started Aug 25 06:24:27 AM UTC 24
Finished Aug 25 06:24:32 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729986181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1729986181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_override.1745787971
Short name T1474
Test name
Test status
Simulation time 50278057 ps
CPU time 0.92 seconds
Started Aug 25 06:23:58 AM UTC 24
Finished Aug 25 06:24:00 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745787971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1745787971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_perf.3985809113
Short name T1529
Test name
Test status
Simulation time 2656197196 ps
CPU time 72.26 seconds
Started Aug 25 06:24:01 AM UTC 24
Finished Aug 25 06:25:15 AM UTC 24
Peak memory 827908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985809113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3985809113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.2115419735
Short name T1484
Test name
Test status
Simulation time 698293652 ps
CPU time 10.02 seconds
Started Aug 25 06:24:02 AM UTC 24
Finished Aug 25 06:24:13 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115419735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.2115419735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.1911455902
Short name T1531
Test name
Test status
Simulation time 11449274673 ps
CPU time 75.79 seconds
Started Aug 25 06:23:58 AM UTC 24
Finished Aug 25 06:25:16 AM UTC 24
Peak memory 346568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911455902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1911455902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.2559130157
Short name T1511
Test name
Test status
Simulation time 729721458 ps
CPU time 43.38 seconds
Started Aug 25 06:24:03 AM UTC 24
Finished Aug 25 06:24:48 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559130157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2559130157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3051726917
Short name T1497
Test name
Test status
Simulation time 4579110670 ps
CPU time 8.48 seconds
Started Aug 25 06:24:24 AM UTC 24
Finished Aug 25 06:24:34 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3051726917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_ad
dr.3051726917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.2572416044
Short name T1489
Test name
Test status
Simulation time 157077724 ps
CPU time 1.99 seconds
Started Aug 25 06:24:20 AM UTC 24
Finished Aug 25 06:24:23 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572416
044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.2572416044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.4155375384
Short name T1491
Test name
Test status
Simulation time 400184700 ps
CPU time 1.68 seconds
Started Aug 25 06:24:22 AM UTC 24
Finished Aug 25 06:24:25 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155375
384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.4155375384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.247202212
Short name T1496
Test name
Test status
Simulation time 466427708 ps
CPU time 3.08 seconds
Started Aug 25 06:24:29 AM UTC 24
Finished Aug 25 06:24:33 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472022
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_acq.247202212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.2183528652
Short name T1495
Test name
Test status
Simulation time 425953326 ps
CPU time 1.37 seconds
Started Aug 25 06:24:30 AM UTC 24
Finished Aug 25 06:24:32 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183528
652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.2183528652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.2725332726
Short name T1486
Test name
Test status
Simulation time 743995967 ps
CPU time 6.91 seconds
Started Aug 25 06:24:11 AM UTC 24
Finished Aug 25 06:24:19 AM UTC 24
Peak memory 232964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272533
2726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.2725332726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.1898805995
Short name T1732
Test name
Test status
Simulation time 24006378160 ps
CPU time 490.4 seconds
Started Aug 25 06:24:14 AM UTC 24
Finished Aug 25 06:32:31 AM UTC 24
Peak memory 5804184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1898805995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stres
s_wr.1898805995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.1794610149
Short name T1504
Test name
Test status
Simulation time 3383408415 ps
CPU time 4.17 seconds
Started Aug 25 06:24:33 AM UTC 24
Finished Aug 25 06:24:38 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794610
149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.1794610149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.401333662
Short name T1505
Test name
Test status
Simulation time 2233881239 ps
CPU time 4.46 seconds
Started Aug 25 06:24:33 AM UTC 24
Finished Aug 25 06:24:39 AM UTC 24
Peak memory 216472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013336
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.401333662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.1446749234
Short name T1502
Test name
Test status
Simulation time 551071945 ps
CPU time 2.45 seconds
Started Aug 25 06:24:34 AM UTC 24
Finished Aug 25 06:24:38 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446749
234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_txstretch.1446749234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_perf.3661875894
Short name T1493
Test name
Test status
Simulation time 626836097 ps
CPU time 6.97 seconds
Started Aug 25 06:24:22 AM UTC 24
Finished Aug 25 06:24:30 AM UTC 24
Peak memory 229056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661875
894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.3661875894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.1139318295
Short name T1501
Test name
Test status
Simulation time 1593463344 ps
CPU time 3.61 seconds
Started Aug 25 06:24:33 AM UTC 24
Finished Aug 25 06:24:38 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139318
295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.1139318295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.2647618872
Short name T1488
Test name
Test status
Simulation time 3388280121 ps
CPU time 14.39 seconds
Started Aug 25 06:24:07 AM UTC 24
Finished Aug 25 06:24:23 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647618872 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.2647618872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.276961096
Short name T1743
Test name
Test status
Simulation time 74214587710 ps
CPU time 968.77 seconds
Started Aug 25 06:24:23 AM UTC 24
Finished Aug 25 06:40:45 AM UTC 24
Peak memory 4454668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276961
096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.276961096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.1826638299
Short name T1503
Test name
Test status
Simulation time 13532422872 ps
CPU time 27.19 seconds
Started Aug 25 06:24:10 AM UTC 24
Finished Aug 25 06:24:38 AM UTC 24
Peak memory 243996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826638299 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.1826638299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2487316536
Short name T1733
Test name
Test status
Simulation time 53965644996 ps
CPU time 521.5 seconds
Started Aug 25 06:24:10 AM UTC 24
Finished Aug 25 06:32:58 AM UTC 24
Peak memory 4301016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487316536 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.2487316536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.2767298064
Short name T1520
Test name
Test status
Simulation time 3141302924 ps
CPU time 56.65 seconds
Started Aug 25 06:24:10 AM UTC 24
Finished Aug 25 06:25:08 AM UTC 24
Peak memory 864532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767298064 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.2767298064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.2503426338
Short name T1492
Test name
Test status
Simulation time 2595800763 ps
CPU time 11.19 seconds
Started Aug 25 06:24:14 AM UTC 24
Finished Aug 25 06:24:26 AM UTC 24
Peak memory 244036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503426
338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.2503426338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.248715832
Short name T1499
Test name
Test status
Simulation time 128794509 ps
CPU time 4.19 seconds
Started Aug 25 06:24:31 AM UTC 24
Finished Aug 25 06:24:36 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487158
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.248715832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_alert_test.3402666856
Short name T1540
Test name
Test status
Simulation time 17402700 ps
CPU time 0.94 seconds
Started Aug 25 06:25:20 AM UTC 24
Finished Aug 25 06:25:23 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402666856 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3402666856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.3661844621
Short name T1512
Test name
Test status
Simulation time 1442270035 ps
CPU time 4.96 seconds
Started Aug 25 06:24:43 AM UTC 24
Finished Aug 25 06:24:49 AM UTC 24
Peak memory 228956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661844621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3661844621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.2477774653
Short name T1510
Test name
Test status
Simulation time 1163238738 ps
CPU time 6.4 seconds
Started Aug 25 06:24:39 AM UTC 24
Finished Aug 25 06:24:46 AM UTC 24
Peak memory 274460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477774653 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.2477774653
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.4229866297
Short name T1693
Test name
Test status
Simulation time 3474422969 ps
CPU time 232.37 seconds
Started Aug 25 06:24:40 AM UTC 24
Finished Aug 25 06:28:36 AM UTC 24
Peak memory 735616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229866297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.4229866297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2998324308
Short name T1584
Test name
Test status
Simulation time 4646817829 ps
CPU time 92.4 seconds
Started Aug 25 06:24:39 AM UTC 24
Finished Aug 25 06:26:13 AM UTC 24
Peak memory 798936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998324308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2998324308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.534646784
Short name T1508
Test name
Test status
Simulation time 349803947 ps
CPU time 1.49 seconds
Started Aug 25 06:24:39 AM UTC 24
Finished Aug 25 06:24:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534646784 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.534646784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.3417758701
Short name T1509
Test name
Test status
Simulation time 530452166 ps
CPU time 5.02 seconds
Started Aug 25 06:24:40 AM UTC 24
Finished Aug 25 06:24:46 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417758701 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.3417758701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2207108967
Short name T1691
Test name
Test status
Simulation time 12386554087 ps
CPU time 229.31 seconds
Started Aug 25 06:24:39 AM UTC 24
Finished Aug 25 06:28:32 AM UTC 24
Peak memory 979204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207108967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2207108967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.1245546971
Short name T1538
Test name
Test status
Simulation time 899087786 ps
CPU time 5.29 seconds
Started Aug 25 06:25:15 AM UTC 24
Finished Aug 25 06:25:21 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245546971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1245546971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_override.890326360
Short name T1506
Test name
Test status
Simulation time 27700682 ps
CPU time 1.04 seconds
Started Aug 25 06:24:37 AM UTC 24
Finished Aug 25 06:24:39 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890326360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.890326360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_perf.3421948172
Short name T1561
Test name
Test status
Simulation time 6820350334 ps
CPU time 60.61 seconds
Started Aug 25 06:24:40 AM UTC 24
Finished Aug 25 06:25:42 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421948172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3421948172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.1855291390
Short name T1598
Test name
Test status
Simulation time 24641728903 ps
CPU time 111.53 seconds
Started Aug 25 06:24:41 AM UTC 24
Finished Aug 25 06:26:35 AM UTC 24
Peak memory 784524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855291390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1855291390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2467895798
Short name T1550
Test name
Test status
Simulation time 6848796340 ps
CPU time 49.99 seconds
Started Aug 25 06:24:36 AM UTC 24
Finished Aug 25 06:25:28 AM UTC 24
Peak memory 491756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467895798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2467895798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.1922028202
Short name T1519
Test name
Test status
Simulation time 3550858051 ps
CPU time 22.47 seconds
Started Aug 25 06:24:42 AM UTC 24
Finished Aug 25 06:25:06 AM UTC 24
Peak memory 243912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922028202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1922028202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.2398684446
Short name T1535
Test name
Test status
Simulation time 3339068759 ps
CPU time 8.74 seconds
Started Aug 25 06:25:09 AM UTC 24
Finished Aug 25 06:25:19 AM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2398684446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad
dr.2398684446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.2944876843
Short name T1523
Test name
Test status
Simulation time 157873705 ps
CPU time 1.37 seconds
Started Aug 25 06:25:06 AM UTC 24
Finished Aug 25 06:25:09 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944876
843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.2944876843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.3412721925
Short name T1524
Test name
Test status
Simulation time 259252054 ps
CPU time 1.57 seconds
Started Aug 25 06:25:07 AM UTC 24
Finished Aug 25 06:25:10 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412721
925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.3412721925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.935832624
Short name T1537
Test name
Test status
Simulation time 2004205654 ps
CPU time 4.51 seconds
Started Aug 25 06:25:15 AM UTC 24
Finished Aug 25 06:25:20 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9358326
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermark
s_acq.935832624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.187395256
Short name T1534
Test name
Test status
Simulation time 570597574 ps
CPU time 2.13 seconds
Started Aug 25 06:25:16 AM UTC 24
Finished Aug 25 06:25:19 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873952
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks
_tx.187395256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_hrst.1720047272
Short name T1528
Test name
Test status
Simulation time 522191850 ps
CPU time 2.89 seconds
Started Aug 25 06:25:10 AM UTC 24
Finished Aug 25 06:25:14 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720047
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_hrst.1720047272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.3424303138
Short name T1518
Test name
Test status
Simulation time 746453983 ps
CPU time 6.77 seconds
Started Aug 25 06:24:58 AM UTC 24
Finished Aug 25 06:25:06 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342430
3138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.3424303138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.1367931955
Short name T1525
Test name
Test status
Simulation time 3246241559 ps
CPU time 12.16 seconds
Started Aug 25 06:24:59 AM UTC 24
Finished Aug 25 06:25:12 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1367931955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stres
s_wr.1367931955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.628481191
Short name T1544
Test name
Test status
Simulation time 2187861722 ps
CPU time 4.94 seconds
Started Aug 25 06:25:17 AM UTC 24
Finished Aug 25 06:25:23 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6284811
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.628481191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.1182360568
Short name T1546
Test name
Test status
Simulation time 1963073623 ps
CPU time 4.46 seconds
Started Aug 25 06:25:18 AM UTC 24
Finished Aug 25 06:25:24 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182360
568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad
dr.1182360568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.2614346691
Short name T1539
Test name
Test status
Simulation time 561614741 ps
CPU time 2.04 seconds
Started Aug 25 06:25:18 AM UTC 24
Finished Aug 25 06:25:21 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614346
691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.2614346691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_perf.1350833631
Short name T1532
Test name
Test status
Simulation time 470937810 ps
CPU time 6.37 seconds
Started Aug 25 06:25:09 AM UTC 24
Finished Aug 25 06:25:17 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350833
631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.1350833631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.2948315768
Short name T1543
Test name
Test status
Simulation time 605396152 ps
CPU time 4.59 seconds
Started Aug 25 06:25:17 AM UTC 24
Finished Aug 25 06:25:23 AM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948315
768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.2948315768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.1295461961
Short name T1530
Test name
Test status
Simulation time 6227238356 ps
CPU time 27.33 seconds
Started Aug 25 06:24:47 AM UTC 24
Finished Aug 25 06:25:16 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295461961 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.1295461961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1963683853
Short name T1592
Test name
Test status
Simulation time 12339725495 ps
CPU time 79.02 seconds
Started Aug 25 06:25:09 AM UTC 24
Finished Aug 25 06:26:30 AM UTC 24
Peak memory 282800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196368
3853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.1963683853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.2913536049
Short name T1586
Test name
Test status
Simulation time 6386406405 ps
CPU time 87.75 seconds
Started Aug 25 06:24:51 AM UTC 24
Finished Aug 25 06:26:21 AM UTC 24
Peak memory 229232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913536049 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.2913536049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2125171681
Short name T1746
Test name
Test status
Simulation time 50768946546 ps
CPU time 1103.96 seconds
Started Aug 25 06:24:48 AM UTC 24
Finished Aug 25 06:43:26 AM UTC 24
Peak memory 7964816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125171681 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.2125171681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.856371443
Short name T1557
Test name
Test status
Simulation time 5453992775 ps
CPU time 44.41 seconds
Started Aug 25 06:24:53 AM UTC 24
Finished Aug 25 06:25:39 AM UTC 24
Peak memory 532748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856371443 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.856371443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.3239787917
Short name T1526
Test name
Test status
Simulation time 5722535370 ps
CPU time 8.59 seconds
Started Aug 25 06:25:04 AM UTC 24
Finished Aug 25 06:25:14 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239787
917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.3239787917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.62630164
Short name T1542
Test name
Test status
Simulation time 145173635 ps
CPU time 5.41 seconds
Started Aug 25 06:25:16 AM UTC 24
Finished Aug 25 06:25:23 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6263016
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.62630164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_alert_test.254016750
Short name T1574
Test name
Test status
Simulation time 17220261 ps
CPU time 0.92 seconds
Started Aug 25 06:25:52 AM UTC 24
Finished Aug 25 06:25:54 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254016750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.254016750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.399892188
Short name T1558
Test name
Test status
Simulation time 258129845 ps
CPU time 16.08 seconds
Started Aug 25 06:25:22 AM UTC 24
Finished Aug 25 06:25:39 AM UTC 24
Peak memory 270536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399892188 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.399892188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.719414978
Short name T1633
Test name
Test status
Simulation time 3183111105 ps
CPU time 100.56 seconds
Started Aug 25 06:25:24 AM UTC 24
Finished Aug 25 06:27:07 AM UTC 24
Peak memory 432340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719414978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.719414978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.946147196
Short name T1625
Test name
Test status
Simulation time 9872329465 ps
CPU time 98.74 seconds
Started Aug 25 06:25:22 AM UTC 24
Finished Aug 25 06:27:03 AM UTC 24
Peak memory 848092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946147196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.946147196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.2460024141
Short name T1547
Test name
Test status
Simulation time 525755484 ps
CPU time 1.54 seconds
Started Aug 25 06:25:22 AM UTC 24
Finished Aug 25 06:25:24 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460024141 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.2460024141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.2675383649
Short name T1552
Test name
Test status
Simulation time 546898068 ps
CPU time 9.61 seconds
Started Aug 25 06:25:23 AM UTC 24
Finished Aug 25 06:25:33 AM UTC 24
Peak memory 241760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675383649 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.2675383649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1935059899
Short name T1683
Test name
Test status
Simulation time 5054431769 ps
CPU time 165.41 seconds
Started Aug 25 06:25:20 AM UTC 24
Finished Aug 25 06:28:09 AM UTC 24
Peak memory 829692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935059899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1935059899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2359947938
Short name T1578
Test name
Test status
Simulation time 3431175853 ps
CPU time 17.14 seconds
Started Aug 25 06:25:43 AM UTC 24
Finished Aug 25 06:26:02 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359947938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2359947938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_override.700466195
Short name T1541
Test name
Test status
Simulation time 41058360 ps
CPU time 0.95 seconds
Started Aug 25 06:25:20 AM UTC 24
Finished Aug 25 06:25:23 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700466195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.700466195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2730561204
Short name T1609
Test name
Test status
Simulation time 18779396956 ps
CPU time 77.17 seconds
Started Aug 25 06:25:24 AM UTC 24
Finished Aug 25 06:26:43 AM UTC 24
Peak memory 709068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730561204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2730561204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.3963708725
Short name T1551
Test name
Test status
Simulation time 153803685 ps
CPU time 7.52 seconds
Started Aug 25 06:25:24 AM UTC 24
Finished Aug 25 06:25:33 AM UTC 24
Peak memory 237040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963708725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.3963708725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.3207636618
Short name T1580
Test name
Test status
Simulation time 6178023409 ps
CPU time 43.3 seconds
Started Aug 25 06:25:20 AM UTC 24
Finished Aug 25 06:26:06 AM UTC 24
Peak memory 430496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207636618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3207636618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1987509843
Short name T1564
Test name
Test status
Simulation time 399492323 ps
CPU time 22.74 seconds
Started Aug 25 06:25:24 AM UTC 24
Finished Aug 25 06:25:48 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987509843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1987509843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3206779790
Short name T1566
Test name
Test status
Simulation time 3320928348 ps
CPU time 8 seconds
Started Aug 25 06:25:40 AM UTC 24
Finished Aug 25 06:25:49 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3206779790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad
dr.3206779790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.4184334812
Short name T1556
Test name
Test status
Simulation time 499650837 ps
CPU time 1.77 seconds
Started Aug 25 06:25:36 AM UTC 24
Finished Aug 25 06:25:39 AM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184334
812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.4184334812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.3379793464
Short name T1560
Test name
Test status
Simulation time 197796258 ps
CPU time 1.37 seconds
Started Aug 25 06:25:39 AM UTC 24
Finished Aug 25 06:25:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379793
464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.3379793464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.3182342434
Short name T1572
Test name
Test status
Simulation time 545251222 ps
CPU time 4.02 seconds
Started Aug 25 06:25:47 AM UTC 24
Finished Aug 25 06:25:53 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182342
434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.3182342434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1694761337
Short name T1569
Test name
Test status
Simulation time 157983281 ps
CPU time 2.57 seconds
Started Aug 25 06:25:48 AM UTC 24
Finished Aug 25 06:25:51 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694761
337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermark
s_tx.1694761337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.4210882455
Short name T1563
Test name
Test status
Simulation time 380312607 ps
CPU time 3.42 seconds
Started Aug 25 06:25:42 AM UTC 24
Finished Aug 25 06:25:47 AM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210882
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.4210882455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.3098405698
Short name T1553
Test name
Test status
Simulation time 1760755581 ps
CPU time 5.41 seconds
Started Aug 25 06:25:28 AM UTC 24
Finished Aug 25 06:25:35 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309840
5698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.3098405698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2600054779
Short name T1587
Test name
Test status
Simulation time 19252939442 ps
CPU time 45.73 seconds
Started Aug 25 06:25:34 AM UTC 24
Finished Aug 25 06:26:21 AM UTC 24
Peak memory 794772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2600054779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stres
s_wr.2600054779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2959467322
Short name T1571
Test name
Test status
Simulation time 2546476902 ps
CPU time 5 seconds
Started Aug 25 06:25:51 AM UTC 24
Finished Aug 25 06:25:57 AM UTC 24
Peak memory 227260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959467
322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.2959467322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3590462218
Short name T1565
Test name
Test status
Simulation time 6575986501 ps
CPU time 5.1 seconds
Started Aug 25 06:25:51 AM UTC 24
Finished Aug 25 06:25:57 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590462
218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.3590462218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3181294486
Short name T1575
Test name
Test status
Simulation time 146840981 ps
CPU time 2.23 seconds
Started Aug 25 06:25:52 AM UTC 24
Finished Aug 25 06:25:55 AM UTC 24
Peak memory 233776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181294
486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_txstretch.3181294486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_perf.56057513
Short name T1568
Test name
Test status
Simulation time 3492584612 ps
CPU time 9.24 seconds
Started Aug 25 06:25:40 AM UTC 24
Finished Aug 25 06:25:50 AM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5605751
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.56057513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1295468189
Short name T1573
Test name
Test status
Simulation time 1091175815 ps
CPU time 2.37 seconds
Started Aug 25 06:25:50 AM UTC 24
Finished Aug 25 06:25:53 AM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295468
189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.1295468189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3006569468
Short name T1521
Test name
Test status
Simulation time 2531921557 ps
CPU time 28.02 seconds
Started Aug 25 06:25:25 AM UTC 24
Finished Aug 25 06:25:55 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006569468 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.3006569468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.29624053
Short name T1698
Test name
Test status
Simulation time 63704520644 ps
CPU time 179.07 seconds
Started Aug 25 06:25:40 AM UTC 24
Finished Aug 25 06:28:42 AM UTC 24
Peak memory 1006092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296240
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.29624053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.2439506136
Short name T1570
Test name
Test status
Simulation time 997376313 ps
CPU time 24.39 seconds
Started Aug 25 06:25:25 AM UTC 24
Finished Aug 25 06:25:51 AM UTC 24
Peak memory 233220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439506136 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.2439506136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1824762036
Short name T1533
Test name
Test status
Simulation time 36363210433 ps
CPU time 469.36 seconds
Started Aug 25 06:25:25 AM UTC 24
Finished Aug 25 06:33:22 AM UTC 24
Peak memory 4196504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824762036 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.1824762036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.2103461860
Short name T1600
Test name
Test status
Simulation time 4409963609 ps
CPU time 67.07 seconds
Started Aug 25 06:25:28 AM UTC 24
Finished Aug 25 06:26:38 AM UTC 24
Peak memory 516316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103461860 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.2103461860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.2034173016
Short name T1562
Test name
Test status
Simulation time 4360046702 ps
CPU time 10.67 seconds
Started Aug 25 06:25:35 AM UTC 24
Finished Aug 25 06:25:47 AM UTC 24
Peak memory 245992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034173
016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.2034173016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2625118544
Short name T1577
Test name
Test status
Simulation time 461334169 ps
CPU time 9.44 seconds
Started Aug 25 06:25:49 AM UTC 24
Finished Aug 25 06:25:59 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625118
544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2625118544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_alert_test.270472819
Short name T1608
Test name
Test status
Simulation time 28443392 ps
CPU time 0.91 seconds
Started Aug 25 06:26:41 AM UTC 24
Finished Aug 25 06:26:43 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270472819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.270472819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3409214402
Short name T1582
Test name
Test status
Simulation time 195941599 ps
CPU time 2.34 seconds
Started Aug 25 06:26:03 AM UTC 24
Finished Aug 25 06:26:06 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409214402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3409214402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.336845089
Short name T1589
Test name
Test status
Simulation time 907333307 ps
CPU time 29.65 seconds
Started Aug 25 06:25:57 AM UTC 24
Finished Aug 25 06:26:29 AM UTC 24
Peak memory 319516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336845089 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.336845089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2975030185
Short name T1728
Test name
Test status
Simulation time 58886795986 ps
CPU time 265.1 seconds
Started Aug 25 06:25:57 AM UTC 24
Finished Aug 25 06:30:27 AM UTC 24
Peak memory 805124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975030185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2975030185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3807242921
Short name T1635
Test name
Test status
Simulation time 45174212121 ps
CPU time 72.67 seconds
Started Aug 25 06:25:55 AM UTC 24
Finished Aug 25 06:27:10 AM UTC 24
Peak memory 719060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807242921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3807242921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2169668509
Short name T1576
Test name
Test status
Simulation time 134148509 ps
CPU time 1.64 seconds
Started Aug 25 06:25:56 AM UTC 24
Finished Aug 25 06:25:59 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169668509 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.2169668509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.3350101835
Short name T1581
Test name
Test status
Simulation time 213766679 ps
CPU time 7.15 seconds
Started Aug 25 06:25:57 AM UTC 24
Finished Aug 25 06:26:06 AM UTC 24
Peak memory 256104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350101835 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.3350101835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4026446898
Short name T1688
Test name
Test status
Simulation time 9164123896 ps
CPU time 141.15 seconds
Started Aug 25 06:25:55 AM UTC 24
Finished Aug 25 06:28:19 AM UTC 24
Peak memory 1355852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026446898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4026446898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2660567582
Short name T1607
Test name
Test status
Simulation time 353347765 ps
CPU time 6.25 seconds
Started Aug 25 06:26:34 AM UTC 24
Finished Aug 25 06:26:42 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660567582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2660567582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_override.2784721692
Short name T1522
Test name
Test status
Simulation time 205792492 ps
CPU time 1.05 seconds
Started Aug 25 06:25:54 AM UTC 24
Finished Aug 25 06:25:56 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784721692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2784721692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_perf.3350814972
Short name T1583
Test name
Test status
Simulation time 543093707 ps
CPU time 6.9 seconds
Started Aug 25 06:26:00 AM UTC 24
Finished Aug 25 06:26:08 AM UTC 24
Peak memory 241968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350814972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3350814972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3674735329
Short name T1585
Test name
Test status
Simulation time 3069589216 ps
CPU time 16.06 seconds
Started Aug 25 06:26:00 AM UTC 24
Finished Aug 25 06:26:17 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674735329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3674735329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.2117721097
Short name T1593
Test name
Test status
Simulation time 5776676782 ps
CPU time 36.03 seconds
Started Aug 25 06:25:53 AM UTC 24
Finished Aug 25 06:26:31 AM UTC 24
Peak memory 344480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117721097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2117721097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_stress_all.3812277044
Short name T1725
Test name
Test status
Simulation time 23789939199 ps
CPU time 223.71 seconds
Started Aug 25 06:26:06 AM UTC 24
Finished Aug 25 06:29:54 AM UTC 24
Peak memory 1315036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812277044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3812277044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.972342694
Short name T1602
Test name
Test status
Simulation time 1290001955 ps
CPU time 34.95 seconds
Started Aug 25 06:26:03 AM UTC 24
Finished Aug 25 06:26:39 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972342694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.972342694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3474640241
Short name T1605
Test name
Test status
Simulation time 15919104281 ps
CPU time 7.57 seconds
Started Aug 25 06:26:32 AM UTC 24
Finished Aug 25 06:26:41 AM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3474640241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.3474640241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.616166985
Short name T321
Test name
Test status
Simulation time 346868164 ps
CPU time 3.19 seconds
Started Aug 25 06:26:30 AM UTC 24
Finished Aug 25 06:26:34 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6161669
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.616166985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3675353109
Short name T1596
Test name
Test status
Simulation time 352988036 ps
CPU time 1.55 seconds
Started Aug 25 06:26:31 AM UTC 24
Finished Aug 25 06:26:33 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675353
109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.3675353109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1352848953
Short name T1601
Test name
Test status
Simulation time 478093858 ps
CPU time 3.72 seconds
Started Aug 25 06:26:34 AM UTC 24
Finished Aug 25 06:26:39 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352848
953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar
ks_acq.1352848953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.293792403
Short name T1591
Test name
Test status
Simulation time 1089065366 ps
CPU time 11.89 seconds
Started Aug 25 06:26:17 AM UTC 24
Finished Aug 25 06:26:30 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293792
403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.293792403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.982827446
Short name T1735
Test name
Test status
Simulation time 22504126379 ps
CPU time 545.57 seconds
Started Aug 25 06:26:21 AM UTC 24
Finished Aug 25 06:35:34 AM UTC 24
Peak memory 5386460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=982827446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress
_wr.982827446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.482608057
Short name T1611
Test name
Test status
Simulation time 2240070883 ps
CPU time 4.35 seconds
Started Aug 25 06:26:39 AM UTC 24
Finished Aug 25 06:26:44 AM UTC 24
Peak memory 227244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4826080
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.482608057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.430385458
Short name T1613
Test name
Test status
Simulation time 477916595 ps
CPU time 3.64 seconds
Started Aug 25 06:26:40 AM UTC 24
Finished Aug 25 06:26:44 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4303854
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.430385458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.3008581145
Short name T1610
Test name
Test status
Simulation time 313243781 ps
CPU time 2.16 seconds
Started Aug 25 06:26:40 AM UTC 24
Finished Aug 25 06:26:43 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008581
145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_txstretch.3008581145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3809855282
Short name T1606
Test name
Test status
Simulation time 807099736 ps
CPU time 8.14 seconds
Started Aug 25 06:26:32 AM UTC 24
Finished Aug 25 06:26:41 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809855
282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.3809855282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2666222108
Short name T1615
Test name
Test status
Simulation time 665008679 ps
CPU time 4.89 seconds
Started Aug 25 06:26:38 AM UTC 24
Finished Aug 25 06:26:45 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666222
108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.2666222108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2871958882
Short name T1616
Test name
Test status
Simulation time 930222519 ps
CPU time 37.79 seconds
Started Aug 25 06:26:07 AM UTC 24
Finished Aug 25 06:26:46 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871958882 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.2871958882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.1855998149
Short name T1672
Test name
Test status
Simulation time 39403941010 ps
CPU time 83.35 seconds
Started Aug 25 06:26:32 AM UTC 24
Finished Aug 25 06:27:57 AM UTC 24
Peak memory 323820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185599
8149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.1855998149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.2171706184
Short name T1595
Test name
Test status
Simulation time 1644199791 ps
CPU time 24.05 seconds
Started Aug 25 06:26:08 AM UTC 24
Finished Aug 25 06:26:33 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171706184 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.2171706184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2302592105
Short name T1677
Test name
Test status
Simulation time 23568716046 ps
CPU time 109.61 seconds
Started Aug 25 06:26:07 AM UTC 24
Finished Aug 25 06:27:59 AM UTC 24
Peak memory 1054868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302592105 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.2302592105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.2294312943
Short name T1588
Test name
Test status
Simulation time 1127817522 ps
CPU time 12.48 seconds
Started Aug 25 06:26:14 AM UTC 24
Finished Aug 25 06:26:28 AM UTC 24
Peak memory 253980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294312943 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.2294312943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.3542459075
Short name T1594
Test name
Test status
Simulation time 1196702369 ps
CPU time 9.64 seconds
Started Aug 25 06:26:21 AM UTC 24
Finished Aug 25 06:26:32 AM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542459
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.3542459075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3882265133
Short name T1612
Test name
Test status
Simulation time 402369782 ps
CPU time 7.92 seconds
Started Aug 25 06:26:35 AM UTC 24
Finished Aug 25 06:26:44 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882265
133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3882265133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2725813852
Short name T1645
Test name
Test status
Simulation time 41348667 ps
CPU time 1.07 seconds
Started Aug 25 06:27:15 AM UTC 24
Finished Aug 25 06:27:17 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725813852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2725813852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.1679001689
Short name T1626
Test name
Test status
Simulation time 4357785649 ps
CPU time 16.09 seconds
Started Aug 25 06:26:46 AM UTC 24
Finished Aug 25 06:27:03 AM UTC 24
Peak memory 256340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679001689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1679001689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.550452657
Short name T1644
Test name
Test status
Simulation time 678356044 ps
CPU time 30.4 seconds
Started Aug 25 06:26:44 AM UTC 24
Finished Aug 25 06:27:16 AM UTC 24
Peak memory 303388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550452657 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.550452657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.4170224557
Short name T1720
Test name
Test status
Simulation time 2528029645 ps
CPU time 149.05 seconds
Started Aug 25 06:26:45 AM UTC 24
Finished Aug 25 06:29:18 AM UTC 24
Peak memory 401548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170224557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.4170224557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1320793278
Short name T1722
Test name
Test status
Simulation time 2078619299 ps
CPU time 164.03 seconds
Started Aug 25 06:26:42 AM UTC 24
Finished Aug 25 06:29:29 AM UTC 24
Peak memory 723048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320793278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1320793278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.836192640
Short name T1617
Test name
Test status
Simulation time 555241284 ps
CPU time 1.82 seconds
Started Aug 25 06:26:43 AM UTC 24
Finished Aug 25 06:26:46 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836192640 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.836192640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.4277701026
Short name T1621
Test name
Test status
Simulation time 212542747 ps
CPU time 7.68 seconds
Started Aug 25 06:26:44 AM UTC 24
Finished Aug 25 06:26:53 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277701026 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.4277701026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.71487419
Short name T1673
Test name
Test status
Simulation time 12999689727 ps
CPU time 73.12 seconds
Started Aug 25 06:26:42 AM UTC 24
Finished Aug 25 06:27:57 AM UTC 24
Peak memory 946252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71487419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.71487419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3425238200
Short name T1652
Test name
Test status
Simulation time 4358970715 ps
CPU time 12.1 seconds
Started Aug 25 06:27:08 AM UTC 24
Finished Aug 25 06:27:21 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425238200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3425238200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_override.3070099914
Short name T1614
Test name
Test status
Simulation time 47653938 ps
CPU time 1.1 seconds
Started Aug 25 06:26:42 AM UTC 24
Finished Aug 25 06:26:44 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070099914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3070099914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_perf.2187360181
Short name T1723
Test name
Test status
Simulation time 12642347418 ps
CPU time 171.63 seconds
Started Aug 25 06:26:45 AM UTC 24
Finished Aug 25 06:29:41 AM UTC 24
Peak memory 530764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187360181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2187360181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1441266187
Short name T1619
Test name
Test status
Simulation time 80409045 ps
CPU time 1.82 seconds
Started Aug 25 06:26:46 AM UTC 24
Finished Aug 25 06:26:49 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441266187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1441266187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.2124116028
Short name T1599
Test name
Test status
Simulation time 6986622762 ps
CPU time 44.49 seconds
Started Aug 25 06:26:42 AM UTC 24
Finished Aug 25 06:27:28 AM UTC 24
Peak memory 376984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124116028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2124116028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3119174123
Short name T1628
Test name
Test status
Simulation time 2959105613 ps
CPU time 18 seconds
Started Aug 25 06:26:46 AM UTC 24
Finished Aug 25 06:27:05 AM UTC 24
Peak memory 231096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119174123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3119174123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2097993028
Short name T1648
Test name
Test status
Simulation time 6231061597 ps
CPU time 10.51 seconds
Started Aug 25 06:27:07 AM UTC 24
Finished Aug 25 06:27:18 AM UTC 24
Peak memory 229104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2097993028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad
dr.2097993028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2867427196
Short name T1630
Test name
Test status
Simulation time 168754359 ps
CPU time 1.54 seconds
Started Aug 25 06:27:03 AM UTC 24
Finished Aug 25 06:27:06 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867427
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.2867427196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.1589246636
Short name T1634
Test name
Test status
Simulation time 151878773 ps
CPU time 1.38 seconds
Started Aug 25 06:27:05 AM UTC 24
Finished Aug 25 06:27:07 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589246
636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.1589246636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1884324674
Short name T1639
Test name
Test status
Simulation time 283905148 ps
CPU time 2.78 seconds
Started Aug 25 06:27:08 AM UTC 24
Finished Aug 25 06:27:12 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884324
674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermar
ks_acq.1884324674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3559193158
Short name T1636
Test name
Test status
Simulation time 344907221 ps
CPU time 1.49 seconds
Started Aug 25 06:27:08 AM UTC 24
Finished Aug 25 06:27:11 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559193
158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_tx.3559193158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.3487998862
Short name T1637
Test name
Test status
Simulation time 279046533 ps
CPU time 3.5 seconds
Started Aug 25 06:27:07 AM UTC 24
Finished Aug 25 06:27:11 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487998
862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.3487998862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.4135827957
Short name T1631
Test name
Test status
Simulation time 6222640812 ps
CPU time 11.07 seconds
Started Aug 25 06:26:54 AM UTC 24
Finished Aug 25 06:27:06 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413582
7957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.4135827957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2828779195
Short name T1718
Test name
Test status
Simulation time 13218436441 ps
CPU time 138.94 seconds
Started Aug 25 06:26:54 AM UTC 24
Finished Aug 25 06:29:16 AM UTC 24
Peak memory 1771744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2828779195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.2828779195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.4148336112
Short name T1650
Test name
Test status
Simulation time 1049315609 ps
CPU time 5.56 seconds
Started Aug 25 06:27:12 AM UTC 24
Finished Aug 25 06:27:19 AM UTC 24
Peak memory 226916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148336
112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.4148336112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2170263649
Short name T1647
Test name
Test status
Simulation time 537147420 ps
CPU time 4.18 seconds
Started Aug 25 06:27:12 AM UTC 24
Finished Aug 25 06:27:18 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170263
649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad
dr.2170263649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.1897519276
Short name T1642
Test name
Test status
Simulation time 1752124077 ps
CPU time 1.92 seconds
Started Aug 25 06:27:13 AM UTC 24
Finished Aug 25 06:27:16 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897519
276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.1897519276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_perf.2850524369
Short name T1641
Test name
Test status
Simulation time 4239130393 ps
CPU time 9.66 seconds
Started Aug 25 06:27:05 AM UTC 24
Finished Aug 25 06:27:15 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850524
369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.2850524369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.2748147412
Short name T1643
Test name
Test status
Simulation time 884043519 ps
CPU time 3.79 seconds
Started Aug 25 06:27:11 AM UTC 24
Finished Aug 25 06:27:16 AM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748147
412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.2748147412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.121705151
Short name T1624
Test name
Test status
Simulation time 1323282248 ps
CPU time 12.88 seconds
Started Aug 25 06:26:47 AM UTC 24
Finished Aug 25 06:27:01 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121705151 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.121705151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2839531478
Short name T1701
Test name
Test status
Simulation time 60988123196 ps
CPU time 352.82 seconds
Started Aug 25 06:27:06 AM UTC 24
Finished Aug 25 06:33:04 AM UTC 24
Peak memory 2529516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283953
1478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.2839531478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3352651645
Short name T1632
Test name
Test status
Simulation time 709756483 ps
CPU time 16.57 seconds
Started Aug 25 06:26:49 AM UTC 24
Finished Aug 25 06:27:07 AM UTC 24
Peak memory 229164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352651645 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.3352651645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.2461219512
Short name T1744
Test name
Test status
Simulation time 69922938440 ps
CPU time 861.96 seconds
Started Aug 25 06:26:49 AM UTC 24
Finished Aug 25 06:41:22 AM UTC 24
Peak memory 6375636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461219512 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.2461219512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.279850246
Short name T1646
Test name
Test status
Simulation time 3163716106 ps
CPU time 23.09 seconds
Started Aug 25 06:26:53 AM UTC 24
Finished Aug 25 06:27:17 AM UTC 24
Peak memory 588184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279850246 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.279850246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.3869935506
Short name T1638
Test name
Test status
Simulation time 1425622792 ps
CPU time 13.24 seconds
Started Aug 25 06:26:57 AM UTC 24
Finished Aug 25 06:27:12 AM UTC 24
Peak memory 228848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869935
506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.3869935506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2141626140
Short name T1640
Test name
Test status
Simulation time 82443251 ps
CPU time 3.17 seconds
Started Aug 25 06:27:11 AM UTC 24
Finished Aug 25 06:27:15 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141626
140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2141626140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3264148303
Short name T1674
Test name
Test status
Simulation time 26095103 ps
CPU time 0.94 seconds
Started Aug 25 06:27:55 AM UTC 24
Finished Aug 25 06:27:57 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264148303 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3264148303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1537512476
Short name T1653
Test name
Test status
Simulation time 596679641 ps
CPU time 3.63 seconds
Started Aug 25 06:27:20 AM UTC 24
Finished Aug 25 06:27:25 AM UTC 24
Peak memory 233400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537512476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1537512476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.273837460
Short name T1663
Test name
Test status
Simulation time 2053261454 ps
CPU time 29.84 seconds
Started Aug 25 06:27:18 AM UTC 24
Finished Aug 25 06:27:49 AM UTC 24
Peak memory 301128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273837460 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.273837460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2712482308
Short name T1694
Test name
Test status
Simulation time 4577457017 ps
CPU time 75.83 seconds
Started Aug 25 06:27:18 AM UTC 24
Finished Aug 25 06:28:36 AM UTC 24
Peak memory 266508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712482308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2712482308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.109543575
Short name T1717
Test name
Test status
Simulation time 9000055941 ps
CPU time 108.46 seconds
Started Aug 25 06:27:17 AM UTC 24
Finished Aug 25 06:29:08 AM UTC 24
Peak memory 342224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109543575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.109543575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3797674076
Short name T1651
Test name
Test status
Simulation time 446122360 ps
CPU time 1.75 seconds
Started Aug 25 06:27:17 AM UTC 24
Finished Aug 25 06:27:20 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797674076 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3797674076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2896293629
Short name T1654
Test name
Test status
Simulation time 257893502 ps
CPU time 7.76 seconds
Started Aug 25 06:27:18 AM UTC 24
Finished Aug 25 06:27:27 AM UTC 24
Peak memory 252236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896293629 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.2896293629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.853934004
Short name T1734
Test name
Test status
Simulation time 18949382652 ps
CPU time 344.32 seconds
Started Aug 25 06:27:17 AM UTC 24
Finished Aug 25 06:33:07 AM UTC 24
Peak memory 1352116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853934004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.853934004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1401003942
Short name T1668
Test name
Test status
Simulation time 1246377105 ps
CPU time 5.13 seconds
Started Aug 25 06:27:47 AM UTC 24
Finished Aug 25 06:27:53 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401003942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1401003942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1365859060
Short name T1666
Test name
Test status
Simulation time 460468681 ps
CPU time 4.92 seconds
Started Aug 25 06:27:45 AM UTC 24
Finished Aug 25 06:27:51 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365859060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1365859060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_override.2045723410
Short name T1649
Test name
Test status
Simulation time 71874207 ps
CPU time 0.99 seconds
Started Aug 25 06:27:17 AM UTC 24
Finished Aug 25 06:27:19 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045723410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2045723410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1453175680
Short name T1664
Test name
Test status
Simulation time 6822752523 ps
CPU time 29.81 seconds
Started Aug 25 06:27:19 AM UTC 24
Finished Aug 25 06:27:50 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453175680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1453175680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.4101300835
Short name T1618
Test name
Test status
Simulation time 2599242712 ps
CPU time 12.02 seconds
Started Aug 25 06:27:19 AM UTC 24
Finished Aug 25 06:27:33 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101300835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.4101300835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1804225370
Short name T1719
Test name
Test status
Simulation time 8523179801 ps
CPU time 117.02 seconds
Started Aug 25 06:27:17 AM UTC 24
Finished Aug 25 06:29:16 AM UTC 24
Peak memory 364836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804225370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1804225370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.773587183
Short name T1659
Test name
Test status
Simulation time 3832216532 ps
CPU time 21.8 seconds
Started Aug 25 06:27:20 AM UTC 24
Finished Aug 25 06:27:43 AM UTC 24
Peak memory 233124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773587183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.773587183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.958204430
Short name T1665
Test name
Test status
Simulation time 702019810 ps
CPU time 5.43 seconds
Started Aug 25 06:27:44 AM UTC 24
Finished Aug 25 06:27:51 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=958204430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.958204430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.1655850064
Short name T1656
Test name
Test status
Simulation time 410521247 ps
CPU time 1.61 seconds
Started Aug 25 06:27:37 AM UTC 24
Finished Aug 25 06:27:40 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655850
064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.1655850064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3317426417
Short name T1658
Test name
Test status
Simulation time 958133242 ps
CPU time 2.74 seconds
Started Aug 25 06:27:39 AM UTC 24
Finished Aug 25 06:27:43 AM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317426
417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.3317426417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2235514705
Short name T1667
Test name
Test status
Simulation time 371265903 ps
CPU time 3.64 seconds
Started Aug 25 06:27:47 AM UTC 24
Finished Aug 25 06:27:52 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235514
705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar
ks_acq.2235514705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1357252422
Short name T1669
Test name
Test status
Simulation time 263036611 ps
CPU time 2.06 seconds
Started Aug 25 06:27:50 AM UTC 24
Finished Aug 25 06:27:54 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357252
422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.1357252422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.1737008431
Short name T1657
Test name
Test status
Simulation time 5544594020 ps
CPU time 11.5 seconds
Started Aug 25 06:27:30 AM UTC 24
Finished Aug 25 06:27:43 AM UTC 24
Peak memory 231036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173700
8431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.1737008431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.3904254345
Short name T1713
Test name
Test status
Simulation time 10852245924 ps
CPU time 79.44 seconds
Started Aug 25 06:27:33 AM UTC 24
Finished Aug 25 06:28:54 AM UTC 24
Peak memory 1026268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3904254345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres
s_wr.3904254345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4253584459
Short name T1676
Test name
Test status
Simulation time 2203142153 ps
CPU time 4.85 seconds
Started Aug 25 06:27:51 AM UTC 24
Finished Aug 25 06:27:58 AM UTC 24
Peak memory 226860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253584
459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.4253584459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2011278688
Short name T1675
Test name
Test status
Simulation time 458939753 ps
CPU time 3.44 seconds
Started Aug 25 06:27:52 AM UTC 24
Finished Aug 25 06:27:58 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011278
688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_ad
dr.2011278688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.341381808
Short name T1671
Test name
Test status
Simulation time 544381757 ps
CPU time 2.63 seconds
Started Aug 25 06:27:52 AM UTC 24
Finished Aug 25 06:27:57 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413818
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_txstretch.341381808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_perf.1861799493
Short name T1662
Test name
Test status
Simulation time 749552702 ps
CPU time 7.24 seconds
Started Aug 25 06:27:41 AM UTC 24
Finished Aug 25 06:27:49 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861799
493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.1861799493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1924472987
Short name T1670
Test name
Test status
Simulation time 2006324733 ps
CPU time 3.93 seconds
Started Aug 25 06:27:51 AM UTC 24
Finished Aug 25 06:27:57 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924472
987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.1924472987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3985305047
Short name T1629
Test name
Test status
Simulation time 1985232076 ps
CPU time 9.04 seconds
Started Aug 25 06:27:26 AM UTC 24
Finished Aug 25 06:27:36 AM UTC 24
Peak memory 229104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985305047 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.3985305047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3691028325
Short name T1714
Test name
Test status
Simulation time 73183263662 ps
CPU time 74.64 seconds
Started Aug 25 06:27:41 AM UTC 24
Finished Aug 25 06:28:57 AM UTC 24
Peak memory 270684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369102
8325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.3691028325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.4265081398
Short name T1660
Test name
Test status
Simulation time 614653123 ps
CPU time 15.57 seconds
Started Aug 25 06:27:29 AM UTC 24
Finished Aug 25 06:27:46 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265081398 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.4265081398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.3401045645
Short name T1740
Test name
Test status
Simulation time 41800498967 ps
CPU time 691.66 seconds
Started Aug 25 06:27:28 AM UTC 24
Finished Aug 25 06:39:09 AM UTC 24
Peak memory 5624020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401045645 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.3401045645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.1124144992
Short name T1655
Test name
Test status
Simulation time 5659651477 ps
CPU time 6.96 seconds
Started Aug 25 06:27:29 AM UTC 24
Finished Aug 25 06:27:37 AM UTC 24
Peak memory 233660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124144992 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.1124144992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1976452763
Short name T1661
Test name
Test status
Simulation time 1783444020 ps
CPU time 10.5 seconds
Started Aug 25 06:27:34 AM UTC 24
Finished Aug 25 06:27:46 AM UTC 24
Peak memory 230912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976452
763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.1976452763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.325860377
Short name T1678
Test name
Test status
Simulation time 266589807 ps
CPU time 8.11 seconds
Started Aug 25 06:27:50 AM UTC 24
Finished Aug 25 06:28:00 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258603
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.325860377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_alert_test.236335515
Short name T1709
Test name
Test status
Simulation time 16594385 ps
CPU time 1.02 seconds
Started Aug 25 06:28:47 AM UTC 24
Finished Aug 25 06:28:50 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236335515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.236335515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2679403438
Short name T1684
Test name
Test status
Simulation time 153664221 ps
CPU time 6.82 seconds
Started Aug 25 06:28:01 AM UTC 24
Finished Aug 25 06:28:09 AM UTC 24
Peak memory 246120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679403438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2679403438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.3360257581
Short name T1687
Test name
Test status
Simulation time 4080047321 ps
CPU time 18.18 seconds
Started Aug 25 06:27:58 AM UTC 24
Finished Aug 25 06:28:18 AM UTC 24
Peak memory 282940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360257581 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.3360257581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.602084564
Short name T1729
Test name
Test status
Simulation time 22167564188 ps
CPU time 199.94 seconds
Started Aug 25 06:27:59 AM UTC 24
Finished Aug 25 06:31:23 AM UTC 24
Peak memory 434380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602084564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.602084564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.411979570
Short name T1700
Test name
Test status
Simulation time 6126778245 ps
CPU time 43.64 seconds
Started Aug 25 06:27:58 AM UTC 24
Finished Aug 25 06:28:43 AM UTC 24
Peak memory 604316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411979570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.411979570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.3866469300
Short name T1680
Test name
Test status
Simulation time 348296690 ps
CPU time 1.47 seconds
Started Aug 25 06:27:58 AM UTC 24
Finished Aug 25 06:28:01 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866469300 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.3866469300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2883314757
Short name T1685
Test name
Test status
Simulation time 273963732 ps
CPU time 9.61 seconds
Started Aug 25 06:27:59 AM UTC 24
Finished Aug 25 06:28:10 AM UTC 24
Peak memory 237568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883314757 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.2883314757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2242413660
Short name T1727
Test name
Test status
Simulation time 20617138479 ps
CPU time 137.84 seconds
Started Aug 25 06:27:58 AM UTC 24
Finished Aug 25 06:30:19 AM UTC 24
Peak memory 1257672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242413660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2242413660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3326756208
Short name T1703
Test name
Test status
Simulation time 317334349 ps
CPU time 6.3 seconds
Started Aug 25 06:28:38 AM UTC 24
Finished Aug 25 06:28:45 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326756208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3326756208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_override.2726483487
Short name T1679
Test name
Test status
Simulation time 45959351 ps
CPU time 0.99 seconds
Started Aug 25 06:27:58 AM UTC 24
Finished Aug 25 06:28:00 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726483487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2726483487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_perf.3216454957
Short name T1731
Test name
Test status
Simulation time 6669876548 ps
CPU time 257.07 seconds
Started Aug 25 06:28:00 AM UTC 24
Finished Aug 25 06:32:22 AM UTC 24
Peak memory 1608192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216454957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3216454957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.1089026288
Short name T1682
Test name
Test status
Simulation time 210443635 ps
CPU time 2.24 seconds
Started Aug 25 06:28:01 AM UTC 24
Finished Aug 25 06:28:05 AM UTC 24
Peak memory 241636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089026288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.1089026288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1357661633
Short name T1690
Test name
Test status
Simulation time 5656937313 ps
CPU time 35.04 seconds
Started Aug 25 06:27:55 AM UTC 24
Finished Aug 25 06:28:32 AM UTC 24
Peak memory 326112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357661633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1357661633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_stress_all.2210581976
Short name T301
Test name
Test status
Simulation time 76945824724 ps
CPU time 1326.68 seconds
Started Aug 25 06:28:02 AM UTC 24
Finished Aug 25 06:50:25 AM UTC 24
Peak memory 2478380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210581976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2210581976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2478334486
Short name T1686
Test name
Test status
Simulation time 650321882 ps
CPU time 15.43 seconds
Started Aug 25 06:28:01 AM UTC 24
Finished Aug 25 06:28:18 AM UTC 24
Peak memory 228920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478334486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2478334486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.1391014173
Short name T1707
Test name
Test status
Simulation time 1093889619 ps
CPU time 10.74 seconds
Started Aug 25 06:28:37 AM UTC 24
Finished Aug 25 06:28:49 AM UTC 24
Peak memory 233036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1391014173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad
dr.1391014173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1602770085
Short name T1695
Test name
Test status
Simulation time 242523485 ps
CPU time 1.75 seconds
Started Aug 25 06:28:33 AM UTC 24
Finished Aug 25 06:28:36 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602770
085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.1602770085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.981772416
Short name T1696
Test name
Test status
Simulation time 227849698 ps
CPU time 2.43 seconds
Started Aug 25 06:28:33 AM UTC 24
Finished Aug 25 06:28:37 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9817724
16 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.981772416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1344763255
Short name T1705
Test name
Test status
Simulation time 1930994511 ps
CPU time 5.09 seconds
Started Aug 25 06:28:41 AM UTC 24
Finished Aug 25 06:28:47 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344763
255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermar
ks_acq.1344763255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.2760190961
Short name T1702
Test name
Test status
Simulation time 512050598 ps
CPU time 1.72 seconds
Started Aug 25 06:28:42 AM UTC 24
Finished Aug 25 06:28:45 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760190
961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark
s_tx.2760190961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1649894792
Short name T1689
Test name
Test status
Simulation time 9352049240 ps
CPU time 8.35 seconds
Started Aug 25 06:28:19 AM UTC 24
Finished Aug 25 06:28:29 AM UTC 24
Peak memory 228932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164989
4792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.1649894792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3100935783
Short name T1697
Test name
Test status
Simulation time 20250342763 ps
CPU time 20.79 seconds
Started Aug 25 06:28:19 AM UTC 24
Finished Aug 25 06:28:41 AM UTC 24
Peak memory 465308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3100935783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stres
s_wr.3100935783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.307264216
Short name T1708
Test name
Test status
Simulation time 1787489878 ps
CPU time 4.13 seconds
Started Aug 25 06:28:44 AM UTC 24
Finished Aug 25 06:28:49 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072642
16 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.307264216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3271956780
Short name T1712
Test name
Test status
Simulation time 1147785654 ps
CPU time 4.58 seconds
Started Aug 25 06:28:45 AM UTC 24
Finished Aug 25 06:28:51 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271956
780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.3271956780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1092521764
Short name T1710
Test name
Test status
Simulation time 132639740 ps
CPU time 2.12 seconds
Started Aug 25 06:28:46 AM UTC 24
Finished Aug 25 06:28:50 AM UTC 24
Peak memory 233732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092521
764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.1092521764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_perf.1655007548
Short name T1699
Test name
Test status
Simulation time 687208924 ps
CPU time 7.78 seconds
Started Aug 25 06:28:33 AM UTC 24
Finished Aug 25 06:28:42 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655007
548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.1655007548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1963111755
Short name T1706
Test name
Test status
Simulation time 2387663219 ps
CPU time 4.33 seconds
Started Aug 25 06:28:43 AM UTC 24
Finished Aug 25 06:28:49 AM UTC 24
Peak memory 216496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963111
755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.1963111755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.3579955752
Short name T1715
Test name
Test status
Simulation time 1358749552 ps
CPU time 51.32 seconds
Started Aug 25 06:28:06 AM UTC 24
Finished Aug 25 06:28:59 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579955752 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.3579955752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3315574116
Short name T1737
Test name
Test status
Simulation time 55162793760 ps
CPU time 510.88 seconds
Started Aug 25 06:28:34 AM UTC 24
Finished Aug 25 06:37:12 AM UTC 24
Peak memory 3119320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331557
4116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.3315574116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1004777193
Short name T1716
Test name
Test status
Simulation time 1665290723 ps
CPU time 49.12 seconds
Started Aug 25 06:28:11 AM UTC 24
Finished Aug 25 06:29:02 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004777193 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.1004777193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1070644442
Short name T1721
Test name
Test status
Simulation time 61772494417 ps
CPU time 72.65 seconds
Started Aug 25 06:28:11 AM UTC 24
Finished Aug 25 06:29:25 AM UTC 24
Peak memory 915648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070644442 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.1070644442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.735182489
Short name T1711
Test name
Test status
Simulation time 2962869850 ps
CPU time 37.2 seconds
Started Aug 25 06:28:12 AM UTC 24
Finished Aug 25 06:28:51 AM UTC 24
Peak memory 360964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735182489 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.735182489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.786468954
Short name T1692
Test name
Test status
Simulation time 1575359037 ps
CPU time 12.03 seconds
Started Aug 25 06:28:20 AM UTC 24
Finished Aug 25 06:28:34 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7864689
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.786468954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.947252369
Short name T1704
Test name
Test status
Simulation time 68756312 ps
CPU time 2.43 seconds
Started Aug 25 06:28:43 AM UTC 24
Finished Aug 25 06:28:47 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9472523
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.947252369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_alert_test.2609760217
Short name T378
Test name
Test status
Simulation time 31909387 ps
CPU time 0.88 seconds
Started Aug 25 05:57:51 AM UTC 24
Finished Aug 25 05:57:53 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609760217 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2609760217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.2401272487
Short name T370
Test name
Test status
Simulation time 86865729 ps
CPU time 2.59 seconds
Started Aug 25 05:57:17 AM UTC 24
Finished Aug 25 05:57:20 AM UTC 24
Peak memory 230924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401272487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2401272487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.1489392544
Short name T313
Test name
Test status
Simulation time 298045600 ps
CPU time 8.17 seconds
Started Aug 25 05:57:11 AM UTC 24
Finished Aug 25 05:57:21 AM UTC 24
Peak memory 276500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489392544 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.1489392544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.2978794500
Short name T487
Test name
Test status
Simulation time 5753667700 ps
CPU time 220.19 seconds
Started Aug 25 05:57:14 AM UTC 24
Finished Aug 25 06:00:59 AM UTC 24
Peak memory 749976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978794500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2978794500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.175586721
Short name T99
Test name
Test status
Simulation time 10904370929 ps
CPU time 97.95 seconds
Started Aug 25 05:57:10 AM UTC 24
Finished Aug 25 05:58:51 AM UTC 24
Peak memory 831944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175586721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.175586721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.90177623
Short name T366
Test name
Test status
Simulation time 363179917 ps
CPU time 1.68 seconds
Started Aug 25 05:57:11 AM UTC 24
Finished Aug 25 05:57:14 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90177623 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.90177623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.1287954277
Short name T83
Test name
Test status
Simulation time 273247841 ps
CPU time 10.58 seconds
Started Aug 25 05:57:13 AM UTC 24
Finished Aug 25 05:57:25 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287954277 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.1287954277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.3088436485
Short name T511
Test name
Test status
Simulation time 16302297448 ps
CPU time 273.2 seconds
Started Aug 25 05:57:10 AM UTC 24
Finished Aug 25 06:01:48 AM UTC 24
Peak memory 1218956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088436485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3088436485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.4197275814
Short name T41
Test name
Test status
Simulation time 1313368115 ps
CPU time 16.16 seconds
Started Aug 25 05:57:42 AM UTC 24
Finished Aug 25 05:58:00 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197275814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4197275814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_override.3184965050
Short name T364
Test name
Test status
Simulation time 50347604 ps
CPU time 0.96 seconds
Started Aug 25 05:57:10 AM UTC 24
Finished Aug 25 05:57:12 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184965050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3184965050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_perf.2833196077
Short name T552
Test name
Test status
Simulation time 12417041740 ps
CPU time 334.42 seconds
Started Aug 25 05:57:14 AM UTC 24
Finished Aug 25 06:02:54 AM UTC 24
Peak memory 1542308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833196077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2833196077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.763687190
Short name T369
Test name
Test status
Simulation time 55229674 ps
CPU time 1.7 seconds
Started Aug 25 05:57:14 AM UTC 24
Finished Aug 25 05:57:17 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763687190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.763687190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3922157693
Short name T35
Test name
Test status
Simulation time 855433978 ps
CPU time 53.25 seconds
Started Aug 25 05:57:09 AM UTC 24
Finished Aug 25 05:58:05 AM UTC 24
Peak memory 296988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922157693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3922157693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_stress_all.2849755913
Short name T198
Test name
Test status
Simulation time 39496525837 ps
CPU time 481.05 seconds
Started Aug 25 05:57:18 AM UTC 24
Finished Aug 25 06:05:26 AM UTC 24
Peak memory 1233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849755913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2849755913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.1419366584
Short name T351
Test name
Test status
Simulation time 3656805745 ps
CPU time 14.82 seconds
Started Aug 25 05:57:16 AM UTC 24
Finished Aug 25 05:57:32 AM UTC 24
Peak memory 233784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419366584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1419366584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.1430707823
Short name T374
Test name
Test status
Simulation time 751445532 ps
CPU time 8.23 seconds
Started Aug 25 05:57:36 AM UTC 24
Finished Aug 25 05:57:45 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1430707823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1430707823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.1526086930
Short name T357
Test name
Test status
Simulation time 266550261 ps
CPU time 2.52 seconds
Started Aug 25 05:57:31 AM UTC 24
Finished Aug 25 05:57:35 AM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526086
930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.1526086930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.3622344922
Short name T195
Test name
Test status
Simulation time 382287162 ps
CPU time 1.47 seconds
Started Aug 25 05:57:33 AM UTC 24
Finished Aug 25 05:57:35 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622344
922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.3622344922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.2034890836
Short name T319
Test name
Test status
Simulation time 1904745338 ps
CPU time 4.84 seconds
Started Aug 25 05:57:44 AM UTC 24
Finished Aug 25 05:57:50 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034890
836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermark
s_acq.2034890836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.1959233933
Short name T371
Test name
Test status
Simulation time 840695367 ps
CPU time 8.96 seconds
Started Aug 25 05:57:26 AM UTC 24
Finished Aug 25 05:57:36 AM UTC 24
Peak memory 233076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195923
3933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.1959233933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.375543555
Short name T160
Test name
Test status
Simulation time 12266394578 ps
CPU time 37.64 seconds
Started Aug 25 05:57:26 AM UTC 24
Finished Aug 25 05:58:06 AM UTC 24
Peak memory 727436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=375543555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.375543555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.2861054243
Short name T381
Test name
Test status
Simulation time 2067831686 ps
CPU time 4.39 seconds
Started Aug 25 05:57:50 AM UTC 24
Finished Aug 25 05:57:55 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861054
243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.2861054243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.598598881
Short name T382
Test name
Test status
Simulation time 3052393539 ps
CPU time 5.49 seconds
Started Aug 25 05:57:50 AM UTC 24
Finished Aug 25 05:57:56 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5985988
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.598598881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_perf.2786679159
Short name T359
Test name
Test status
Simulation time 571357112 ps
CPU time 7.85 seconds
Started Aug 25 05:57:33 AM UTC 24
Finished Aug 25 05:57:42 AM UTC 24
Peak memory 233732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786679
159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.2786679159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2583058576
Short name T380
Test name
Test status
Simulation time 549001703 ps
CPU time 5.09 seconds
Started Aug 25 05:57:47 AM UTC 24
Finished Aug 25 05:57:54 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583058
576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.2583058576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.194481706
Short name T347
Test name
Test status
Simulation time 676075817 ps
CPU time 12.65 seconds
Started Aug 25 05:57:18 AM UTC 24
Finished Aug 25 05:57:32 AM UTC 24
Peak memory 226852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194481706 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.194481706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.2901080855
Short name T376
Test name
Test status
Simulation time 1289940260 ps
CPU time 23.75 seconds
Started Aug 25 05:57:22 AM UTC 24
Finished Aug 25 05:57:47 AM UTC 24
Peak memory 233608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901080855 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.2901080855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.3235439802
Short name T884
Test name
Test status
Simulation time 44812134827 ps
CPU time 787.29 seconds
Started Aug 25 05:57:21 AM UTC 24
Finished Aug 25 06:10:37 AM UTC 24
Peak memory 6502552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235439802 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.3235439802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.1841518093
Short name T386
Test name
Test status
Simulation time 3981064395 ps
CPU time 51.66 seconds
Started Aug 25 05:57:25 AM UTC 24
Finished Aug 25 05:58:19 AM UTC 24
Peak memory 561396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841518093 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.1841518093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.512189895
Short name T373
Test name
Test status
Simulation time 5574126165 ps
CPU time 10.31 seconds
Started Aug 25 05:57:27 AM UTC 24
Finished Aug 25 05:57:39 AM UTC 24
Peak memory 233916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5121898
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.512189895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.4250110601
Short name T155
Test name
Test status
Simulation time 492053996 ps
CPU time 11.56 seconds
Started Aug 25 05:57:47 AM UTC 24
Finished Aug 25 05:58:00 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250110
601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.4250110601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_alert_test.3327820725
Short name T392
Test name
Test status
Simulation time 35510007 ps
CPU time 0.82 seconds
Started Aug 25 05:58:30 AM UTC 24
Finished Aug 25 05:58:32 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327820725 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3327820725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.1411606672
Short name T30
Test name
Test status
Simulation time 151650759 ps
CPU time 2.82 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 05:58:06 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411606672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1411606672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.2421387433
Short name T157
Test name
Test status
Simulation time 696817694 ps
CPU time 4.66 seconds
Started Aug 25 05:57:57 AM UTC 24
Finished Aug 25 05:58:03 AM UTC 24
Peak memory 235904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421387433 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.2421387433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.2322674873
Short name T411
Test name
Test status
Simulation time 16115601419 ps
CPU time 84.17 seconds
Started Aug 25 05:58:00 AM UTC 24
Finished Aug 25 05:59:26 AM UTC 24
Peak memory 539152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322674873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2322674873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.2231795568
Short name T433
Test name
Test status
Simulation time 9690148101 ps
CPU time 156.51 seconds
Started Aug 25 05:57:55 AM UTC 24
Finished Aug 25 06:00:35 AM UTC 24
Peak memory 735324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231795568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2231795568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.3859594544
Short name T156
Test name
Test status
Simulation time 541697684 ps
CPU time 1.97 seconds
Started Aug 25 05:57:57 AM UTC 24
Finished Aug 25 05:58:00 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859594544 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.3859594544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.3603571981
Short name T190
Test name
Test status
Simulation time 529123881 ps
CPU time 10.2 seconds
Started Aug 25 05:57:57 AM UTC 24
Finished Aug 25 05:58:09 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603571981 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.3603571981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.1283842873
Short name T117
Test name
Test status
Simulation time 5000844073 ps
CPU time 132.05 seconds
Started Aug 25 05:57:55 AM UTC 24
Finished Aug 25 06:00:10 AM UTC 24
Peak memory 1487084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283842873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1283842873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.2242122409
Short name T127
Test name
Test status
Simulation time 579092658 ps
CPU time 28.36 seconds
Started Aug 25 05:58:24 AM UTC 24
Finished Aug 25 05:58:54 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242122409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2242122409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.3321926783
Short name T78
Test name
Test status
Simulation time 133346692 ps
CPU time 2.17 seconds
Started Aug 25 05:58:21 AM UTC 24
Finished Aug 25 05:58:24 AM UTC 24
Peak memory 231232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321926783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3321926783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_override.3861914586
Short name T144
Test name
Test status
Simulation time 32403704 ps
CPU time 1.17 seconds
Started Aug 25 05:57:55 AM UTC 24
Finished Aug 25 05:57:57 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861914586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3861914586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_perf.699795580
Short name T16
Test name
Test status
Simulation time 2466593001 ps
CPU time 21.85 seconds
Started Aug 25 05:58:00 AM UTC 24
Finished Aug 25 05:58:23 AM UTC 24
Peak memory 216680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699795580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.699795580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.3389005078
Short name T159
Test name
Test status
Simulation time 125185212 ps
CPU time 2.15 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 05:58:05 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389005078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.3389005078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.1400208011
Short name T290
Test name
Test status
Simulation time 8555193978 ps
CPU time 45.53 seconds
Started Aug 25 05:57:54 AM UTC 24
Finished Aug 25 05:58:41 AM UTC 24
Peak memory 331936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400208011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1400208011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.3278221781
Short name T92
Test name
Test status
Simulation time 833937778 ps
CPU time 42.69 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 05:58:46 AM UTC 24
Peak memory 233792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278221781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3278221781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.3731012130
Short name T389
Test name
Test status
Simulation time 3306379554 ps
CPU time 10.01 seconds
Started Aug 25 05:58:17 AM UTC 24
Finished Aug 25 05:58:28 AM UTC 24
Peak memory 229092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3731012130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3731012130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.2242421577
Short name T383
Test name
Test status
Simulation time 140319565 ps
CPU time 1.54 seconds
Started Aug 25 05:58:11 AM UTC 24
Finished Aug 25 05:58:13 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242421
577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.2242421577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.1262795864
Short name T384
Test name
Test status
Simulation time 600407709 ps
CPU time 2.15 seconds
Started Aug 25 05:58:11 AM UTC 24
Finished Aug 25 05:58:14 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262795
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.1262795864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1505273529
Short name T391
Test name
Test status
Simulation time 5339390990 ps
CPU time 4.94 seconds
Started Aug 25 05:58:24 AM UTC 24
Finished Aug 25 05:58:30 AM UTC 24
Peak memory 226644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505273
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark
s_acq.1505273529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1472685748
Short name T187
Test name
Test status
Simulation time 764467984 ps
CPU time 1.86 seconds
Started Aug 25 05:58:26 AM UTC 24
Finished Aug 25 05:58:30 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472685
748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_tx.1472685748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_hrst.1132475933
Short name T197
Test name
Test status
Simulation time 1221047643 ps
CPU time 3.39 seconds
Started Aug 25 05:58:19 AM UTC 24
Finished Aug 25 05:58:24 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132475
933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.1132475933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.2558409510
Short name T385
Test name
Test status
Simulation time 5410300141 ps
CPU time 10.45 seconds
Started Aug 25 05:58:06 AM UTC 24
Finished Aug 25 05:58:18 AM UTC 24
Peak memory 233148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255840
9510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.2558409510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.236870858
Short name T57
Test name
Test status
Simulation time 23551563039 ps
CPU time 93.87 seconds
Started Aug 25 05:58:06 AM UTC 24
Finished Aug 25 05:59:42 AM UTC 24
Peak memory 1114420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=236870858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.236870858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.3642290717
Short name T395
Test name
Test status
Simulation time 1964464069 ps
CPU time 4.74 seconds
Started Aug 25 05:58:29 AM UTC 24
Finished Aug 25 05:58:35 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642290
717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.3642290717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.4186293526
Short name T188
Test name
Test status
Simulation time 195596041 ps
CPU time 2.74 seconds
Started Aug 25 05:58:30 AM UTC 24
Finished Aug 25 05:58:34 AM UTC 24
Peak memory 233408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186293
526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.4186293526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_perf.2658700640
Short name T388
Test name
Test status
Simulation time 3496985026 ps
CPU time 8.87 seconds
Started Aug 25 05:58:15 AM UTC 24
Finished Aug 25 05:58:25 AM UTC 24
Peak memory 233336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658700
640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.2658700640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2995069567
Short name T393
Test name
Test status
Simulation time 430594315 ps
CPU time 3.53 seconds
Started Aug 25 05:58:29 AM UTC 24
Finished Aug 25 05:58:34 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995069
567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.2995069567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1353473737
Short name T87
Test name
Test status
Simulation time 4712352528 ps
CPU time 41.65 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 05:58:45 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353473737 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.1353473737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.53256114
Short name T256
Test name
Test status
Simulation time 29966215444 ps
CPU time 61.65 seconds
Started Aug 25 05:58:15 AM UTC 24
Finished Aug 25 05:59:18 AM UTC 24
Peak memory 249956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532561
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.53256114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.2420750337
Short name T128
Test name
Test status
Simulation time 947803628 ps
CPU time 50.35 seconds
Started Aug 25 05:58:04 AM UTC 24
Finished Aug 25 05:58:56 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420750337 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.2420750337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.2558406438
Short name T690
Test name
Test status
Simulation time 56607247318 ps
CPU time 490.51 seconds
Started Aug 25 05:58:02 AM UTC 24
Finished Aug 25 06:06:20 AM UTC 24
Peak memory 4575648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558406438 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.2558406438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.629037370
Short name T387
Test name
Test status
Simulation time 1386370359 ps
CPU time 11.48 seconds
Started Aug 25 05:58:06 AM UTC 24
Finished Aug 25 05:58:19 AM UTC 24
Peak memory 230856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6290373
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.629037370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.3760397556
Short name T96
Test name
Test status
Simulation time 1000543599 ps
CPU time 21.23 seconds
Started Aug 25 05:58:26 AM UTC 24
Finished Aug 25 05:58:49 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760397
556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.3760397556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_alert_test.3571920985
Short name T158
Test name
Test status
Simulation time 63425488 ps
CPU time 0.96 seconds
Started Aug 25 05:59:03 AM UTC 24
Finished Aug 25 05:59:05 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571920985 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3571920985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.1530095358
Short name T95
Test name
Test status
Simulation time 119766721 ps
CPU time 5.63 seconds
Started Aug 25 05:58:41 AM UTC 24
Finished Aug 25 05:58:48 AM UTC 24
Peak memory 243900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530095358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1530095358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.3598091684
Short name T398
Test name
Test status
Simulation time 365441672 ps
CPU time 7.35 seconds
Started Aug 25 05:58:34 AM UTC 24
Finished Aug 25 05:58:43 AM UTC 24
Peak memory 284704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598091684 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.3598091684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.3101822786
Short name T440
Test name
Test status
Simulation time 1802352093 ps
CPU time 80.93 seconds
Started Aug 25 05:58:34 AM UTC 24
Finished Aug 25 05:59:58 AM UTC 24
Peak memory 653340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101822786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3101822786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.2904545134
Short name T429
Test name
Test status
Simulation time 2126019611 ps
CPU time 66.69 seconds
Started Aug 25 05:58:33 AM UTC 24
Finished Aug 25 05:59:42 AM UTC 24
Peak memory 350288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904545134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2904545134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2324705070
Short name T260
Test name
Test status
Simulation time 198759948 ps
CPU time 1.47 seconds
Started Aug 25 05:58:33 AM UTC 24
Finished Aug 25 05:58:36 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324705070 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.2324705070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.3028742971
Short name T396
Test name
Test status
Simulation time 128275712 ps
CPU time 4.02 seconds
Started Aug 25 05:58:34 AM UTC 24
Finished Aug 25 05:58:40 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028742971 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.3028742971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.2070974721
Short name T513
Test name
Test status
Simulation time 2891815436 ps
CPU time 194.96 seconds
Started Aug 25 05:58:31 AM UTC 24
Finished Aug 25 06:01:50 AM UTC 24
Peak memory 923804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070974721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2070974721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.3876259677
Short name T274
Test name
Test status
Simulation time 2222427697 ps
CPU time 12.32 seconds
Started Aug 25 05:58:58 AM UTC 24
Finished Aug 25 05:59:12 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876259677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3876259677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_override.1147686683
Short name T394
Test name
Test status
Simulation time 22438476 ps
CPU time 1.08 seconds
Started Aug 25 05:58:31 AM UTC 24
Finished Aug 25 05:58:34 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147686683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1147686683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_perf.3727170754
Short name T40
Test name
Test status
Simulation time 12258466824 ps
CPU time 565.27 seconds
Started Aug 25 05:58:36 AM UTC 24
Finished Aug 25 06:08:10 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727170754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3727170754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.2240002596
Short name T17
Test name
Test status
Simulation time 2463193268 ps
CPU time 35.5 seconds
Started Aug 25 05:58:36 AM UTC 24
Finished Aug 25 05:59:13 AM UTC 24
Peak memory 239240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240002596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2240002596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.1404656135
Short name T154
Test name
Test status
Simulation time 1077607084 ps
CPU time 57.89 seconds
Started Aug 25 05:58:31 AM UTC 24
Finished Aug 25 05:59:31 AM UTC 24
Peak memory 303120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404656135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1404656135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.763260005
Short name T405
Test name
Test status
Simulation time 689302356 ps
CPU time 37.41 seconds
Started Aug 25 05:58:37 AM UTC 24
Finished Aug 25 05:59:16 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763260005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.763260005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.3045149557
Short name T131
Test name
Test status
Simulation time 424597770 ps
CPU time 4.77 seconds
Started Aug 25 05:58:52 AM UTC 24
Finished Aug 25 05:58:58 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3045149557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3045149557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.4147616948
Short name T98
Test name
Test status
Simulation time 574119606 ps
CPU time 1.36 seconds
Started Aug 25 05:58:49 AM UTC 24
Finished Aug 25 05:58:51 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147616
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.4147616948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.1106683522
Short name T126
Test name
Test status
Simulation time 340233555 ps
CPU time 2.17 seconds
Started Aug 25 05:58:50 AM UTC 24
Finished Aug 25 05:58:53 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106683
522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.1106683522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.2705466916
Short name T390
Test name
Test status
Simulation time 511618331 ps
CPU time 5.21 seconds
Started Aug 25 05:58:58 AM UTC 24
Finished Aug 25 05:59:05 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705466
916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark
s_acq.2705466916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.1823252709
Short name T93
Test name
Test status
Simulation time 650461439 ps
CPU time 2.13 seconds
Started Aug 25 05:58:58 AM UTC 24
Finished Aug 25 05:59:02 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823252
709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_tx.1823252709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.2214499276
Short name T130
Test name
Test status
Simulation time 999958732 ps
CPU time 3.76 seconds
Started Aug 25 05:58:53 AM UTC 24
Finished Aug 25 05:58:58 AM UTC 24
Peak memory 233468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214499
276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.2214499276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.3985586297
Short name T401
Test name
Test status
Simulation time 7890035005 ps
CPU time 12.6 seconds
Started Aug 25 05:58:47 AM UTC 24
Finished Aug 25 05:59:01 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398558
6297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.3985586297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.1857393162
Short name T55
Test name
Test status
Simulation time 14872522982 ps
CPU time 13.44 seconds
Started Aug 25 05:58:48 AM UTC 24
Finished Aug 25 05:59:03 AM UTC 24
Peak memory 248248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1857393162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress
_wr.1857393162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.2947228213
Short name T94
Test name
Test status
Simulation time 480384596 ps
CPU time 3.75 seconds
Started Aug 25 05:59:00 AM UTC 24
Finished Aug 25 05:59:05 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947228
213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.2947228213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.2669559345
Short name T403
Test name
Test status
Simulation time 492489697 ps
CPU time 4.14 seconds
Started Aug 25 05:59:02 AM UTC 24
Finished Aug 25 05:59:07 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669559
345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.2669559345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.815143935
Short name T186
Test name
Test status
Simulation time 280791640 ps
CPU time 1.97 seconds
Started Aug 25 05:59:02 AM UTC 24
Finished Aug 25 05:59:05 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8151439
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_txstretch.815143935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_perf.1934452240
Short name T400
Test name
Test status
Simulation time 6680738436 ps
CPU time 7.64 seconds
Started Aug 25 05:58:52 AM UTC 24
Finished Aug 25 05:59:00 AM UTC 24
Peak memory 231108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934452
240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.1934452240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.1136663141
Short name T402
Test name
Test status
Simulation time 566324994 ps
CPU time 5.06 seconds
Started Aug 25 05:59:00 AM UTC 24
Finished Aug 25 05:59:07 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136663
141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.1136663141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.1744491566
Short name T129
Test name
Test status
Simulation time 5820266882 ps
CPU time 14.12 seconds
Started Aug 25 05:58:42 AM UTC 24
Finished Aug 25 05:58:57 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744491566 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.1744491566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.3142700031
Short name T1597
Test name
Test status
Simulation time 55409067221 ps
CPU time 1696.77 seconds
Started Aug 25 05:58:52 AM UTC 24
Finished Aug 25 06:27:28 AM UTC 24
Peak memory 10531108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314270
0031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.3142700031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.542007178
Short name T452
Test name
Test status
Simulation time 5365404558 ps
CPU time 84.33 seconds
Started Aug 25 05:58:44 AM UTC 24
Finished Aug 25 06:00:11 AM UTC 24
Peak memory 228984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542007178 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.542007178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.3505471790
Short name T56
Test name
Test status
Simulation time 53518593182 ps
CPU time 29.14 seconds
Started Aug 25 05:58:44 AM UTC 24
Finished Aug 25 05:59:15 AM UTC 24
Peak memory 457100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505471790 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.3505471790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.2492495582
Short name T404
Test name
Test status
Simulation time 2438878210 ps
CPU time 22.28 seconds
Started Aug 25 05:58:46 AM UTC 24
Finished Aug 25 05:59:10 AM UTC 24
Peak memory 487640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492495582 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.2492495582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.3634810639
Short name T399
Test name
Test status
Simulation time 2461557925 ps
CPU time 10.08 seconds
Started Aug 25 05:58:48 AM UTC 24
Finished Aug 25 05:59:00 AM UTC 24
Peak memory 233292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634810
639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.3634810639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.2729290439
Short name T377
Test name
Test status
Simulation time 129310749 ps
CPU time 4.57 seconds
Started Aug 25 05:58:59 AM UTC 24
Finished Aug 25 05:59:05 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729290
439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2729290439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_alert_test.3156497745
Short name T425
Test name
Test status
Simulation time 37908415 ps
CPU time 0.92 seconds
Started Aug 25 05:59:38 AM UTC 24
Finished Aug 25 05:59:40 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156497745 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3156497745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.646408972
Short name T31
Test name
Test status
Simulation time 151714396 ps
CPU time 2.71 seconds
Started Aug 25 05:59:12 AM UTC 24
Finished Aug 25 05:59:15 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646408972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.646408972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.3294523549
Short name T406
Test name
Test status
Simulation time 696934279 ps
CPU time 10.18 seconds
Started Aug 25 05:59:06 AM UTC 24
Finished Aug 25 05:59:18 AM UTC 24
Peak memory 276816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294523549 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.3294523549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.446808535
Short name T555
Test name
Test status
Simulation time 4181568898 ps
CPU time 226.23 seconds
Started Aug 25 05:59:07 AM UTC 24
Finished Aug 25 06:02:57 AM UTC 24
Peak memory 514288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446808535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.446808535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.1243858333
Short name T447
Test name
Test status
Simulation time 9338473329 ps
CPU time 56.4 seconds
Started Aug 25 05:59:06 AM UTC 24
Finished Aug 25 06:00:04 AM UTC 24
Peak memory 586192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243858333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1243858333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.540986416
Short name T375
Test name
Test status
Simulation time 149617733 ps
CPU time 1.73 seconds
Started Aug 25 05:59:06 AM UTC 24
Finished Aug 25 05:59:09 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540986416 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.540986416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.245109521
Short name T408
Test name
Test status
Simulation time 304188966 ps
CPU time 14.96 seconds
Started Aug 25 05:59:07 AM UTC 24
Finished Aug 25 05:59:23 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245109521 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.245109521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.1895332014
Short name T497
Test name
Test status
Simulation time 4509937000 ps
CPU time 142.23 seconds
Started Aug 25 05:59:06 AM UTC 24
Finished Aug 25 06:01:31 AM UTC 24
Peak memory 1356156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895332014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1895332014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.2998024522
Short name T438
Test name
Test status
Simulation time 1628956162 ps
CPU time 22.74 seconds
Started Aug 25 05:59:31 AM UTC 24
Finished Aug 25 05:59:55 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998024522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2998024522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.1740562140
Short name T288
Test name
Test status
Simulation time 130994944 ps
CPU time 3.2 seconds
Started Aug 25 05:59:29 AM UTC 24
Finished Aug 25 05:59:33 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740562140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1740562140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_override.2883152326
Short name T145
Test name
Test status
Simulation time 20573080 ps
CPU time 1.05 seconds
Started Aug 25 05:59:06 AM UTC 24
Finished Aug 25 05:59:08 AM UTC 24
Peak memory 214304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883152326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2883152326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_perf.62913798
Short name T597
Test name
Test status
Simulation time 28695235936 ps
CPU time 289.82 seconds
Started Aug 25 05:59:09 AM UTC 24
Finished Aug 25 06:04:04 AM UTC 24
Peak memory 299284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62913798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.62913798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.4176765714
Short name T418
Test name
Test status
Simulation time 477756332 ps
CPU time 23.39 seconds
Started Aug 25 05:59:09 AM UTC 24
Finished Aug 25 05:59:34 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176765714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.4176765714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.2784245116
Short name T432
Test name
Test status
Simulation time 14161223976 ps
CPU time 39.57 seconds
Started Aug 25 05:59:04 AM UTC 24
Finished Aug 25 05:59:45 AM UTC 24
Peak memory 329884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784245116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2784245116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.3819833884
Short name T409
Test name
Test status
Simulation time 3217004883 ps
CPU time 12.63 seconds
Started Aug 25 05:59:10 AM UTC 24
Finished Aug 25 05:59:24 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819833884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3819833884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.3210390064
Short name T422
Test name
Test status
Simulation time 1732422941 ps
CPU time 8.67 seconds
Started Aug 25 05:59:27 AM UTC 24
Finished Aug 25 05:59:36 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3210390064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3210390064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.3289866343
Short name T412
Test name
Test status
Simulation time 144338587 ps
CPU time 1.42 seconds
Started Aug 25 05:59:24 AM UTC 24
Finished Aug 25 05:59:27 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289866
343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.3289866343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.3309435344
Short name T414
Test name
Test status
Simulation time 507791280 ps
CPU time 1.7 seconds
Started Aug 25 05:59:24 AM UTC 24
Finished Aug 25 05:59:27 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309435
344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.3309435344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.1970198157
Short name T423
Test name
Test status
Simulation time 502620338 ps
CPU time 5.24 seconds
Started Aug 25 05:59:32 AM UTC 24
Finished Aug 25 05:59:38 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970198
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermark
s_acq.1970198157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.72413989
Short name T420
Test name
Test status
Simulation time 198350457 ps
CPU time 1.28 seconds
Started Aug 25 05:59:33 AM UTC 24
Finished Aug 25 05:59:35 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7241398
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.72413989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.3955051953
Short name T415
Test name
Test status
Simulation time 3518971908 ps
CPU time 9.14 seconds
Started Aug 25 05:59:18 AM UTC 24
Finished Aug 25 05:59:28 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395505
1953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.3955051953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.1659387446
Short name T417
Test name
Test status
Simulation time 9037941922 ps
CPU time 12.13 seconds
Started Aug 25 05:59:19 AM UTC 24
Finished Aug 25 05:59:32 AM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1659387446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.1659387446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.2808621283
Short name T430
Test name
Test status
Simulation time 5450234229 ps
CPU time 5.05 seconds
Started Aug 25 05:59:36 AM UTC 24
Finished Aug 25 05:59:43 AM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808621
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.2808621283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.279773947
Short name T428
Test name
Test status
Simulation time 871321986 ps
CPU time 4.17 seconds
Started Aug 25 05:59:36 AM UTC 24
Finished Aug 25 05:59:42 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797739
47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.279773947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.2924337117
Short name T189
Test name
Test status
Simulation time 144946504 ps
CPU time 2.27 seconds
Started Aug 25 05:59:37 AM UTC 24
Finished Aug 25 05:59:40 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924337
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.2924337117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_perf.4259487782
Short name T419
Test name
Test status
Simulation time 2536763708 ps
CPU time 8.48 seconds
Started Aug 25 05:59:25 AM UTC 24
Finished Aug 25 05:59:35 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259487
782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.4259487782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.2090510366
Short name T424
Test name
Test status
Simulation time 460061930 ps
CPU time 3.34 seconds
Started Aug 25 05:59:35 AM UTC 24
Finished Aug 25 05:59:40 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090510
366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.2090510366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.276423588
Short name T436
Test name
Test status
Simulation time 3984071394 ps
CPU time 37.91 seconds
Started Aug 25 05:59:14 AM UTC 24
Finished Aug 25 05:59:53 AM UTC 24
Peak memory 233880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276423588 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.276423588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.1101726086
Short name T485
Test name
Test status
Simulation time 31729011054 ps
CPU time 87.23 seconds
Started Aug 25 05:59:26 AM UTC 24
Finished Aug 25 06:00:55 AM UTC 24
Peak memory 620744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110172
6086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.1101726086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.2400753880
Short name T444
Test name
Test status
Simulation time 9190124072 ps
CPU time 42.48 seconds
Started Aug 25 05:59:16 AM UTC 24
Finished Aug 25 06:00:00 AM UTC 24
Peak memory 250136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400753880 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.2400753880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.2892029915
Short name T421
Test name
Test status
Simulation time 7920365837 ps
CPU time 19.14 seconds
Started Aug 25 05:59:16 AM UTC 24
Finished Aug 25 05:59:36 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892029915 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.2892029915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.475644824
Short name T410
Test name
Test status
Simulation time 1072747309 ps
CPU time 6.98 seconds
Started Aug 25 05:59:17 AM UTC 24
Finished Aug 25 05:59:25 AM UTC 24
Peak memory 288860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475644824 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.475644824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.4228632319
Short name T416
Test name
Test status
Simulation time 10318139310 ps
CPU time 9.9 seconds
Started Aug 25 05:59:19 AM UTC 24
Finished Aug 25 05:59:30 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228632
319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.4228632319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.275639479
Short name T427
Test name
Test status
Simulation time 157887475 ps
CPU time 6.34 seconds
Started Aug 25 05:59:34 AM UTC 24
Finished Aug 25 05:59:42 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756394
79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.275639479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_alert_test.1284065714
Short name T459
Test name
Test status
Simulation time 38129667 ps
CPU time 0.9 seconds
Started Aug 25 06:00:13 AM UTC 24
Finished Aug 25 06:00:15 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284065714 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1284065714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.2287627481
Short name T435
Test name
Test status
Simulation time 684086244 ps
CPU time 6.05 seconds
Started Aug 25 05:59:43 AM UTC 24
Finished Aug 25 05:59:51 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287627481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2287627481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.3773746858
Short name T434
Test name
Test status
Simulation time 611849343 ps
CPU time 5.05 seconds
Started Aug 25 05:59:41 AM UTC 24
Finished Aug 25 05:59:47 AM UTC 24
Peak memory 241864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773746858 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.3773746858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.2991596250
Short name T536
Test name
Test status
Simulation time 3828630181 ps
CPU time 164.56 seconds
Started Aug 25 05:59:42 AM UTC 24
Finished Aug 25 06:02:30 AM UTC 24
Peak memory 893124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991596250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2991596250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1580885505
Short name T140
Test name
Test status
Simulation time 15331798726 ps
CPU time 96.51 seconds
Started Aug 25 05:59:41 AM UTC 24
Finished Aug 25 06:01:20 AM UTC 24
Peak memory 748044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580885505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1580885505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.3738217998
Short name T431
Test name
Test status
Simulation time 266731176 ps
CPU time 1.85 seconds
Started Aug 25 05:59:41 AM UTC 24
Finished Aug 25 05:59:44 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738217998 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.3738217998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.3494124475
Short name T437
Test name
Test status
Simulation time 333366039 ps
CPU time 10.96 seconds
Started Aug 25 05:59:42 AM UTC 24
Finished Aug 25 05:59:54 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494124475 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.3494124475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.1575255404
Short name T136
Test name
Test status
Simulation time 6274563164 ps
CPU time 90.08 seconds
Started Aug 25 05:59:40 AM UTC 24
Finished Aug 25 06:01:12 AM UTC 24
Peak memory 954532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575255404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1575255404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.1469641726
Short name T279
Test name
Test status
Simulation time 241102046 ps
CPU time 13.49 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:24 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469641726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1469641726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_mode_toggle.1628981726
Short name T79
Test name
Test status
Simulation time 127759095 ps
CPU time 2.64 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:13 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628981726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1628981726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_override.2046502674
Short name T426
Test name
Test status
Simulation time 110145014 ps
CPU time 0.97 seconds
Started Aug 25 05:59:39 AM UTC 24
Finished Aug 25 05:59:41 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046502674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2046502674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_perf.124702073
Short name T498
Test name
Test status
Simulation time 4967155106 ps
CPU time 107.78 seconds
Started Aug 25 05:59:42 AM UTC 24
Finished Aug 25 06:01:33 AM UTC 24
Peak memory 430536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124702073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.124702073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.3739533691
Short name T661
Test name
Test status
Simulation time 23170691529 ps
CPU time 354.82 seconds
Started Aug 25 05:59:43 AM UTC 24
Finished Aug 25 06:05:44 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739533691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.3739533691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.33123900
Short name T445
Test name
Test status
Simulation time 2251625212 ps
CPU time 23.78 seconds
Started Aug 25 05:59:38 AM UTC 24
Finished Aug 25 06:00:03 AM UTC 24
Peak memory 283036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33123900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.33123900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1926913732
Short name T468
Test name
Test status
Simulation time 818223036 ps
CPU time 45.88 seconds
Started Aug 25 05:59:43 AM UTC 24
Finished Aug 25 06:00:32 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926913732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1926913732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.4141024467
Short name T462
Test name
Test status
Simulation time 1305616699 ps
CPU time 9.89 seconds
Started Aug 25 06:00:00 AM UTC 24
Finished Aug 25 06:00:17 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4141024467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.4141024467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.3945393862
Short name T443
Test name
Test status
Simulation time 1429823330 ps
CPU time 2.85 seconds
Started Aug 25 05:59:56 AM UTC 24
Finished Aug 25 06:00:00 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945393
862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.3945393862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.2655786567
Short name T442
Test name
Test status
Simulation time 926489824 ps
CPU time 1.35 seconds
Started Aug 25 05:59:57 AM UTC 24
Finished Aug 25 06:00:00 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655786
567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.2655786567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.582271914
Short name T454
Test name
Test status
Simulation time 160500058 ps
CPU time 1.73 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:12 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5822719
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_acq.582271914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.2790504939
Short name T453
Test name
Test status
Simulation time 118437892 ps
CPU time 1.72 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:12 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790504
939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_tx.2790504939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.2252647776
Short name T448
Test name
Test status
Simulation time 1299554706 ps
CPU time 11.94 seconds
Started Aug 25 05:59:52 AM UTC 24
Finished Aug 25 06:00:05 AM UTC 24
Peak memory 233604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225264
7776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.2252647776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.2461271593
Short name T451
Test name
Test status
Simulation time 12637318381 ps
CPU time 14.68 seconds
Started Aug 25 05:59:54 AM UTC 24
Finished Aug 25 06:00:10 AM UTC 24
Peak memory 309380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2461271593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress
_wr.2461271593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.90768120
Short name T461
Test name
Test status
Simulation time 5542036051 ps
CPU time 4.48 seconds
Started Aug 25 06:00:11 AM UTC 24
Finished Aug 25 06:00:17 AM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9076812
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.90768120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.2364902774
Short name T465
Test name
Test status
Simulation time 1230515460 ps
CPU time 6.2 seconds
Started Aug 25 06:00:11 AM UTC 24
Finished Aug 25 06:00:18 AM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364902
774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.2364902774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.2334815500
Short name T458
Test name
Test status
Simulation time 1989909902 ps
CPU time 2.63 seconds
Started Aug 25 06:00:11 AM UTC 24
Finished Aug 25 06:00:15 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334815
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.2334815500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_perf.975905325
Short name T450
Test name
Test status
Simulation time 510379289 ps
CPU time 6.77 seconds
Started Aug 25 05:59:59 AM UTC 24
Finished Aug 25 06:00:07 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9759053
25 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.975905325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.3661360588
Short name T457
Test name
Test status
Simulation time 1109834339 ps
CPU time 3.86 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:15 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661360
588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.3661360588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.3094017631
Short name T446
Test name
Test status
Simulation time 1495481693 ps
CPU time 16.24 seconds
Started Aug 25 05:59:45 AM UTC 24
Finished Aug 25 06:00:03 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094017631 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.3094017631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.19428665
Short name T776
Test name
Test status
Simulation time 24118967828 ps
CPU time 486.39 seconds
Started Aug 25 06:00:00 AM UTC 24
Finished Aug 25 06:08:19 AM UTC 24
Peak memory 4983216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194286
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.19428665
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.2650742976
Short name T456
Test name
Test status
Simulation time 1882499778 ps
CPU time 24.07 seconds
Started Aug 25 05:59:48 AM UTC 24
Finished Aug 25 06:00:13 AM UTC 24
Peak memory 233256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650742976 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.2650742976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.3195196712
Short name T658
Test name
Test status
Simulation time 45158174584 ps
CPU time 345.24 seconds
Started Aug 25 05:59:48 AM UTC 24
Finished Aug 25 06:05:38 AM UTC 24
Peak memory 3637660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195196712 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.3195196712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.1667161648
Short name T439
Test name
Test status
Simulation time 2093002546 ps
CPU time 6.76 seconds
Started Aug 25 05:59:48 AM UTC 24
Finished Aug 25 05:59:56 AM UTC 24
Peak memory 268376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667161648 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.1667161648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.400713351
Short name T449
Test name
Test status
Simulation time 1893553355 ps
CPU time 8.82 seconds
Started Aug 25 05:59:55 AM UTC 24
Finished Aug 25 06:00:05 AM UTC 24
Peak memory 231168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007133
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.400713351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.359948092
Short name T464
Test name
Test status
Simulation time 207674321 ps
CPU time 7.28 seconds
Started Aug 25 06:00:09 AM UTC 24
Finished Aug 25 06:00:18 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599480
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.359948092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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