| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.3052042612 |
|
|
Aug 27 07:28:05 AM UTC 24 |
Aug 27 07:29:18 AM UTC 24 |
9585667057 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.1678875547 |
|
|
Aug 27 07:28:58 AM UTC 24 |
Aug 27 07:29:20 AM UTC 24 |
1270861001 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.354073232 |
|
|
Aug 27 07:29:17 AM UTC 24 |
Aug 27 07:29:32 AM UTC 24 |
1048154365 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.3543496265 |
|
|
Aug 27 07:29:36 AM UTC 24 |
Aug 27 07:29:39 AM UTC 24 |
282253343 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.1087418052 |
|
|
Aug 27 07:29:27 AM UTC 24 |
Aug 27 07:29:41 AM UTC 24 |
12206497270 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.3952619256 |
|
|
Aug 27 07:29:11 AM UTC 24 |
Aug 27 07:29:42 AM UTC 24 |
1174721021 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.1184163080 |
|
|
Aug 27 07:29:40 AM UTC 24 |
Aug 27 07:29:42 AM UTC 24 |
148999656 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.3036671629 |
|
|
Aug 27 07:28:07 AM UTC 24 |
Aug 27 07:29:43 AM UTC 24 |
3695716126 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.2926884355 |
|
|
Aug 27 07:29:33 AM UTC 24 |
Aug 27 07:29:44 AM UTC 24 |
2002323698 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.690359120 |
|
|
Aug 27 07:29:43 AM UTC 24 |
Aug 27 07:29:47 AM UTC 24 |
113787948 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.330064625 |
|
|
Aug 27 07:26:07 AM UTC 24 |
Aug 27 07:29:47 AM UTC 24 |
14317006640 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1613662309 |
|
|
Aug 27 07:29:02 AM UTC 24 |
Aug 27 07:29:47 AM UTC 24 |
5782752191 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3647392165 |
|
|
Aug 27 07:29:21 AM UTC 24 |
Aug 27 07:29:47 AM UTC 24 |
1237384283 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.270562324 |
|
|
Aug 27 07:29:43 AM UTC 24 |
Aug 27 07:29:48 AM UTC 24 |
1218263323 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1562615349 |
|
|
Aug 27 07:29:44 AM UTC 24 |
Aug 27 07:29:48 AM UTC 24 |
223746208 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.674506859 |
|
|
Aug 27 07:27:25 AM UTC 24 |
Aug 27 07:29:48 AM UTC 24 |
10948051752 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1748432091 |
|
|
Aug 27 07:29:44 AM UTC 24 |
Aug 27 07:29:49 AM UTC 24 |
756757207 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_perf.4045255257 |
|
|
Aug 27 07:29:40 AM UTC 24 |
Aug 27 07:29:50 AM UTC 24 |
1875646770 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1810188230 |
|
|
Aug 27 07:29:49 AM UTC 24 |
Aug 27 07:29:51 AM UTC 24 |
31722147 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.578695228 |
|
|
Aug 27 07:29:43 AM UTC 24 |
Aug 27 07:29:51 AM UTC 24 |
1633511788 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.227705185 |
|
|
Aug 27 07:29:49 AM UTC 24 |
Aug 27 07:29:52 AM UTC 24 |
132743311 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_override.199006067 |
|
|
Aug 27 07:29:50 AM UTC 24 |
Aug 27 07:29:52 AM UTC 24 |
47914893 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.673461950 |
|
|
Aug 27 07:29:47 AM UTC 24 |
Aug 27 07:29:52 AM UTC 24 |
5151451849 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.569988944 |
|
|
Aug 27 07:29:47 AM UTC 24 |
Aug 27 07:29:52 AM UTC 24 |
554031454 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2952585635 |
|
|
Aug 27 07:29:47 AM UTC 24 |
Aug 27 07:29:54 AM UTC 24 |
164310717 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.3520534449 |
|
|
Aug 27 07:29:52 AM UTC 24 |
Aug 27 07:29:54 AM UTC 24 |
398609033 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3645866867 |
|
|
Aug 27 07:29:49 AM UTC 24 |
Aug 27 07:29:55 AM UTC 24 |
935973429 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.765409615 |
|
|
Aug 27 07:29:44 AM UTC 24 |
Aug 27 07:29:57 AM UTC 24 |
5070748705 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.2615021521 |
|
|
Aug 27 07:27:25 AM UTC 24 |
Aug 27 07:29:58 AM UTC 24 |
6490635442 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2747533178 |
|
|
Aug 27 07:29:53 AM UTC 24 |
Aug 27 07:30:00 AM UTC 24 |
529473541 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_perf.222573754 |
|
|
Aug 27 07:29:53 AM UTC 24 |
Aug 27 07:30:01 AM UTC 24 |
1080255301 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3790980785 |
|
|
Aug 27 07:21:46 AM UTC 24 |
Aug 27 07:30:05 AM UTC 24 |
24902362591 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.2154171259 |
|
|
Aug 27 07:28:55 AM UTC 24 |
Aug 27 07:30:06 AM UTC 24 |
5876677318 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2163479036 |
|
|
Aug 27 07:29:52 AM UTC 24 |
Aug 27 07:30:06 AM UTC 24 |
584775960 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.750638654 |
|
|
Aug 27 07:30:01 AM UTC 24 |
Aug 27 07:30:11 AM UTC 24 |
8491082658 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.332956633 |
|
|
Aug 27 07:29:56 AM UTC 24 |
Aug 27 07:30:11 AM UTC 24 |
303991491 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_perf.2169809702 |
|
|
Aug 27 07:28:07 AM UTC 24 |
Aug 27 07:30:12 AM UTC 24 |
12824610395 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.384488896 |
|
|
Aug 27 07:30:12 AM UTC 24 |
Aug 27 07:30:16 AM UTC 24 |
182756977 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.4156629310 |
|
|
Aug 27 07:29:59 AM UTC 24 |
Aug 27 07:30:18 AM UTC 24 |
3734730664 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1733215308 |
|
|
Aug 27 07:30:16 AM UTC 24 |
Aug 27 07:30:18 AM UTC 24 |
185523977 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3760078242 |
|
|
Aug 27 07:30:07 AM UTC 24 |
Aug 27 07:30:19 AM UTC 24 |
1227162675 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3433027756 |
|
|
Aug 27 07:30:17 AM UTC 24 |
Aug 27 07:30:23 AM UTC 24 |
408672798 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.2509888825 |
|
|
Aug 27 07:28:57 AM UTC 24 |
Aug 27 07:30:24 AM UTC 24 |
3971197738 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1893789692 |
|
|
Aug 27 07:30:12 AM UTC 24 |
Aug 27 07:30:24 AM UTC 24 |
5756335004 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2991042300 |
|
|
Aug 27 07:30:20 AM UTC 24 |
Aug 27 07:30:26 AM UTC 24 |
419150631 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2957932656 |
|
|
Aug 27 07:30:19 AM UTC 24 |
Aug 27 07:30:29 AM UTC 24 |
2833861199 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2608808798 |
|
|
Aug 27 07:30:27 AM UTC 24 |
Aug 27 07:30:30 AM UTC 24 |
135439694 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3350423301 |
|
|
Aug 27 07:30:25 AM UTC 24 |
Aug 27 07:30:30 AM UTC 24 |
448525556 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2042292726 |
|
|
Aug 27 07:29:56 AM UTC 24 |
Aug 27 07:30:31 AM UTC 24 |
606908738 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.2728900272 |
|
|
Aug 27 07:30:28 AM UTC 24 |
Aug 27 07:30:33 AM UTC 24 |
79227091 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.4270691041 |
|
|
Aug 27 07:30:30 AM UTC 24 |
Aug 27 07:30:35 AM UTC 24 |
759966476 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.183099987 |
|
|
Aug 27 07:31:18 AM UTC 24 |
Aug 27 07:31:30 AM UTC 24 |
6516203836 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1953014185 |
|
|
Aug 27 07:30:31 AM UTC 24 |
Aug 27 07:30:35 AM UTC 24 |
518767477 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.377403349 |
|
|
Aug 27 07:30:25 AM UTC 24 |
Aug 27 07:30:36 AM UTC 24 |
2693443888 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2775832775 |
|
|
Aug 27 07:30:34 AM UTC 24 |
Aug 27 07:30:36 AM UTC 24 |
44367063 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2213778261 |
|
|
Aug 27 07:30:32 AM UTC 24 |
Aug 27 07:30:37 AM UTC 24 |
473247291 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_override.385992022 |
|
|
Aug 27 07:30:36 AM UTC 24 |
Aug 27 07:30:38 AM UTC 24 |
18552107 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3551812789 |
|
|
Aug 27 07:30:37 AM UTC 24 |
Aug 27 07:30:40 AM UTC 24 |
482143429 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.3080422104 |
|
|
Aug 27 07:30:02 AM UTC 24 |
Aug 27 07:30:43 AM UTC 24 |
12767199067 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1472701455 |
|
|
Aug 27 07:29:19 AM UTC 24 |
Aug 27 07:30:45 AM UTC 24 |
25083105149 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.3648493400 |
|
|
Aug 27 07:10:30 AM UTC 24 |
Aug 27 07:30:46 AM UTC 24 |
62999997878 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.4202743180 |
|
|
Aug 27 07:30:06 AM UTC 24 |
Aug 27 07:30:47 AM UTC 24 |
4100902045 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2231543558 |
|
|
Aug 27 07:30:39 AM UTC 24 |
Aug 27 07:30:47 AM UTC 24 |
715172151 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.640024864 |
|
|
Aug 27 07:30:46 AM UTC 24 |
Aug 27 07:30:48 AM UTC 24 |
44375014 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2551214460 |
|
|
Aug 27 07:30:48 AM UTC 24 |
Aug 27 07:30:52 AM UTC 24 |
380879639 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2363294157 |
|
|
Aug 27 07:30:38 AM UTC 24 |
Aug 27 07:30:55 AM UTC 24 |
1069989949 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_perf.4151364426 |
|
|
Aug 27 07:30:44 AM UTC 24 |
Aug 27 07:31:05 AM UTC 24 |
7155426798 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3521239844 |
|
|
Aug 27 07:30:47 AM UTC 24 |
Aug 27 07:31:10 AM UTC 24 |
9162542024 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3136152779 |
|
|
Aug 27 07:29:52 AM UTC 24 |
Aug 27 07:31:12 AM UTC 24 |
7532519098 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.1161470244 |
|
|
Aug 27 07:30:56 AM UTC 24 |
Aug 27 07:31:16 AM UTC 24 |
362043192 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3104201562 |
|
|
Aug 27 07:30:19 AM UTC 24 |
Aug 27 07:31:17 AM UTC 24 |
27689631334 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.436852135 |
|
|
Aug 27 07:10:16 AM UTC 24 |
Aug 27 07:31:19 AM UTC 24 |
169569519801 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.1230662716 |
|
|
Aug 27 07:09:45 AM UTC 24 |
Aug 27 07:31:20 AM UTC 24 |
59575461437 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2920335169 |
|
|
Aug 27 07:31:11 AM UTC 24 |
Aug 27 07:31:20 AM UTC 24 |
3582265772 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.2409385576 |
|
|
Aug 27 07:30:49 AM UTC 24 |
Aug 27 07:31:21 AM UTC 24 |
983382598 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3328636739 |
|
|
Aug 27 07:31:20 AM UTC 24 |
Aug 27 07:31:22 AM UTC 24 |
154050057 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3675338814 |
|
|
Aug 27 07:31:21 AM UTC 24 |
Aug 27 07:31:23 AM UTC 24 |
165287754 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1004293485 |
|
|
Aug 27 07:29:49 AM UTC 24 |
Aug 27 07:31:26 AM UTC 24 |
1665194938 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2941036089 |
|
|
Aug 27 07:31:22 AM UTC 24 |
Aug 27 07:31:27 AM UTC 24 |
823991183 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4090868725 |
|
|
Aug 27 07:31:21 AM UTC 24 |
Aug 27 07:31:29 AM UTC 24 |
3340942902 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.881159738 |
|
|
Aug 27 07:29:42 AM UTC 24 |
Aug 27 07:31:30 AM UTC 24 |
61731921552 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.603735602 |
|
|
Aug 27 07:31:28 AM UTC 24 |
Aug 27 07:31:32 AM UTC 24 |
443492473 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.527435287 |
|
|
Aug 27 07:31:29 AM UTC 24 |
Aug 27 07:31:33 AM UTC 24 |
570172151 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3862336073 |
|
|
Aug 27 07:31:13 AM UTC 24 |
Aug 27 07:31:34 AM UTC 24 |
18386264244 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.818505144 |
|
|
Aug 27 07:31:32 AM UTC 24 |
Aug 27 07:31:36 AM UTC 24 |
492648275 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_alert_test.3749425135 |
|
|
Aug 27 07:31:35 AM UTC 24 |
Aug 27 07:31:37 AM UTC 24 |
39941415 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3859337329 |
|
|
Aug 27 07:31:35 AM UTC 24 |
Aug 27 07:31:38 AM UTC 24 |
338810022 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3368236049 |
|
|
Aug 27 07:31:31 AM UTC 24 |
Aug 27 07:31:38 AM UTC 24 |
341655892 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1404724157 |
|
|
Aug 27 07:31:33 AM UTC 24 |
Aug 27 07:31:38 AM UTC 24 |
554581230 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_override.3518992156 |
|
|
Aug 27 07:31:37 AM UTC 24 |
Aug 27 07:31:39 AM UTC 24 |
49821886 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1817032470 |
|
|
Aug 27 07:31:34 AM UTC 24 |
Aug 27 07:31:40 AM UTC 24 |
469394892 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.2308588655 |
|
|
Aug 27 07:30:37 AM UTC 24 |
Aug 27 07:31:41 AM UTC 24 |
3095380236 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.4093482310 |
|
|
Aug 27 07:31:39 AM UTC 24 |
Aug 27 07:31:42 AM UTC 24 |
329283120 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.4084847505 |
|
|
Aug 27 07:31:41 AM UTC 24 |
Aug 27 07:31:46 AM UTC 24 |
100275434 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2252227356 |
|
|
Aug 27 07:31:26 AM UTC 24 |
Aug 27 07:31:47 AM UTC 24 |
510944258 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1359757228 |
|
|
Aug 27 07:31:41 AM UTC 24 |
Aug 27 07:31:52 AM UTC 24 |
2816428353 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.3885653485 |
|
|
Aug 27 07:30:36 AM UTC 24 |
Aug 27 07:31:55 AM UTC 24 |
1586449321 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1502414918 |
|
|
Aug 27 07:31:53 AM UTC 24 |
Aug 27 07:31:56 AM UTC 24 |
130829586 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.739141217 |
|
|
Aug 27 07:31:37 AM UTC 24 |
Aug 27 07:31:58 AM UTC 24 |
1355313757 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1045543698 |
|
|
Aug 27 07:31:48 AM UTC 24 |
Aug 27 07:32:00 AM UTC 24 |
434662599 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.2812899139 |
|
|
Aug 27 07:31:05 AM UTC 24 |
Aug 27 07:32:00 AM UTC 24 |
2956123623 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3785024236 |
|
|
Aug 27 07:29:02 AM UTC 24 |
Aug 27 07:32:02 AM UTC 24 |
4782113883 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.3855414259 |
|
|
Aug 27 07:32:02 AM UTC 24 |
Aug 27 07:32:08 AM UTC 24 |
3021681698 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_perf.65025191 |
|
|
Aug 27 07:22:06 AM UTC 24 |
Aug 27 07:32:08 AM UTC 24 |
26376309952 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.112783228 |
|
|
Aug 27 07:32:03 AM UTC 24 |
Aug 27 07:32:10 AM UTC 24 |
911818118 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.4093905143 |
|
|
Aug 27 07:32:12 AM UTC 24 |
Aug 27 07:32:15 AM UTC 24 |
182203307 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1119296106 |
|
|
Aug 27 07:32:14 AM UTC 24 |
Aug 27 07:32:17 AM UTC 24 |
331811930 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.1154135826 |
|
|
Aug 27 07:31:57 AM UTC 24 |
Aug 27 07:32:18 AM UTC 24 |
973741186 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_perf.2438326846 |
|
|
Aug 27 07:27:27 AM UTC 24 |
Aug 27 07:32:19 AM UTC 24 |
72478511029 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.217476408 |
|
|
Aug 27 07:27:48 AM UTC 24 |
Aug 27 07:32:21 AM UTC 24 |
55502507617 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3600680779 |
|
|
Aug 27 07:32:19 AM UTC 24 |
Aug 27 07:32:23 AM UTC 24 |
1188793893 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_perf.93478671 |
|
|
Aug 27 07:32:16 AM UTC 24 |
Aug 27 07:32:24 AM UTC 24 |
1199836777 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3761133132 |
|
|
Aug 27 07:32:18 AM UTC 24 |
Aug 27 07:32:24 AM UTC 24 |
2846622182 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.817699713 |
|
|
Aug 27 07:32:09 AM UTC 24 |
Aug 27 07:32:25 AM UTC 24 |
1457489188 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.3006400490 |
|
|
Aug 27 07:31:47 AM UTC 24 |
Aug 27 07:32:27 AM UTC 24 |
6263051954 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.4140648186 |
|
|
Aug 27 07:32:25 AM UTC 24 |
Aug 27 07:32:28 AM UTC 24 |
610412646 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2188639423 |
|
|
Aug 27 07:32:24 AM UTC 24 |
Aug 27 07:32:30 AM UTC 24 |
324635203 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3885439264 |
|
|
Aug 27 07:32:25 AM UTC 24 |
Aug 27 07:32:30 AM UTC 24 |
456806527 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3542119888 |
|
|
Aug 27 07:32:26 AM UTC 24 |
Aug 27 07:32:31 AM UTC 24 |
1018405730 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3779897273 |
|
|
Aug 27 07:32:31 AM UTC 24 |
Aug 27 07:32:33 AM UTC 24 |
15680742 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.2934233534 |
|
|
Aug 27 07:32:26 AM UTC 24 |
Aug 27 07:32:34 AM UTC 24 |
292775412 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.612792528 |
|
|
Aug 27 07:32:28 AM UTC 24 |
Aug 27 07:32:34 AM UTC 24 |
899360701 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2496302511 |
|
|
Aug 27 07:32:29 AM UTC 24 |
Aug 27 07:32:34 AM UTC 24 |
564972479 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_override.2895734814 |
|
|
Aug 27 07:32:35 AM UTC 24 |
Aug 27 07:32:37 AM UTC 24 |
16135871 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.4280251479 |
|
|
Aug 27 07:32:09 AM UTC 24 |
Aug 27 07:32:37 AM UTC 24 |
13615742432 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2100916384 |
|
|
Aug 27 07:32:35 AM UTC 24 |
Aug 27 07:32:38 AM UTC 24 |
491949780 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2946923623 |
|
|
Aug 27 07:28:18 AM UTC 24 |
Aug 27 07:32:41 AM UTC 24 |
46854152778 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1833976175 |
|
|
Aug 27 07:32:35 AM UTC 24 |
Aug 27 07:32:43 AM UTC 24 |
293751145 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1900652331 |
|
|
Aug 27 07:32:38 AM UTC 24 |
Aug 27 07:32:44 AM UTC 24 |
177933278 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1053451384 |
|
|
Aug 27 07:29:53 AM UTC 24 |
Aug 27 07:32:45 AM UTC 24 |
4197673388 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.3819276250 |
|
|
Aug 27 07:32:45 AM UTC 24 |
Aug 27 07:32:49 AM UTC 24 |
145451589 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3061179492 |
|
|
Aug 27 07:31:39 AM UTC 24 |
Aug 27 07:32:52 AM UTC 24 |
45129798599 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.3459488385 |
|
|
Aug 27 07:27:37 AM UTC 24 |
Aug 27 07:32:54 AM UTC 24 |
35184966337 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_perf.372525888 |
|
|
Aug 27 07:29:02 AM UTC 24 |
Aug 27 07:32:57 AM UTC 24 |
18881364629 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.383677177 |
|
|
Aug 27 07:30:36 AM UTC 24 |
Aug 27 07:32:57 AM UTC 24 |
11300540084 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_perf.179443066 |
|
|
Aug 27 07:32:38 AM UTC 24 |
Aug 27 07:32:59 AM UTC 24 |
14770578520 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2160991267 |
|
|
Aug 27 07:32:44 AM UTC 24 |
Aug 27 07:33:01 AM UTC 24 |
3590381787 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1455445311 |
|
|
Aug 27 07:32:58 AM UTC 24 |
Aug 27 07:33:09 AM UTC 24 |
1017115002 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3223085310 |
|
|
Aug 27 07:32:00 AM UTC 24 |
Aug 27 07:33:11 AM UTC 24 |
1489992874 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.1823981928 |
|
|
Aug 27 07:33:02 AM UTC 24 |
Aug 27 07:33:14 AM UTC 24 |
2177241440 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1335330285 |
|
|
Aug 27 07:33:11 AM UTC 24 |
Aug 27 07:33:15 AM UTC 24 |
168608450 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3980371484 |
|
|
Aug 27 07:32:55 AM UTC 24 |
Aug 27 07:33:16 AM UTC 24 |
882682945 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.196790667 |
|
|
Aug 27 07:33:14 AM UTC 24 |
Aug 27 07:33:17 AM UTC 24 |
258608327 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1728488026 |
|
|
Aug 27 07:32:58 AM UTC 24 |
Aug 27 07:33:18 AM UTC 24 |
1219193409 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2067174630 |
|
|
Aug 27 07:33:19 AM UTC 24 |
Aug 27 07:33:22 AM UTC 24 |
388906973 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1465427815 |
|
|
Aug 27 07:32:17 AM UTC 24 |
Aug 27 07:33:23 AM UTC 24 |
153095892996 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_perf.270233985 |
|
|
Aug 27 07:33:15 AM UTC 24 |
Aug 27 07:33:25 AM UTC 24 |
861200230 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.1553522789 |
|
|
Aug 27 07:31:38 AM UTC 24 |
Aug 27 07:33:25 AM UTC 24 |
15704206086 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1768137704 |
|
|
Aug 27 07:33:28 AM UTC 24 |
Aug 27 07:33:33 AM UTC 24 |
522171537 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.3753788830 |
|
|
Aug 27 07:10:52 AM UTC 24 |
Aug 27 07:33:27 AM UTC 24 |
62210456637 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.4072496250 |
|
|
Aug 27 07:33:25 AM UTC 24 |
Aug 27 07:33:27 AM UTC 24 |
85488840 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.112687109 |
|
|
Aug 27 07:33:17 AM UTC 24 |
Aug 27 07:33:29 AM UTC 24 |
1241605635 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.892116404 |
|
|
Aug 27 07:33:26 AM UTC 24 |
Aug 27 07:33:29 AM UTC 24 |
62090676 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1201530968 |
|
|
Aug 27 07:33:30 AM UTC 24 |
Aug 27 07:33:34 AM UTC 24 |
810618324 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.3886094629 |
|
|
Aug 27 07:33:24 AM UTC 24 |
Aug 27 07:33:30 AM UTC 24 |
1124760114 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.914927803 |
|
|
Aug 27 07:32:52 AM UTC 24 |
Aug 27 07:33:30 AM UTC 24 |
1234630851 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1002500274 |
|
|
Aug 27 07:30:40 AM UTC 24 |
Aug 27 07:33:31 AM UTC 24 |
6648539048 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1436184027 |
|
|
Aug 27 07:31:42 AM UTC 24 |
Aug 27 07:33:31 AM UTC 24 |
1911210183 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.4197081863 |
|
|
Aug 27 07:33:27 AM UTC 24 |
Aug 27 07:33:32 AM UTC 24 |
1874834829 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_alert_test.664362560 |
|
|
Aug 27 07:33:31 AM UTC 24 |
Aug 27 07:33:32 AM UTC 24 |
136546502 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2390848492 |
|
|
Aug 27 07:33:29 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
2048266555 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.154650549 |
|
|
Aug 27 07:21:45 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
44524884936 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2760940251 |
|
|
Aug 27 07:33:23 AM UTC 24 |
Aug 27 07:33:40 AM UTC 24 |
397943456 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3521529464 |
|
|
Aug 27 07:28:40 AM UTC 24 |
Aug 27 07:33:45 AM UTC 24 |
18405110175 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2440628873 |
|
|
Aug 27 07:32:38 AM UTC 24 |
Aug 27 07:33:54 AM UTC 24 |
2282670320 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1532124911 |
|
|
Aug 27 07:24:14 AM UTC 24 |
Aug 27 07:33:56 AM UTC 24 |
28662647113 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.569971375 |
|
|
Aug 27 07:15:01 AM UTC 24 |
Aug 27 07:34:08 AM UTC 24 |
71281940253 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.503069319 |
|
|
Aug 27 07:32:53 AM UTC 24 |
Aug 27 07:34:18 AM UTC 24 |
37615716728 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1576885151 |
|
|
Aug 27 07:32:31 AM UTC 24 |
Aug 27 07:34:20 AM UTC 24 |
8586521471 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3689830853 |
|
|
Aug 27 07:32:42 AM UTC 24 |
Aug 27 07:34:20 AM UTC 24 |
5801775302 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1044324681 |
|
|
Aug 27 07:32:59 AM UTC 24 |
Aug 27 07:34:28 AM UTC 24 |
8309490344 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.521385956 |
|
|
Aug 27 07:23:40 AM UTC 24 |
Aug 27 07:34:29 AM UTC 24 |
45997765379 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_stress_all.1173267509 |
|
|
Aug 27 07:14:39 AM UTC 24 |
Aug 27 07:34:30 AM UTC 24 |
55345347402 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2805342006 |
|
|
Aug 27 07:26:14 AM UTC 24 |
Aug 27 07:34:35 AM UTC 24 |
124330083667 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1800459237 |
|
|
Aug 27 07:32:35 AM UTC 24 |
Aug 27 07:34:39 AM UTC 24 |
4222444144 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.1152492468 |
|
|
Aug 27 07:11:23 AM UTC 24 |
Aug 27 07:35:08 AM UTC 24 |
63757543935 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1547656122 |
|
|
Aug 27 07:29:51 AM UTC 24 |
Aug 27 07:35:09 AM UTC 24 |
19436488726 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2202469309 |
|
|
Aug 27 07:32:35 AM UTC 24 |
Aug 27 07:35:27 AM UTC 24 |
14514634486 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.1282792991 |
|
|
Aug 27 07:13:20 AM UTC 24 |
Aug 27 07:35:43 AM UTC 24 |
24432050068 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.2280639499 |
|
|
Aug 27 07:30:52 AM UTC 24 |
Aug 27 07:35:54 AM UTC 24 |
52473796369 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.3114533481 |
|
|
Aug 27 07:13:32 AM UTC 24 |
Aug 27 07:35:57 AM UTC 24 |
59716282163 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.3486768899 |
|
|
Aug 27 07:30:07 AM UTC 24 |
Aug 27 07:36:00 AM UTC 24 |
19819951009 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.658290893 |
|
|
Aug 27 07:31:22 AM UTC 24 |
Aug 27 07:37:33 AM UTC 24 |
27236207013 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.3754311890 |
|
|
Aug 27 07:08:45 AM UTC 24 |
Aug 27 07:37:42 AM UTC 24 |
67576270350 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2736218386 |
|
|
Aug 27 07:19:47 AM UTC 24 |
Aug 27 07:39:37 AM UTC 24 |
60239679876 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3767758819 |
|
|
Aug 27 07:33:15 AM UTC 24 |
Aug 27 07:40:02 AM UTC 24 |
30108949904 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.1967478673 |
|
|
Aug 27 07:15:51 AM UTC 24 |
Aug 27 07:40:05 AM UTC 24 |
61376401488 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_perf.104935026 |
|
|
Aug 27 07:25:12 AM UTC 24 |
Aug 27 07:40:16 AM UTC 24 |
25172353578 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_perf.609258077 |
|
|
Aug 27 07:31:43 AM UTC 24 |
Aug 27 07:41:43 AM UTC 24 |
51462773583 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3964233266 |
|
|
Aug 27 07:29:54 AM UTC 24 |
Aug 27 07:44:40 AM UTC 24 |
23246244276 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.542241197 |
|
|
Aug 27 07:20:16 AM UTC 24 |
Aug 27 07:44:49 AM UTC 24 |
15540646519 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_stress_all.4254521483 |
|
|
Aug 27 07:27:33 AM UTC 24 |
Aug 27 07:45:53 AM UTC 24 |
67616422756 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1526561 |
|
|
Aug 27 07:31:59 AM UTC 24 |
Aug 27 07:47:39 AM UTC 24 |
57259184188 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_stress_all.3016190274 |
|
|
Aug 27 07:31:56 AM UTC 24 |
Aug 27 07:48:02 AM UTC 24 |
14692986793 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.3407459567 |
|
|
Aug 27 07:30:49 AM UTC 24 |
Aug 27 07:48:15 AM UTC 24 |
34676833331 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.3692653890 |
|
|
Aug 27 07:21:51 AM UTC 24 |
Aug 27 07:49:19 AM UTC 24 |
67487747320 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.158326108 |
|
|
Aug 27 07:29:17 AM UTC 24 |
Aug 27 08:00:14 AM UTC 24 |
44415964740 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.4094863346 |
|
|
Aug 27 07:33:33 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
30550260 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1800642370 |
|
|
Aug 27 07:33:33 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
28008860 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2097763281 |
|
|
Aug 27 07:33:32 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
438604917 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3427143775 |
|
|
Aug 27 07:33:33 AM UTC 24 |
Aug 27 07:33:35 AM UTC 24 |
61328712 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1773785817 |
|
|
Aug 27 07:33:32 AM UTC 24 |
Aug 27 07:33:36 AM UTC 24 |
815606359 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1630990143 |
|
|
Aug 27 07:33:35 AM UTC 24 |
Aug 27 07:33:38 AM UTC 24 |
54922566 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2612148076 |
|
|
Aug 27 07:33:35 AM UTC 24 |
Aug 27 07:33:38 AM UTC 24 |
280396991 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.464021044 |
|
|
Aug 27 07:33:37 AM UTC 24 |
Aug 27 07:33:39 AM UTC 24 |
27288390 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.292199553 |
|
|
Aug 27 07:33:37 AM UTC 24 |
Aug 27 07:33:39 AM UTC 24 |
19435339 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2639693841 |
|
|
Aug 27 07:33:37 AM UTC 24 |
Aug 27 07:33:39 AM UTC 24 |
29639918 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3487552650 |
|
|
Aug 27 07:33:36 AM UTC 24 |
Aug 27 07:33:39 AM UTC 24 |
98082649 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.157548696 |
|
|
Aug 27 07:33:37 AM UTC 24 |
Aug 27 07:33:40 AM UTC 24 |
80106893 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3246700331 |
|
|
Aug 27 07:33:36 AM UTC 24 |
Aug 27 07:33:40 AM UTC 24 |
82014418 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.3437785058 |
|
|
Aug 27 07:33:34 AM UTC 24 |
Aug 27 07:33:41 AM UTC 24 |
951993400 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1332810839 |
|
|
Aug 27 07:33:40 AM UTC 24 |
Aug 27 07:33:42 AM UTC 24 |
19187142 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1771599804 |
|
|
Aug 27 07:33:40 AM UTC 24 |
Aug 27 07:33:42 AM UTC 24 |
68401309 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3245206371 |
|
|
Aug 27 07:33:40 AM UTC 24 |
Aug 27 07:33:43 AM UTC 24 |
73643003 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.69286167 |
|
|
Aug 27 07:33:39 AM UTC 24 |
Aug 27 07:33:43 AM UTC 24 |
226864024 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4017198753 |
|
|
Aug 27 07:33:39 AM UTC 24 |
Aug 27 07:33:43 AM UTC 24 |
722786071 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1167123111 |
|
|
Aug 27 07:33:41 AM UTC 24 |
Aug 27 07:33:43 AM UTC 24 |
46322760 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2465505688 |
|
|
Aug 27 07:33:41 AM UTC 24 |
Aug 27 07:33:44 AM UTC 24 |
31682839 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3089368841 |
|
|
Aug 27 07:33:40 AM UTC 24 |
Aug 27 07:33:44 AM UTC 24 |
260313126 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.232750114 |
|
|
Aug 27 07:33:58 AM UTC 24 |
Aug 27 07:34:02 AM UTC 24 |
50358180 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.406364991 |
|
|
Aug 27 07:33:40 AM UTC 24 |
Aug 27 07:33:44 AM UTC 24 |
879098654 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2572706013 |
|
|
Aug 27 07:33:43 AM UTC 24 |
Aug 27 07:33:45 AM UTC 24 |
291687540 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2389081774 |
|
|
Aug 27 07:33:42 AM UTC 24 |
Aug 27 07:33:46 AM UTC 24 |
63226896 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1228765694 |
|
|
Aug 27 07:33:43 AM UTC 24 |
Aug 27 07:33:46 AM UTC 24 |
89173376 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.4275390700 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:46 AM UTC 24 |
17084692 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.3659869691 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:46 AM UTC 24 |
17311840 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.4294151249 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:47 AM UTC 24 |
21761021 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2067168198 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:47 AM UTC 24 |
48260145 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3129777120 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:48 AM UTC 24 |
109315670 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.2066218447 |
|
|
Aug 27 07:33:46 AM UTC 24 |
Aug 27 07:33:48 AM UTC 24 |
83186599 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.1544534250 |
|
|
Aug 27 07:33:44 AM UTC 24 |
Aug 27 07:33:48 AM UTC 24 |
82122123 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1525989650 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:49 AM UTC 24 |
38946504 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3538700727 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:49 AM UTC 24 |
18692859 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2889578482 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:49 AM UTC 24 |
20585450 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.330863869 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:50 AM UTC 24 |
23219131 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.3363068492 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:50 AM UTC 24 |
44890720 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2854065880 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:51 AM UTC 24 |
287318262 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3358453542 |
|
|
Aug 27 07:33:49 AM UTC 24 |
Aug 27 07:33:51 AM UTC 24 |
86671878 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3531680056 |
|
|
Aug 27 07:33:49 AM UTC 24 |
Aug 27 07:33:51 AM UTC 24 |
680828802 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2206468200 |
|
|
Aug 27 07:33:47 AM UTC 24 |
Aug 27 07:33:52 AM UTC 24 |
135364170 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2542240723 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:52 AM UTC 24 |
21446110 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1004476159 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:52 AM UTC 24 |
75420960 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1551881045 |
|
|
Aug 27 07:33:46 AM UTC 24 |
Aug 27 07:33:53 AM UTC 24 |
404343507 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.457386152 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:53 AM UTC 24 |
17942838 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.352912351 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:53 AM UTC 24 |
27631618 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.792821241 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:53 AM UTC 24 |
67743539 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2855170758 |
|
|
Aug 27 07:33:51 AM UTC 24 |
Aug 27 07:33:54 AM UTC 24 |
32189041 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.4030953723 |
|
|
Aug 27 07:33:50 AM UTC 24 |
Aug 27 07:33:54 AM UTC 24 |
128142708 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2720380594 |
|
|
Aug 27 07:33:53 AM UTC 24 |
Aug 27 07:33:55 AM UTC 24 |
45696384 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3827602786 |
|
|
Aug 27 07:33:53 AM UTC 24 |
Aug 27 07:33:55 AM UTC 24 |
59317262 ps |